QP.

CODE
B.E / B.Tech. PRACTICAL END SEMESTER EXAMINATIONS, OCTOBER / NOVEMBER 2018
Third Semester
Computer Science and Engineering
CS8382 - DIGITAL SYSTEMS LABORATORY
(Common to Information Technology)
(Regulations - 2017)

Time : 3 Hours Max. Marks 100

Aim/Principle/Apparatus Tabulation/Circuit/ Calculation Viva-Voce Record Total

required/Procedure Program/Drawing & Results
20 40 20 10 10 100

1. i) Implement the following identities using truth table

a) DeMorgan’s theorem for three variables
b) Associative Law
ii) Draw the logic diagram of Full Adder and implement it using logic gates.

2. i) Design and implement half adder and full subtractor with its truth table.
ii) Write a HDL program to simulate 4:1 Multiplexer.

3. i) Design a 4-bit Magnitude Comparator to compare two 4-bit numbers.

ii) Using HDL, simulate half adder.

4. i) Simulate two to four-line decoder using HDL.

ii) Design and implement a combinational circuit to convert BCD to excess-3.

5. i) Implement the Serial In Serial Out shift register.

ii) Simulate Half adder using dataflow description.

6. Design the 3-bit asynchronous up/down counter and implement it.

7. i) Design and implement excess-3 to BCD converter.

ii) Verify the truth table of Half subtractor using logic gates.

8. i) Validate a combinational circuit that converts a four bit binary code to gray code.
ii) Write a HDL gate level description of 4x1 multiplexer.
9. Design and implement the Serial In Parallel Out and Parallel In Parallel Out shift register.

10. Write a HDL program to simulate 3-bit synchronous up/down counter.

11. Implement even and odd parity generator and checker with its logic diagram and truth tables.

12. i) Verify a HDL model for Serial In Serial Out shift register using simulation.
ii) Implement Data selector circuit with suitable logic diagrams.

13. i) Simulate 4x1 multiplexer using HDL.

ii) Implement the Serial In Serial Out shift register.

14. Implement 4-bit binary adder/subtractor and simulate the same using HDL.

15. i) Design a Full subtractor circuit and simulate it using description language.
ii) Design and implement a combinational circuit that converts four bit gray code to binary code.

16. Implement the Serial In Serial Out and Parallel In Serial Out shift register.

17. i) Write a HDL program to compare the magnitude of three numbers and simulate it
ii) Verify De-Morgan’s theorem using basic gates.

18. Design a sequential circuit that gives serial and parallel outputs when serial inputs are fed in the
input of the circuit.

19. i) Design and implement gray to binary code conversion.

ii) Verify the truth table of Full subtractor using logic gates.

20. i) Design and implement odd parity generator and checker with its logic diagram and truth tables.
ii) Verify the truth table of Half subtractor using logic gates