Sei sulla pagina 1di 52
A B C D E 1 1 Compal Confidential Schematics Document 2 2 NIWE1 Arrandale
A
B
C
D
E
1
1
Compal Confidential
Schematics Document
2
2
NIWE1
Arrandale
with Intel IBEX PEAK-M core logic
3
3
REV:0.3
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics,Ltd.
Compal Electronics,Ltd.
Compal Electronics,Ltd.
2008/03/25
2008/03/25
2008/03/25
2008/04/
2008/04/
2008/04/
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Cover Sheet
Cover Sheet
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.3
0.3
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-5751
LA-5751
LA-5751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Thursday, October 29, 2009
Thursday, October 29, 2009
Thursday, October 29, 2009
Sheet
Sheet
Sheet
1
1
1
of
of
of
51
51
51
A
B
C
D
E
A B C D E Compal confidential POWER BD: CARD READER BD: CAP SENSOR BD:
A
B
C
D
E
Compal confidential
POWER BD:
CARD READER BD:
CAP SENSOR BD:
File Name :
POWER BTN
NOVO BTN
POWER MANAGE BTN
ENE UB6250/52
HP JACK
ZZZ1
ZZZ1
MIC JACK
Intel
VRAM 64*16
14W_PCB_LA5751P
14W_PCB_LA5751P
DDR3*4
Arrandale
VOLUME UP
VOLUME DOWN
MUTE
AUDIO ENHANCE
BUTTON & LED
1
Clock Generator
1
ZZZ
ZZZ
page23
(UMA/DIS)
PCI-E X16
RTM890N
HYN@
HYN@
page12
X76_H512
X76_H512
NVidia N11M-GE1
Socket-rPGA989
page19~23
37.5mm*37.5mm
DDR3-SO-DIMM X2
BANK 0, 1, 2, 3
level shift IC
page 10,11
page5~9
Dual Channel
HDMI
ASM1442
UP TO 8G
CONN
100MHz
DDR3-800(1.5V)
page25
FDI *8
DMI *4
2.7GT/s
DDR3-1066(1.5V)
page24
CRT Connector
2Channel Speaker
page33
page26
2
Intel Ibex Peak M
2
AZALIA
Audio Codec
LVDS
CONEXTAN
Analog MIC_Int
page33
Connector
page27
FCBGA 951
CX20671
page33
PCI Express
Mini card Slot 1
25mm*25mm
6*PCI-E BUS
14*USB2.0
CMOS Camera
page28
page27
PCI Express
Mini card Slot 2
6*SATA serial
BlueTooth CONN
page 13~18
page37
page28
USB CONN X1(Right)
SPI ROM
page37
BIOS
LPC BUS
page13
USB PORT X1(Left)
SIM Card
3
3
page37
page28
USB(WWAN)
EC
RTL8103EL/8111DL
New Card X1
ENE KB926D
10/100/1G LAN
page28
page34
Card Reader/Audio Jack SB
CONN
page29
WWAN
ENE UB6250/52
page28
MS/MS
HP X 1+
MIC_Ext X1
pro/SD/SD
Int.KBD
RJ45 CONN
pro/mmc/XD
page30
page35
page38
EMC1403
SPI ROM
ESATA HDD AND USB CONN
Thermal Sensor
EC
page36
page37
SATA HDD CONN
page31
page32
SATA ODD CONN
Touch Pad
4
4
page32
page35
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2008/03/24
2008/03/24
2008/03/24
2008/04/
2008/04/
2008/04/
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
MB Block Diagram
MB Block Diagram
MB Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.3
0.3
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-5751
LA-5751
LA-5751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Thursday, October 29, 2009
Thursday, October 29, 2009
Thursday, October 29, 2009
Sheet
Sheet
Sheet
2
2
2
of
of
of
51
51
51
A
B
C
D
E
A B C D E DDR3 Voltage Rails SMBUS Control Table N10x NEW WLAN Cap
A
B
C
D
E
DDR3 Voltage Rails
SMBUS Control Table
N10x
NEW
WLAN
Cap sensor
PCH
Thermal
CARD
SOURCE
RAM M2
BATT
KE926
SODIMM
CLK CHIP
N10x
WWAN
board
+5VS
Sensor
+3VS
SMB_EC_CK1
X
V
X
X
X
X
X
X
X
X
X
power
KB926
+1.5VS
SMB_EC_DA1
plane
+3VALW
+3VALW
+VCCP
SMB_EC_CK2
X
X
X
X
X
X
X
X
X
X
V
KB926
1
+5VALW
+1.5V
+CPU_CORE
1
SMB_EC_DA2
+3VALW
+3VALW
+B
+VGA_CORE
SMBCLK
V
X
X
V
V
X
X
X
X
V
X
PCH
+3VALW
+1.8VS
SMBDATA
+3VALW
+3VALW
+3VS
+3VS
+3VS
+0.75VS
SML0CLK
X
X
X
X
X
X
X
X
X
X
X
PCH
State
+1.05VS
SML0DATA
+3VALW
SML1CLK
X
X
V
X
X
X
V
X
V
X
X
PCH
SML1DATA
+3VALW
+3VALW
+3VS
+3VS
S0
O
O
O
O
I2C / SMBUS ADDRESSING
S3
O
O
O
X
DEVICE
HEX
ADDRESS
2
S5 S4/AC
2
O
O
X
X
DDR SO-DIMM 0
A0
1
0 1 0 0 0 0 0
S5 S4/ Battery only
O
X
X
X
DDR SO-DIMM 1
A4
1 0 1 0 0 1 0 0
CLOCK GENERATOR (EXT.)
D2
1
1 0 1 0 0 1 0
S5 S4/AC & Battery
don't exist
X
X
X
X
@ FUNCTION
Structure
Description
NON-USE
45@
45 BOM
BT@
Blue Tooth function
3G@
3G function (WWAN)
CAP@
CAP Sensor function
PCIE PORT LIST
USB PORT LIST
CMOS@
CMOS CAMERA function
ESATA@
E-SATA function
PORT
DEVICE
PORT
DEVICE
3
3
HDMI@
HDMI function (UMA or DIS)
UMA_HDMI@
HDMI function (UMA only)
1
0
RIGHT SIDE
X76@
X76 BOM
2
WLAN
1
LEFT SIDE
100@
10/100 LAN function
3
LAN
2
CMOS
GIGA@
GIGA LAN function
4
3G
3
LEFT SIDE
UMA@
UMA only (Arrandale)
5
NEW CARD
4
RIGHT SIDE
DIS@
DIS only (Arrandale)
6
5
CARD READER
7
6
8
7
8
WIRELESS
9
10
NEW CARD
11
BT
SKU
12
13
3G
Arrandale(dGPU)
DIS@
4
4
DIS only
Arrandale(iGPU)
UMA@
UMA only
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2008/03/24
2008/03/24
2008/03/24
2008/04/
2008/04/
2008/04/
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
MB Notes List
MB Notes List
MB Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
B
B
0.3
0.3
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-5751
LA-5751
LA-5751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Thursday, October 29, 2009
Thursday, October 29, 2009
Thursday, October 29, 2009
Sheet
Sheet
Sheet
3
3
3
of
of
of
51
51
51
A
B
C
D
E
A B C D E VGA and DDR3 Voltage Rails (N11x GPIO) Performance Mode P0
A
B
C
D
E
VGA and DDR3 Voltage Rails
(N11x GPIO)
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
FBVDDQ
PCI Express
I/O and
I/O and
Other
GPIO
I/O
ACTIVE
Function Description
GPU
Mem
NVCLK
FBVDD
(GPU+Mem)
(1.05V)
PLLVDD
PLLVDD
(4)
(1,5)
/MCLK
NVVDD
(1.5V)
(1.5V)
(6)
(1.8V)
(1.05V)
(3.3V)
GPIO0
N/A
N/A
Products
(W)
(W)
(MHz)
(V)
(A)
(W)
(A)
(W)
(A)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
GPIO1
IN
-
Hot plug detect for IFP link C
N11M-GE1
64bit
14.02
2.16
TBD
TBD
12.9
12.26
0.66
0.99
1.3
1.95
530
0.56
84
0.15
140
0.15
38
0.13
512MB
GPIO2
OUT
H
Panel Back-Light brightness(PWM capable)
DDR3
1
1
GPIO3
OUT
H
Panel Power Enable
GPIO5 GPIO6
GPIO4
OUT
H
Panel Back-Light On/Off (PWM)
GPU_VID0
GPU_VID1
VGA_CORE
P-State
Device ID
GPIO5
OUT
-
GPU VID0
0 0.8V
Deep P12
0
N11M-GE1/LP1
1 0.85V
P8
0
GPIO6
OUT
-
GPU VID1
0x0A7D
(40nm)
1 1.03V
P0
1
GPIO7
OUT
N/A
GPIO8
I/O
N/A
GPIO9
OUT
N/A
GPIO10
OUT
N/A
GPIO11
I/O
-
Reserve 10K pull low.
GPIO12
IN
N/A
GPIO13
OUT
N/A
2
2
GPIO14
OUT
-
Reserve 10K pull low.
GPIO15
IN
N/A
GPIO16
OUT
N/A
GPIO17
IN
-
PAD
The ramp time for any rail must be more than 40us
Power Sequence
GPIO18
IN
N/A
GPIO19
IN
N/A
(+3VS) VDD33
PEX_VDD can ramp up any time
(1.05VS) PEX_VDD
tNVVDD
3
3
(+VGA_CORE) NVVDD
tNV-IFPAB_IOVDD
(1.8VS)IFPAB_IOVDD
tNV-FBVDDQ
(1.5VS) FBVDDQ
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2009/03/16
2009/03/16
2009/03/16
2010/03/15
2010/03/15
2010/03/15
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
VGA Notes List
VGA Notes List
VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
B
B
0.3
0.3
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-5751
LA-5751
LA-5751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Thursday, October 29, 2009
Thursday, October 29, 2009
Thursday, October 29, 2009
Sheet
Sheet
Sheet
4
4
4
of
of
of
51
51
51
A
B
C
D
E

1

B

A

DDR3 Compensation Signals SM_RCOMP0 1 2 R567R567 100_0402_1%100_0402_1% SM_RCOMP1 1 2 R566R566
DDR3 Compensation Signals
SM_RCOMP0
1
2
R567R567
100_0402_1%100_0402_1%
SM_RCOMP1
1
2
R566R566
24.9_0402_1%24.9_0402_1%
SM_RCOMP2
1
2
R565R565
130_0402_1%130_0402_1%
Layout Note:Please these
resistors near Processor
+VCCP
PM_EXTTS#0
1 2
R561R561
10K_0402_5%10K_0402_5%
PM_EXTTS#1
1 2
R562R562
10K_0402_5%10K_0402_5%
XDP_PREQ#
R136R136
1 @@
2
51_0402_1%51_0402_1%
XDP_TMS
R138R138
1 @@
2
51_0402_1%51_0402_1%
XDP_TDI
R556R556
1 @@
2
51_0402_1%51_0402_1%
XDP_TDO
R134R134
1 2
51_0402_5%51_0402_5%
XDP_TCK
R57R57
1 @@
2
51_0402_1%51_0402_1%
XDP_TRST#
R133R133
1 2
51_0402_5%51_0402_5%
R137
R137
XDP_DBRESET#
1 @ @
2
1K_0402_5%
1K_0402_5%
+3VS

CHECK INTEL DOCUMENT #385422 Debug Port Design Guide Rev1.3

D

C

INTEL DOCUMENT #385422 Debug Port Design Guide Rev1.3 D C B A 5 4 3 2

B

A

5 4 3 2 D Layout rule:10mil width trace length < 0.5", spacing 20mil JCPU1B
5
4
3
2
D
Layout rule:10mil width trace
length < 0.5", spacing 20mil
JCPU1B
JCPU1B
20_0402_1%20_0402_1%
1 R560R560
2
COMP3
AT23
COMP3
A16
CLK_CPU_BCLK
BCLK
CLK_CPU_BCLK
<16>
20_0402_1%20_0402_1%
1 R558R558
2
COMP2
AT24
B16
CLK_CPU_BCLK#
COMP2
BCLK#
CLK_CPU_BCLK#
<16>
49.9_0402_1%49.9_0402_1%
1
R548R548
2
COMP1
G16
AR30
CLK_CPU_ITP
T17T17
PADPAD
COMP1
BCLK_ITP
AT30
CLK_CPU_ITP#
T18T18
PADPAD
BCLK_ITP#
49.9_0402_1%49.9_0402_1%
1
R557R557
2
COMP0
AT26
COMP0
E16
CLK_EXP
PEG_CLK
CLK_EXP
<14>
D16
CLK_EXP#
PEG_CLK#
CLK_EXP#
<14>
TP_SKTOCC#
AH24
SKTOCC#
A18
DPLL_REF_SSCLK
A17
DPLL_REF_SSCLK#
2
1
H_CATERR#
AK14
+VCCP
CATERR#
49.9_0402_1%49.9_0402_1%
R163R163
pins unused by
Clarksfield on the
rPGA989 Package
3
R564R564
0_0402_5%0_0402_5%
F6
SM_DRAMRST#
SM_DRAMRST#
1 2
H_PECI_ISO
AT15
<16>
H_PECI
PECI
AL1
SM_RCOMP0
SM_RCOMP[0]
2 R569R569
1
68_0402_5%68_0402_5%
AM1
SM_RCOMP1
+VCCP
SM_RCOMP[1]
AN1
SM_RCOMP2
SM_RCOMP[2]
H_PROCHOT#
AN26
<34,48>
H_PROCHOT#
PROCHOT#
AN15
PM_EXTTS#0
PM_EXT_TS#[0]
AP15
PM_EXTTS#1
1
2
PM_EXT_TS#[1]
PM_EXTTS#1_R
<10,11>
R563R563
0_0402_5%0_0402_5%
H_THERMTRIP#
AK15
<16>
H_THERMTRIP#
THERMTRIP#
AT28
XDP_PRDY#
PRDY#
T19T19
PADPAD
C
AP27
XDP_PREQ#
PREQ#
AN28
XDP_TCK
TCK
2
1
H_CPURST#_R
AP26
AP28
XDP_TMS
+VCCP
RESET_OBS#
TMS
68_0402_5%68_0402_5%
R135R135
AT27
XDP_TRST#
TRST#
MISC
MISC
THERMAL
THERMAL
R187
R187
H_PM_SYNC_R
XDP_TDI
PWR MANAGEMENT
PWR MANAGEMENT
1
2
AL15
AT29
<15>
H_PM_SYNC
PM_SYNC
TDI
0_0402_5%
0_0402_5%
AR27
XDP_TDO
TDO
AR29
TDI_M
1 R190
R190
2
VCCPWRGOOD_1
AN14
AP29
R555R555
2
1
0_0402_5%0_0402_5%
VCCPWRGOOD_1
TDO_M
0_0402_5%
0_0402_5%
AN25
XDP_DBRESET#
DBR#
1 R139
R139
2
VCCPWRGOOD_0
AN27
<16>
H_CPUPWRGD
VCCPWRGOOD_0
0_0402_5%
0_0402_5%
AJ22
XDP_BPM#0
BPM#[0]
1 R191
R191
2
VDDPWRGOOD_R
AK13
AK22
XDP_BPM#1
<15>
PM_DRAM_PWRGD
SM_DRAMPWROK
BPM#[1]
0_0402_5%
0_0402_5%
AK24
XDP_BPM#2
BPM#[2]
AJ24
XDP_BPM#3
BPM#[3]
2
1
VTT_POK
AM15
AJ25
XDP_BPM#4
<46>
VCCP_POK
VTTPWRGOOD
BPM#[4]
R184
R184
AH22
XDP_BPM#5
BPM#[5]
FROM POWER VTT
POWER GOOD SIGNAL
1K_0402_1%
1K_0402_1%
AK23
XDP_BPM#6
BPM#[6]
AM26
AH23
XDP_BPM#7
TAPPWRGOOD
BPM#[7]
R183
R183
R185
R185
560_0402_5%
560_0402_5%
1
2
PLT_RST#_R
AL14
<16,19,28,29>
BUF_PLT_RST#
RSTIN#
1.5K_0402_5%
1.5K_0402_5%
R186
R186
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
ME@
ME@
750_0402_1%
750_0402_1%
1
2
JTAG & BPM
JTAG & BPM
DDR3
DDR3
CLOCKS
CLOCKS
MISC
MISC
12
12
5 For Intel S3 Power Reduction. +1.5V +3VALW @ @ R193 R193 1.1K_0402_1% 1.1K_0402_1% U8
5 For Intel S3 Power Reduction.
+1.5V
+3VALW
@ @
R193
R193
1.1K_0402_1%
1.1K_0402_1%
U8
U8
2
R195
R195
B
4
DRAM_PWRGD
1
2
VDDPWRGOOD_R
<46>
VCCP_POK
Y
1
A
1.5K_0402_1%
1.5K_0402_1%
MC74VHC1G08DFT2G SC70 5P
MC74VHC1G08DFT2G SC70 5P
@ @
R194
R194
R192
R192
3K_0402_1%
3K_0402_1%
750_0402_1%
750_0402_1%
+5VALW
R610
R610
10K_0402_5%
10K_0402_5%
S3_0.75V_EN
S3_0.75V_EN
<44>
D D
VCCP_POK
2
G G
Q42
Q42
S
S
2N7002_SOT23
2N7002_SOT23
3
5
G
P
13
12
12
12
12
+1.5V For Intel S3 Power Reduction. 3 R301 R301 1K_0402_1% 1K_0402_1% @ @ 1 2
+1.5V
For Intel S3 Power Reduction.
3
R301
R301
1K_0402_1%
1K_0402_1%
@
@
1
2
0_0402_5%
0_0402_5%
R300
R300
DDR3 CONNECTER
DRAMRST#
1
3
SM_DRAMRST#
<10,11>
DRAMRST#
Q27
Q27
2N7002_SOT23
2N7002_SOT23
2
1
PCH GPIO CONTROL
R283R283
100K_0402_5%100K_0402_5%
1
2
DRAMRST_CNTRL_R
<16>
DRAMRST_CNTRL_PCH
R281R281
0_0402_5%0_0402_5%
1
2
<34>
DRAMRST_CNTRL_EC
R282R282
@@
0_0402_5%0_0402_5%
EC GPIO CONTROL
1
0.01U_0402_16V7K
0.01U_0402_16V7K
C338
C338
2
6
1
2
D
D
2
G G
S
S

Security Classification

Security Classification

Security Classification

Compal Secret Data

Compal Secret Data

Compal Secret Data

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Issued Date

Issued Date

Issued Date

2008/10/31

2008/10/31

2008/10/31

Deciphered Date

Deciphered Date

Deciphered Date

2009/10/31

2009/10/31

2009/10/31

Title

Title

Title

Arrandale(1/5)-Thermal/XDP

Arrandale(1/5)-Thermal/XDP

Arrandale(1/5)-Thermal/XDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Date:

Date:

Size

Size

Size

Document Number

Document Number

Document Number

LA-5751

LA-5751

LA-5751

Rev

Rev

Rev

0.3 0.3

0.3

Custom

Custom

Custom

Friday, October 30, 2009

Friday, October 30, 2009

Friday, October 30, 2009

Sheet

Sheet

Sheet

5

5 5

of

of

of

51

51

51

5

4

3

2

1

5 4 3 2 1 Layout rule:trace length < 0.5" JCPU1A JCPU1A JCPU1E JCPU1E B26
5
4
3
2
1
Layout rule:trace
length < 0.5"
JCPU1A
JCPU1A
JCPU1E
JCPU1E
B26
EXP_ICOMPI
1
R544R544
2
49.9_0402_1%49.9_0402_1%
PEG_ICOMPI
A26
AJ13
PEG_ICOMPO
RSVD32
A24
B27
AJ12
<15>
DMI_CRX_PTX_N0
DMI_RX#[0]
PEG_RCOMPO
RSVD33
C23
A25
EXP_RBIAS
1
R545R545
2
750_0402_1%750_0402_1%
<15>
DMI_CRX_PTX_N1
DMI_RX#[1]
PEG_RBIAS
B22
AP25
<15>
DMI_CRX_PTX_N2
PCIE_CRX_GTX_N[0
15]
<19>
DMI_RX#[2]
RSVD1
A21
K35
PCIE_CRX_GTX_N15
AL25
AH25
<15>
DMI_CRX_PTX_N3
DMI_RX#[3]
PEG_RX#[0]
RSVD2
RSVD34
J34
PCIE_CRX_GTX_N14
AL24
AK26
PEG_RX#[1]
RSVD3
RSVD35
B24
J33
PCIE_CRX_GTX_N13
AL22
<15>
DMI_CRX_PTX_P0
DMI_RX[0]
PEG_RX#[2]
RSVD4
D23
G35
PCIE_CRX_GTX_N12
AJ33
AL26
<15>
DMI_CRX_PTX_P1
DMI_RX[1]
PEG_RX#[3]
RSVD5
RSVD36
D
D
B23
G32
PCIE_CRX_GTX_N11
AG9
AR2
<15>
DMI_CRX_PTX_P2
DMI_RX[2]
PEG_RX#[4]
RSVD6
RSVD_NCTF_37
A22
F34
PCIE_CRX_GTX_N10
M27
<15>
DMI_CRX_PTX_P3
DMI_RX[3]
PEG_RX#[5]
RSVD7
F31
PCIE_CRX_GTX_N9
L28
AJ26
PEG_RX#[6]
RSVD8
RSVD38
D24
D35
PCIE_CRX_GTX_N8
J17
AJ27
<15>
DMI_CTX_PRX_N0
DMI_TX#[0]
PEG_RX#[7]
SA_DIMM_VREF
RSVD39
G24
E33
PCIE_CRX_GTX_N7
H17
<15>
DMI_CTX_PRX_N1
DMI_TX#[1]
PEG_RX#[8]
SB_DIMM_VREF
F23
C33
PCIE_CRX_GTX_N6
G25
<15>
DMI_CTX_PRX_N2
DMI_TX#[2]
PEG_RX#[9]
RSVD11
H23
D32
PCIE_CRX_GTX_N5
G17
<15>
DMI_CTX_PRX_N3
DMI_TX#[3]
PEG_RX#[10]
RSVD12
B32
PCIE_CRX_GTX_N4
E31
AP1
PEG_RX#[11]
RSVD13
RSVD_NCTF_40
D25
C31
PCIE_CRX_GTX_N3
E30
AT2
<15>
DMI_CTX_PRX_P0
DMI_TX[0]
PEG_RX#[12]
RSVD14
RSVD_NCTF_41
F24
B28
PCIE_CRX_GTX_N2
<15>
DMI_CTX_PRX_P1
DMI_TX[1]
PEG_RX#[13]
E23
B30
PCIE_CRX_GTX_N1
AT3
<15>
DMI_CTX_PRX_P2
DMI_TX[2]
PEG_RX#[14]
RSVD_NCTF_42
G23
A31
PCIE_CRX_GTX_N0
AR1
<15>
DMI_CTX_PRX_P3
DMI_TX[3]
PEG_RX#[15]
RSVD_NCTF_43
PCIE_CRX_GTX_P[0
15]
<19>
J35
PCIE_CRX_GTX_P15
PEG_RX[0]
H34
PCIE_CRX_GTX_P14
PEG_RX[1]
H33
PCIE_CRX_GTX_P13
AL28
PEG_RX[2]
RSVD45
FDI_CTX_PRX_N0
E22
F35
PCIE_CRX_GTX_P12
CFG0
AM30
AL29
<15>
FDI_CTX_PRX_N0
FDI_TX#[0]
PEG_RX[3]
CFG[0]
RSVD46
FDI_CTX_PRX_N1
D21
G33
PCIE_CRX_GTX_P11
AM28
AP30
<15>
FDI_CTX_PRX_N1
FDI_TX#[1]
PEG_RX[4]
CFG[1]
RSVD47
FDI_CTX_PRX_N2
D19
E34
PCIE_CRX_GTX_P10
AP31
AP32
<15>
FDI_CTX_PRX_N2
FDI_TX#[2]
PEG_RX[5]
CFG[2]
RSVD48
FDI_CTX_PRX_N3
D18
F32
PCIE_CRX_GTX_P9
CFG3
AL32
AL27
<15>
FDI_CTX_PRX_N3
FDI_TX#[3]
PEG_RX[6]
CFG[3]
RSVD49
FDI_CTX_PRX_N4
G21
D34
PCIE_CRX_GTX_P8
CFG4
AL30
AT31
<15>
FDI_CTX_PRX_N4
FDI_TX#[4]
PEG_RX[7]
F33
PCIE Lane Numbers Reversed
CFG3-PCI Express Static Lane Reversal
CFG[4]
RSVD50
FDI_CTX_PRX_N5
E19
PCIE_CRX_GTX_P7
AM31
AT32
<15>
FDI_CTX_PRX_N5
FDI_TX#[5]
PEG_RX[8]
CFG[5]
RSVD51
FDI_CTX_PRX_N6
F21
B33
PCIE_CRX_GTX_P6
AN29
AP33
<15>
FDI_CTX_PRX_N6
FDI_TX#[6]
PEG_RX[9]
CFG[6]
RSVD52
FDI_CTX_PRX_N7
G18
D31
PCIE_CRX_GTX_P5
@
@
R59
R59
1
2
CFG7
AM32
AR33
<15>
FDI_CTX_PRX_N7
FDI_TX#[7]
PEG_RX[10]
CFG[7]
RSVD53
A32
PCIE_CRX_GTX_P4
3.01K_0402_1%
3.01K_0402_1%
AK32
AT33
PEG_RX[11]
CFG[8]
RSVD_NCTF_54
C30
PCIE_CRX_GTX_P3
AK31
AT34
PEG_RX[12]
CFG[9]
RSVD_NCTF_55
FDI_CTX_PRX_P0
D22
A28
PCIE_CRX_GTX_P2
AK28
AP35
<15>
FDI_CTX_PRX_P0
FDI_TX[0]
PEG_RX[13]
CFG[10]
RSVD_NCTF_56
FDI_CTX_PRX_P1
C21
B29
PCIE_CRX_GTX_P1
FOR ES1 SAMPLE ONLY
AJ28
AR35
<15>
FDI_CTX_PRX_P1
FDI_TX[1]
PEG_RX[14]
CFG[11]
RSVD_NCTF_57
FDI_CTX_PRX_P2
D20
A30
PCIE_CRX_GTX_P0
DIS@
AN30
AR32
<15>
FDI_CTX_PRX_P2
FDI_TX[2]
PEG_RX[15]
CFG[12]
RSVD58
FDI_CTX_PRX_P3
C18
AN32
<15>
FDI_CTX_PRX_P3
FDI_TX[3]
PCIE_CTX_GRX_N[0
15]
<19>
CFG[13]
FDI_CTX_PRX_P4
G22
L33
PCIE_CTX_GRX_C_N15
C527
C527
1 PCIE_CTX_GRX_N15
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AJ32
<15>
FDI_CTX_PRX_P4
FDI_TX[4]
PEG_TX#[0]
CFG[14]
FDI_CTX_PRX_P5
E20
M35
PCIE_CTX_GRX_C_N14
C540
C540
1 PCIE_CTX_GRX_N14
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AJ29
E15
<15>
FDI_CTX_PRX_P5
FDI_TX[5]
PEG_TX#[1]
CFG[15]
RSVD_TP_59
C
FDI_CTX_PRX_P6
F20
PCIE_CTX_GRX_C_N13
C529
C529
1 PCIE_CTX_GRX_N13
C
M33
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AJ30
F15
<15>
FDI_CTX_PRX_P6
FDI_TX[6]
PEG_TX#[2]
CFG[16]
RSVD_TP_60
FDI_CTX_PRX_P7
G19
M30
PCIE_CTX_GRX_C_N12
C542
C542
1 PCIE_CTX_GRX_N12
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AK30
A2
<15>
FDI_CTX_PRX_P7
FDI_TX[7]
PEG_TX#[3]
CFG[17]
KEY
L31
PCIE_CTX_GRX_C_N11
C531
C531
1 PCIE_CTX_GRX_N11
2
0.1U_0402_10V6K
0.1U_0402_10V6K
H16
D15
R189
R189
PEG_TX#[4]
RSVD_TP_86
RSVD62
FDI_FSYNC0
F17
K32
PCIE_CTX_GRX_C_N10
C544
C544
1 PCIE_CTX_GRX_N10
2
0.1U_0402_10V6K
0.1U_0402_10V6K
C15
0_0402_5%
0_0402_5%
<15>
FDI_FSYNC0
FDI_FSYNC[0]
PEG_TX#[5]
RSVD63
FDI_FSYNC1
E17
M29
PCIE_CTX_GRX_C_N9
C533
C533
1 PCIE_CTX_GRX_N9
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AJ15
RSVD64_R
2
@
@
1
<15>
FDI_FSYNC1
FDI_FSYNC[1]
PEG_TX#[6]
RSVD64
J31
PCIE_CTX_GRX_C_N8
C546
C546
1 PCIE_CTX_GRX_N8
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AH15
RSVD65_R
2
@
@
1
PEG_TX#[7]
RSVD65
FDI_INT
C17
K29
PCIE_CTX_GRX_C_N7
C535
C535
1 PCIE_CTX_GRX_N7
2
0.1U_0402_10V6K
0.1U_0402_10V6K
R188
R188
<15>
FDI_INT
FDI_INT
PEG_TX#[8]
H30
PCIE_CTX_GRX_C_N6
C562
C562
1 PCIE_CTX_GRX_N6
2
0.1U_0402_10V6K
0.1U_0402_10V6K
B19
0_0402_5%
0_0402_5%
PEG_TX#[9]
RSVD15
FDI_LSYNC0
F18
H29
PCIE_CTX_GRX_C_N5
C564
C564
1 PCIE_CTX_GRX_N5
2
0.1U_0402_10V6K
0.1U_0402_10V6K
R547
R547
A19
<15>
FDI_LSYNC0
FDI_LSYNC[0]
PEG_TX#[10]
RSVD16
FDI_LSYNC1
D17
F29
PCIE_CTX_GRX_C_N4
C555
C555
1 PCIE_CTX_GRX_N4
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0_0402_5%
0_0402_5%
<15>
FDI_LSYNC1
FDI_LSYNC[1]
PEG_TX#[11]
E28
PCIE_CTX_GRX_C_N3
C557
C557
1 PCIE_CTX_GRX_N3
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
@
@
2
H_RSVD17_R
A20
PEG_TX#[12]
RSVD17
D29
PCIE_CTX_GRX_C_N2
C561
C561
1 PCIE_CTX_GRX_N2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
@
@
2
H_RSVD18_R
B20
PEG_TX#[13]
RSVD18
D27
PCIE_CTX_GRX_C_N1
C548
C548
1 PCIE_CTX_GRX_N1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AA5
PEG_TX#[14]
RSVD_TP_66
C26
PCIE_CTX_GRX_C_N0
C559
C559
1 PCIE_CTX_GRX_N0
2
0.1U_0402_10V6K
0.1U_0402_10V6K
R546
R546
U9
AA4
PEG_TX#[15]
RSVD19
RSVD_TP_67
0_0402_5%
0_0402_5%
T9
R8
PCIE_CTX_GRX_P[0
15]
<19>
RSVD20
RSVD_TP_68
L34
PCIE_CTX_GRX_C_P15
C528
C528
1 PCIE_CTX_GRX_P15
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AD3
PEG_TX[0]
RSVD_TP_69
M34
PCIE_CTX_GRX_C_P14
C541
C541
1 PCIE_CTX_GRX_P14
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AC9
AD2
PEG_TX[1]
RSVD21
RSVD_TP_70
M32
PCIE_CTX_GRX_C_P13
C530
C530
1 PCIE_CTX_GRX_P13
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AB9
AA2
PEG_TX[2]
RSVD22
RSVD_TP_71
L30
PCIE_CTX_GRX_C_P12
C543
C543
1 PCIE_CTX_GRX_P12
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AA1
PEG_TX[3]
RSVD_TP_72
M31
PCIE_CTX_GRX_C_P11
C532
C532
1 PCIE_CTX_GRX_P11
2
0.1U_0402_10V6K
0.1U_0402_10V6K
R9
PEG_TX[4]
RSVD_TP_73
K31
PCIE_CTX_GRX_C_P10
C545
C545
1 PCIE_CTX_GRX_P10
2
0.1U_0402_10V6K
0.1U_0402_10V6K
AG7
PEG_TX[5]
RSVD_TP_74
M28
PCIE_CTX_GRX_C_P9
C534
C534
1 PCIE_CTX_GRX_P9
2
0.1U_0402_10V6K
0.1U_0402_10V6K
C1
AE3
PEG_TX[6]
RSVD_NCTF_23
RSVD_TP_75
H31
PCIE_CTX_GRX_C_P8
C547
C547
1 PCIE_CTX_GRX_P8
2
0.1U_0402_10V6K
0.1U_0402_10V6K
A3
PEG_TX[7]
RSVD_NCTF_24
K28
PCIE_CTX_GRX_C_P7
C536
C536
1 PCIE_CTX_GRX_P7
2
0.1U_0402_10V6K
0.1U_0402_10V6K
PEG_TX[8]
G30
PCIE_CTX_GRX_C_P6
C563
C563
1 PCIE_CTX_GRX_P6
2
0.1U_0402_10V6K
0.1U_0402_10V6K
V4
PEG_TX[9]
RSVD_TP_76
G29
PCIE_CTX_GRX_C_P5
C565
C565
1 PCIE_CTX_GRX_P5
2
0.1U_0402_10V6K
0.1U_0402_10V6K
V5
PEG_TX[10]
CFG Straps for PROCESSOR
RSVD_TP_77
F28
PCIE_CTX_GRX_C_P4
C556
C556
1 PCIE_CTX_GRX_P4
2
0.1U_0402_10V6K
0.1U_0402_10V6K
N2
PEG_TX[11]
RSVD_TP_78
E27
PCIE_CTX_GRX_C_P3
C558
C558
1 PCIE_CTX_GRX_P3
2
0.1U_0402_10V6K
0.1U_0402_10V6K
J29
AD5
PEG_TX[12]
RSVD26
RSVD_TP_79
D28
PCIE_CTX_GRX_C_P2
C560
C560
1 PCIE_CTX_GRX_P2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
J28
AD7
PEG_TX[13]
RSVD27
RSVD_TP_80
C27
PCIE_CTX_GRX_C_P1
C549
C549
1 PCIE_CTX_GRX_P1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
W3
PEG_TX[14]
RSVD_TP_81
C25
PCIE_CTX_GRX_C_P0
C550
C550
1 PCIE_CTX_GRX_P0
2
0.1U_0402_10V6K
0.1U_0402_10V6K
A34
W2
PEG_TX[15]
RSVD_NCTF_28
RSVD_TP_82
A33
N3
RSVD_NCTF_29
RSVD_TP_83
B
CFG0
B
1
@
@
2
AE5
RSVD_TP_84
R58
R58
3.01K_0402_1%
3.01K_0402_1%
C35
AD9
RSVD_NCTF_30
RSVD_TP_85
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
B35
RSVD_NCTF_31
ME@
ME@
PCI-Express Configuration Select
CFG0
1: Single PEG
0: Bifurcation enabled
AP34
VSS
Not applicable for Clarksfield Processor
CFG[1:0] 11=1*16 PEG
10=2*8 PEG
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
ME@
ME@
FDI_FSYNC0
R532R532
1 DIS@DIS@
2
1K_0402_5%1K_0402_5%
CFG3
1
2
R61R61
3.01K_0402_1%3.01K_0402_1%
FDI_FSYNC1
R536R536
1 DIS@DIS@
2
1K_0402_5%1K_0402_5%
CFG3-PCI Express Static Lane Reversal
FDI_INT
R534R534
1 DIS@DIS@
2
1K_0402_5%1K_0402_5%
CFG3
FDI_LSYNC0
R533R533
1 DIS@DIS@
1K_0402_5%1K_0402_5%
1: Normal Operation
0: Lane Numbers Reversed
15 -> 0, 14 ->1,
2
FDI_LSYNC1
R535R535
1 DIS@DIS@
2
1K_0402_5%1K_0402_5%
@
@
CFG4
DMI
DMI
Intel(R) FDI
Intel(R) FDI
1
2
R60
R60
3.01K_0402_1%
3.01K_0402_1%
CFG4-Display Port Presence
1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0: Enabled; An external Display Port
device is connected to the Embedded
Display Port
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2008/10/31
2008/10/31
2008/10/31
2009/10/31
2009/10/31
2009/10/31
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Arrandale(2/5)-DMI/PEG/FDI
Arrandale(2/5)-DMI/PEG/FDI
Arrandale(2/5)-DMI/PEG/FDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.3
0.3
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-5751
LA-5751
LA-5751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, October 30, 2009
Friday, October 30, 2009
Friday, October 30, 2009
Sheet
Sheet
Sheet
6
6
6
of
of
of
51
51
51
5
4
3
2
1
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
RESERVED
RESERVED
5 4 3 2 1 JCPU1D JCPU1D JCPU1C JCPU1C <11> DDR_B_D[0 63] SB_CK[0] M_CLK_DDR2 <11>
5
4
3
2
1
JCPU1D
JCPU1D
JCPU1C
JCPU1C
<11>
DDR_B_D[0 63]
SB_CK[0]
M_CLK_DDR2
<11>
D
D
W9
SA_CK[0]
AA6
M_CLK_DDR0
<10>
SB_CK#[0]
W8
M_CLK_DDR#2
<11>
AA7
DDR_B_D0
B5
M3
<10>
DDR_A_D[0 63]
SA_CK#[0]
M_CLK_DDR#0
<10>
SB_DQ[0]
SB_CKE[0]
DDR_CKE2_DIMMB
<11>
P7
DDR_B_D1
A5
SA_CKE[0]
DDR_CKE0_DIMMA
<10>
SB_DQ[1]
DDR_A_D0
A10
DDR_B_D2
C3
SA_DQ[0]
SB_DQ[2]
DDR_A_D1
C10
DDR_B_D3
B3
SA_DQ[1]
SB_DQ[3]
SB_CK[1]
<11>
DDR_A_D2
C7
DDR_B_D4
E4
SA_DQ[2]
SB_DQ[4]
SB_CK#[1]
V7
V6
M_CLK_DDR#3
<11>
DDR_A_D3
A7
DDR_B_D5
A6
M2
SA_DQ[3]
SA_CK[1]
<10>
SB_DQ[5]
SB_CKE[1]
DDR_CKE3_DIMMB
DDR_A_D4
M_CLK_DDR3
<11>
B10
Y5
A4
SA_DQ[4]
SA_CK#[1]
Y6
DDR_B_D6
M_CLK_DDR#1
<10>
SB_DQ[6]
DDR_A_D5
D10
P6
DDR_B_D7
C4
SA_DQ[5]
SA_CKE[1]
M_CLK_DDR1
DDR_CKE1_DIMMA
<10>
SB_DQ[7]
DDR_A_D6
E10
DDR_B_D8
D1
SA_DQ[6]
SB_DQ[8]
DDR_A_D7
A8
DDR_B_D9
D2
SA_DQ[7]
SB_DQ[9]
DDR_A_D8
D8
DDR_B_D10
F2
AB8
SA_DQ[8]
SB_DQ[10]
SB_CS#[0]
DDR_CS2_DIMMB#
<11>
DDR_A_D9
F10
AE2
DDR_B_D11
F1
AD6
SA_DQ[9]
SA_CS#[0]
DDR_CS0_DIMMA#
<10>
SB_DQ[11]
SB_CS#[1]
DDR_CS3_DIMMB#
<11>
DDR_A_D10
E6
AE8
DDR_B_D12
C2
SA_DQ[10]
SA_CS#[1]
DDR_CS1_DIMMA#
<10>
SB_DQ[12]
DDR_A_D11
F7
DDR_B_D13
F5
SA_DQ[11]
SB_DQ[13]
DDR_A_D12
E9
DDR_B_D14
F3
SA_DQ[12]
SB_DQ[14]
DDR_A_D13
B7
DDR_B_D15
G4
AC7
SA_DQ[13]
SB_DQ[15]
SB_ODT[0]
M_ODT2
<11>
DDR_A_D14
E7
AD8
DDR_B_D16
H6
AD1
SA_DQ[14]
SA_ODT[0]
M_ODT0
<10>
SB_DQ[16]
SB_ODT[1]
M_ODT3
<11>
DDR_A_D15
C6
AF9
DDR_B_D17
G2
SA_DQ[15]
SA_ODT[1]
M_ODT1
<10>
SB_DQ[17]
DDR_A_D16
H10
DDR_B_D18
J6
SA_DQ[16]
SB_DQ[18]
DDR_A_D17
G8
DDR_B_D19
J3
SA_DQ[17]
SB_DQ[19]
DDR_A_D18
K7
DDR_B_D20
G1
SA_DQ[18]
SB_DQ[20]
DDR_B_DM[0
7]
<11>
DDR_A_D19
J8
DDR_B_D21
G5
D4
DDR_B_DM0
SA_DQ[19]
SB_DQ[21]
SB_DM[0]
DDR_A_D20
G7
DDR_B_D22
J2
E1
DDR_B_DM1
SA_DQ[20]
SB_DQ[22]
SB_DM[1]
DDR_A_D21
G10
DDR_B_D23
J1
H3
DDR_B_DM2
SA_DQ[21]
DDR_A_DM[0
7]
<10>
SB_DQ[23]
SB_DM[2]
DDR_A_D22
J7
B9
DDR_A_DM0
DDR_B_D24
J5
K1
DDR_B_DM3
SA_DQ[22]
SA_DM[0]
SB_DQ[24]
SB_DM[3]
DDR_A_D23
J10
D7
DDR_A_DM1
DDR_B_D25
K2
AH1
DDR_B_DM4
SA_DQ[23]
SA_DM[1]
SB_DQ[25]
SB_DM[4]
DDR_A_D24
L7
H7
DDR_A_DM2
DDR_B_D26
L3
AL2
DDR_B_DM5
SA_DQ[24]
SA_DM[2]
SB_DQ[26]
SB_DM[5]
DDR_A_D25
M6
M7
DDR_A_DM3
DDR_B_D27
M1
AR4
DDR_B_DM6
SA_DQ[25]
SA_DM[3]
SB_DQ[27]
SB_DM[6]
DDR_A_D26
M8
AG6
DDR_A_DM4
DDR_B_D28
K5
AT8
DDR_B_DM7
SA_DQ[26]
SA_DM[4]
SB_DQ[28]
SB_DM[7]
DDR_A_D27
L9
AM7
DDR_A_DM5
DDR_B_D29
K4
SA_DQ[27]
SA_DM[5]
SB_DQ[29]
C
DDR_A_D28
L6
AN10
DDR_A_DM6
DDR_B_D30
M4
SA_DQ[28]
SA_DM[6]
SB_DQ[30]
DDR_A_D29
C
K8
AN13
DDR_A_DM7
DDR_B_D31
N5
SA_DQ[29]
SA_DM[7]
SB_DQ[31]
DDR_A_D30
N8
DDR_B_D32
AF3
SA_DQ[30]
SB_DQ[32]
DDR_A_D31
P9
DDR_B_D33
AG1
SA_DQ[31]
SB_DQ[33]
DDR_B_DQS#[0
7]
<11>
DDR_A_D32
AH5
DDR_B_D34
AJ3
D5
DDR_B_DQS#0
SA_DQ[32]
SB_DQ[34]
SB_DQS#[0]
DDR_A_D33
AF5
DDR_B_D35
AK1
F4
DDR_B_DQS#1
SA_DQ[33]
DDR_A_DQS#[0
7]
<10>
SB_DQ[35]
SB_DQS#[1]
DDR_A_D34
AK6
C9
DDR_A_DQS#0
DDR_B_D36
AG4
J4
DDR_B_DQS#2
SA_DQ[34]
SA_DQS#[0]
SB_DQ[36]
SB_DQS#[2]
DDR_A_D35
AK7
F8
DDR_A_DQS#1
DDR_B_D37
AG3
L4
DDR_B_DQS#3
SA_DQ[35]
SA_DQS#[1]
SB_DQ[37]
SB_DQS#[3]
DDR_A_D36
AF6
J9
DDR_A_DQS#2
DDR_B_D38
AJ4
AH2
DDR_B_DQS#4
SA_DQ[36]
SA_DQS#[2]
SB_DQ[38]
SB_DQS#[4]
DDR_A_D37
AG5
N9
DDR_A_DQS#3
DDR_B_D39
AH4
AL4
DDR_B_DQS#5
SA_DQ[37]
SA_DQS#[3]
SB_DQ[39]
SB_DQS#[5]
DDR_A_D38
AJ7
AH7
DDR_A_DQS#4
DDR_B_D40
AK3
AR5
DDR_B_DQS#6
SA_DQ[38]
SA_DQS#[4]
SB_DQ[40]
SB_DQS#[6]
DDR_A_D39
AJ6
AK9
DDR_A_DQS#5
DDR_B_D41
AK4
AR8
DDR_B_DQS#7
SA_DQ[39]
SA_DQS#[5]
SB_DQ[41]
SB_DQS#[7]
DDR_A_D40
AJ10
AP11
DDR_A_DQS#6
DDR_B_D42
AM6
SA_DQ[40]
SA_DQS#[6]
SB_DQ[42]
DDR_A_D41
AJ9
AT13
DDR_A_DQS#7
DDR_B_D43
AN2
SA_DQ[41]
SA_DQS#[7]
SB_DQ[43]
DDR_A_D42
AL10
DDR_B_D44
AK5
SA_DQ[42]
SB_DQ[44]
DDR_A_D43
AK12
DDR_B_D45
AK2
SA_DQ[43]
SB_DQ[45]
DDR_A_D44
AK8
DDR_B_D46
AM4
SA_DQ[44]
SB_DQ[46]
DDR_A_D45
AL7
DDR_B_D47
AM3
SA_DQ[45]
DDR_A_DQS[0
7]
<10>
SB_DQ[47]
DDR_B_DQS[0
7]
<11>
DDR_A_D46
AK11
C8
DDR_A_DQS0
DDR_B_D48
AP3
C5
DDR_B_DQS0
SA_DQ[46]
SA_DQS[0]
SB_DQ[48]
SB_DQS[0]
DDR_A_D47
AL8
F9
DDR_A_DQS1
DDR_B_D49
AN5
E3
DDR_B_DQS1
SA_DQ[47]
SA_DQS[1]
SB_DQ[49]
SB_DQS[1]
DDR_A_D48
AN8
H9
DDR_A_DQS2
DDR_B_D50
AT4
H4
DDR_B_DQS2
SA_DQ[48]
SA_DQS[2]
SB_DQ[50]
SB_DQS[2]
DDR_A_D49
AM10
M9
DDR_A_DQS3
DDR_B_D51
AN6
M5
DDR_B_DQS3
SA_DQ[49]
SA_DQS[3]
SB_DQ[51]
SB_DQS[3]
DDR_A_D50
AR11
AH8
DDR_A_DQS4
DDR_B_D52
AN4
AG2
DDR_B_DQS4
SA_DQ[50]
SA_DQS[4]
SB_DQ[52]
SB_DQS[4]
DDR_A_D51
AL11
AK10
DDR_A_DQS5
DDR_B_D53
AN3
AL5
DDR_B_DQS5
SA_DQ[51]
SA_DQS[5]
SB_DQ[53]
SB_DQS[5]
DDR_A_D52
AM9
AN11
DDR_A_DQS6
DDR_B_D54
AT5
AP5
DDR_B_DQS6
SA_DQ[52]
SA_DQS[6]
SB_DQ[54]
SB_DQS[6]
DDR_A_D53
AN9
AR13
DDR_A_DQS7
DDR_B_D55
AT6
AR7
DDR_B_DQS7
SA_DQ[53]
SA_DQS[7]
SB_DQ[55]
SB_DQS[7]
DDR_A_D54
AT11
DDR_B_D56
AN7
SA_DQ[54]
SB_DQ[56]
DDR_A_D55
AP12
DDR_B_D57
AP6
SA_DQ[55]
SB_DQ[57]
DDR_A_D56
AM12
DDR_B_D58
AP8
SA_DQ[56]
SB_DQ[58]
DDR_A_D57
AN12
DDR_B_D59
AT9
SA_DQ[57]
DDR_A_MA[0
15]
<10>
SB_DQ[59]
DDR_A_D58
AM13
Y3
DDR_A_MA0
DDR_B_D60
AT7
SA_DQ[58]
SA_MA[0]
SB_DQ[60]
DDR_A_D59
AT14
W1
DDR_A_MA1
DDR_B_D61
AP9
SA_DQ[59]
SA_MA[1]
SB_DQ[61]
DDR_A_D60
AT12
AA8
DDR_A_MA2
DDR_B_D62
AR10
SA_DQ[60]
SA_MA[2]
SB_DQ[62]
DDR_B_MA[0
15]
<11>
B
DDR_A_D61
DDR_A_MA3
B
AL13
AA3
DDR_B_D63
AT10
U5
DDR_B_MA0
SA_DQ[61]
SA_MA[3]
SB_DQ[63]
SB_MA[0]
DDR_A_D62
AR14
V1
DDR_A_MA4
V2
DDR_B_MA1
SA_DQ[62]
SA_MA[4]
SB_MA[1]
DDR_A_D63
AP14
AA9
DDR_A_MA5
T5
DDR_B_MA2
SA_DQ[63]
SA_MA[5]
SB_MA[2]
V8
DDR_A_MA6
V3
DDR_B_MA3
SA_MA[6]
SB_MA[3]
T1
DDR_A_MA7
R1
DDR_B_MA4
SA_MA[7]
SB_MA[4]
Y9
DDR_A_MA8
AB1
T8
DDR_B_MA5
SA_MA[8]
<11>
DDR_B_BS0
SB_BS[0]
SB_MA[5]
R2
<10>
DDR_A_BS0
AC3
U6
DDR_A_MA9
W5
DDR_B_MA6
SA_BS[0]
SA_MA[9]
<11>
DDR_B_BS1
SB_BS[1]
SB_MA[6]
AB2
AD4
DDR_A_MA10
R7
R6
DDR_B_MA7
<10>
DDR_A_BS1
SA_BS[1]
SA_MA[10]
<11>
DDR_B_BS2
SB_BS[2]
SB_MA[7]
U7
T2
DDR_A_MA11
R4
DDR_B_MA8
<10>
DDR_A_BS2
SA_BS[2]
SA_MA[11]
SB_MA[8]
U3
DDR_A_MA12
R5
DDR_B_MA9
SA_MA[12]
SB_MA[9]
AG8
DDR_A_MA13
AC5
AB5
DDR_B_MA10
SA_MA[13]
<11>
DDR_B_CAS#
SB_CAS#
SB_MA[10]
T3
DDR_A_MA14
Y7
P3
DDR_B_MA11
SA_MA[14]
<11>
DDR_B_RAS#
SB_RAS#
SB_MA[11]
AE1
V9
DDR_A_MA15
AC6
R3
DDR_B_MA12
<10>
DDR_A_CAS#
SA_CAS#
SA_MA[15]
<11>
DDR_B_WE#
SB_WE#
SB_MA[12]
AB3
AF7
DDR_B_MA13
<10>
DDR_A_RAS#
SA_RAS#
SB_MA[13]
AE9
P5
DDR_B_MA14
<10>
DDR_A_WE#
SA_WE#
SB_MA[14]
N1
DDR_B_MA15
SB_MA[15]
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
ME@
ME@
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
ME@
ME@
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2008/10/31
2008/10/31
2008/10/31
2009/10/31
2009/10/31
2009/10/31
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Arrandale(3/5)-DDR III
Arrandale(3/5)-DDR III
Arrandale(3/5)-DDR III
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.3
0.3
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-5751
LA-5751
LA-5751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, October 30, 2009
Friday, October 30, 2009
Friday, October 30, 2009
Sheet
Sheet
Sheet
7
7
7
of
of
of
51
51
51
5
4
3
2
1
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
C257 C257 1U_0603_10V4Z 1U_0603_10V4Z C170 C170 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K C255 C255 C212 C212 C213
C257
C257
1U_0603_10V4Z
1U_0603_10V4Z
C170
C170
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C255
C255
C212
C212
C213
C213
1U_0603_10V4Z
1U_0603_10V4Z
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
C169
C169
10U_0805_6.3V6M
10U_0805_6.3V6M
C253
C253
C258
C258
C273
C273
C218
C218
1U_0603_10V4Z
1U_0603_10V4Z
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
C168
C168
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C256
C256
C252
C252
1U_0603_10V4Z
1U_0603_10V4Z
22U_0805_6.3V6M
22U_0805_6.3V6M
C149
C149
1U_0603_10V4Z
1U_0603_10V4Z
C269
C269
C254
C254
C268
C268
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0603_10V4Z
1U_0603_10V4Z
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
C167
C167
1U_0603_10V4Z
1U_0603_10V4Z
5
4
3
2
1
C286
C286
0.1U_0402_10V6K
0.1U_0402_10V6K
R132
R132
GFX_IMON
2
1
1K_0402_5%
1K_0402_5%
C287
C287
DIS@
DIS@
0.1U_0402_10V6K
0.1U_0402_10V6K
+CPU_CORE
C288
C288
AS NO CONNECT
+GFX_CORE
GRAPHICS
GRAPHICS
JCPU1F
JCPU1F
0.1U_0402_10V6K
0.1U_0402_10V6K
FDI
FDI
PEG & DMI
PEG & DMI
JCPU1G
JCPU1G
BUT A SMALL AMOUNT OF POWER
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C289
C289
AT21
(~15MW) MAYBE WASTED
VAXG1
0.1U_0402_10V6K
0.1U_0402_10V6K
AT19
AR22
VAXG2
VAXG_SENSE
VCC_AXG_SENSE
<47>
1
1
1
1
1
1
1
1
AT18
AT22
DESIGN GUIDE REV1.1
VAXG3
VSSAXG_SENSE
VSS_AXG_SENSE
<47>
+VCCP
48A
18A
C161
C161
C160
C160
C191
C191
C190
C190
C189
C189
C159
C159
C591
C591
C592
C592
AT16
15A
VAXG4
@
@
@
@
@
@
@
@
AR21
VAXG5
D
D
AG35
AH14
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@
AR19
VCC1
VTT0_1
2
2
2
2
2
2
2
2
VAXG6
AG34
AH12
AR18
VCC2
VTT0_2
VAXG7
AG33
AH11
1
AR16
AM22
VCC3
VTT0_3
VAXG8
GFX_VID[0]
GFXVR_VID_0
<47>
AG32
AH10
AP21
AP22
R140
R140
1 1
1 1
VCC4
VTT0_4
VAXG9
GFX_VID[1]
GFXVR_VID_1
<47>
+ +
AG31
J14
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
AP19
AN22
GFX_VR_EN
1
2
4.7K_0402_5%
4.7K_0402_5%
VCC5
VTT0_5
VAXG10
GFX_VID[2]
GFXVR_VID_2
<47>
AG30
J13
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AP18
AP23
VCC6
VTT0_6
VAXG11
GFX_VID[3]
GFXVR_VID_3
<47>
AG29
H14
AP16
AM23
UMA@
UMA@
VCC7
VTT0_7
GFXVR_VID_4
<47>
2 2
2 2
2
VAXG12
GFX_VID[4]
C211
C211
C240
C240
AG28
H12
AN21
AP24
VCC8
VTT0_8
VAXG13
GFX_VID[5]
GFXVR_VID_5
<47>
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AG27
G14
AN19
AN24
VCC9
VTT0_9
VAXG14
GFX_VID[6]
GFXVR_VID_6
<47>
AG26
G13
R559
R559
AN18
VCC10
VTT0_10
VAXG15
AF35
G12
AN16
UMA@
UMA@
0_0402_5%
0_0402_5%
VCC11
VTT0_11
VAXG16
AF34
G11
AM21
AR25
GFX_VR_EN
1
2
R141
R141
0_0402_5%
0_0402_5%
VCC12
VTT0_12
DIS@
DIS@
VAXG17
GFX_VR_EN
GFXVR_EN
<47>
C210
C210
C272
C272
AF33
F14
AM19
AT25
VCC13
VTT0_13
VAXG18
GFX_DPRSLPVR
GFXVR_DPRSLPVR
<47>
AF32
F13
GFX_IMON
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
1
1
1
AM18
AM24
VCC14
VTT0_14
VAXG19
GFX_IMON
GFXVR_IMON
<47>
AF31
F12
@
@
@
@
AM16
VCC15
VTT0_15
VAXG20
AF30
F11
AL21
VCC16
VTT0_16
VAXG21
AF29
E14
AL19
VCC17
VTT0_17
2
2
2
2
2
VAXG22
+1.5V_DDR3
C215
C215
AF28
E12
AL18
VCC18
VTT0_18
VAXG23
+VCCP
1
10U_0805_6.3V6M
10U_0805_6.3V6M
AF27
D14
AL16
VCC19
VTT0_19
VAXG24
AF26
D13
AK21
AJ1
VCC20
VTT0_20
VAXG25
VDDQ1
AD35
D12
AK19
AF1
VCC21
VTT0_21
VAXG26
VDDQ2
AD34
D11
AK18
AE7
1
1
1
1
1
VCC22
VTT0_22
VAXG27
VDDQ3
C214
C214
AD33
C14
AK16
AE4
VCC23
VTT0_23
VAXG28
VDDQ4
10U_0805_6.3V6M
10U_0805_6.3V6M
AD32
C13
AJ21
AC1
VCC24
VTT0_24
VAXG29
VDDQ5
AD31
C12
1
1 1
1
AJ19
AB7
VCC25
VTT0_25
VAXG30
VDDQ6
2
2
2
2
2
AD30
C11
AJ18
AB4
VCC26
VTT0_26
VAXG31
VDDQ7
AD29
B14
AJ16
Y1
VCC27
VTT0_27
VAXG32
VDDQ8
AD28
B12
AH21
W7
VCC28
VTT0_28
2
2 2
2
VAXG33
VDDQ9
AD27
A14
AH19
3A
W4
VCC29
VTT0_29
VAXG34
VDDQ10
AD26
A13
AH18
U1
VCC30
VTT0_30
VAXG35
VDDQ11
AC35
A12
AH16
T7
VCC31
VTT0_31
VAXG36
VDDQ12
AC34
A11
T4
Modify for cost revew.
1
VCC32
VTT0_32
VDDQ13
C
C
AC33
P1
1 1
09/16/2009
VCC33
VDDQ14
+VCCP
@
@
+ +
AC32
N7
VCC34
VDDQ15
+VCCP
AC31
N4
VCC35
VDDQ16
AC30
AF10
L1
VCC36
VTT0_33
VDDQ17
2
2 2
AC29
AE10
J24
H1
VCC37
VTT0_34
VTT1_45
VDDQ18
AC28
AC10
J23
VCC38
VTT0_35
VTT1_46
AC27
AB10
1 1
H25
VCC39
VTT0_36
VTT1_47
+VCCP
AC26
Y10
1
1
VCC40
VTT0_37
AA35
W10
VCC41
VTT0_38
AA34
U10
P10
VCC42
VTT0_39
2 2
VTT0_59
AA33
T10
N10
VCC43
VTT0_40
2
2
VTT0_60
AA32
J12
L10
VCC44
VTT0_41
VTT0_61
AA31
J11
K10
1 1
VCC45
VTT0_42
VTT0_62
AA30
J16
VCC46
VTT0_43
AA29
J15
VCC47
VTT0_44
CPU
AA28
VCC48
+VCCP
2 2
AA27
VCC49
C207
C207
AA26
J22
VCC50
VTT1_63
+VCCP
10U_0805_6.3V6M
10U_0805_6.3V6M
Y35
K26
J20
VCC51
VTT1_48
VTT1_64
Y34
J27
J18
VCC52
VTT1_49
VTT1_65
Y33
J26
H21
VCC53
VTT1_50
VTT1_66
Y32
1
1 J25
1
1
H20
VCC54
VTT1_51
VTT1_67
C274
C274
Y31
H27
H19
VCC55
VTT1_52
VTT1_68
Y30
R608R608
1
2
1K_0402_5%1K_0402_5%
10U_0805_6.3V6M
10U_0805_6.3V6M
G28
1
1
VCC56
VTT1_53
Y29
2 G27
VCC57
2
2
2
VTT1_54
Y28
G26
VCC58
VTT1_55
Y27
F26
VCC59
VTT1_56
2
2
C217
C217
Y26
E26
L26
VCC60
VTT1_57
VCCPLL1
C554
C554
C200
C200
10U_0805_6.3V6M
10U_0805_6.3V6M
V35
AN33
E25
L27
VCC61
PSI#
PSI#
<48>
VTT1_58
VCCPLL2
+1.8VS
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
10U_0805_6.3V6M
10U_0805_6.3V6M
V34
0.6A
M26
VCC62
VCCPLL3
V33
VCC63
H_VID[0
6]
<48>
V32
AK35
H_VID0
VCC64
VID[0]
B V31
AK33
H_VID1
B
C219
C219
VCC65
VID[1]
C181
C181
C182
C182
10U_0805_6.3V6M
10U_0805_6.3V6M
V30
AK34
H_VID2
1
1
1
1
1
VCC66
VID[2]
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
V29
AL35
H_VID3
VCC67
VID[3]
V28
AL33
H_VID4
VCC68
VID[4]
V27
AM33
H_VID5
VCC69
VID[5]
2
2
2
2
2
V26
AM35
H_VID6
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
VCC70
VID[6]
PM_DPRSLPVR_R
C198
C198
C216
C216
U35
AM34
1
2
ME@
ME@
VCC71
PROC_DPRSLPVR
PROC_DPRSLPVR
<48>
R56R56
0_0402_5%0_0402_5%
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
U34
VCC72
U33
For Intel S3 Power Reduction.
VCC73
1
+1.5V
+1.5V_DDR3
J3
J3
C209
C209
U32
VCC74
VTT_SELECT
10U_0805_6.3V6M
10U_0805_6.3V6M
U31
G15
2
1
VCC75
VTT_SELECT
VTT_SELECT
<46>
2
1
C199
C199
C270
C270
U30
VCC76
JUMP_43X118
JUMP_43X118
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
U29
VCC77
U28
H_VTTVID1 = Low, 1.1V FOR Clarksfiel
J2
J2
VCC78
C208
C208
U27
2
1
VCC79
2
1
H_VTTVID1 = High, 1.05V FOR Auburndale
+1.5V_DDR3
10U_0805_6.3V6M
10U_0805_6.3V6M
U26
VCC80
+1.5V
2
R35
JUMP_43X118
JUMP_43X118
C201
C201
C271
C271
VCC81
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
R34
VCC82
R33
1
VCC83
R32
AN35
U11
U11
VCC84
ISENSE
IMVP_IMON
<48>
R31
8
1
@
@
R233
R233
VCC85
D
S
+5VALW
R30
7
2
220_0402_5%
220_0402_5%
VCC86
D
S
2
R29
0_0402_5%
0_0402_5%
6
3
VCC87
D
S
R28
AJ34
VCC_SENSE
1 R554
R554
2
VCCSENSE
5
4
1 1
1 1
VCC88
VCC_SENSE
VCCSENSE
<48>
D
G
D
D
R27
AJ35
VSS_SENSE
1 2
VSSSENSE
VCC89
VSS_SENSE
VSSSENSE
<48>
R26
R553R553
0_0402_5%0_0402_5%
SI4800BDY-T1-E3_SO8
SI4800BDY-T1-E3_SO8
SUSP
2
Q19
Q19
VCC90
P35
R268
R268
G G
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
VCC91
+1.5V_DDR3
2 2
2 2
P34
B15
20K_0402_5%
20K_0402_5%
S
S
VCC92
VTT_SENSE
VTT_SENSE
<46>
P33
A15
VCC93
VSS_SENSE_VTT
PAD T15
PAD T15
P32
@
@
1.5V_DDR3_GATE
VCC94
P31
1
VCC95
D
D
P30
R267
R267
VCC96
A
A P29
2
Q23
Q23
C325
C325
0_0402_5%
0_0402_5%
VCC97
<39,44,45>
SUSP
P28
G G
2N7002_SOT23
2N7002_SOT23
0.1U_0603_25V7K
0.1U_0603_25V7K
VCC98
2
P27
S
S
@
@
VCC99
P26
For Intel S3 Power Reduction.
VCC100
Close to CPU
+CPU_CORE
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU CORE SUPPLY
CPU CORE SUPPLY
VCCSENSE
1
2
R552R552
100_0402_1%100_0402_1%
2008/10/31
2008/10/31
2008/10/31
2009/10/31
2009/10/31
2009/10/31
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
VSSSENSE
1
2
Arrandale(4/5)-PWR
Arrandale(4/5)-PWR
Arrandale(4/5)-PWR
R551R551
100_0402_1%100_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ME@
ME@
Custom
Custom
Custom
0.3
0.3
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-5751
LA-5751
LA-5751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Friday, October 30, 2009
Friday, October 30, 2009
Friday, October 30, 2009
Sheet
Sheet
Sheet
8
8
8
of
of
of
51
51
51
5
4
3
2
1
POWER
POWER
SENSE LINES
SENSE LINES
CPU VIDS
CPU VIDS
1.1V RAIL POWER
1.1V RAIL POWER
12
13
@
@
@
@
1
2
POWER
POWER
SENSE
SENSE
GRAPHICS VIDs
GRAPHICS VIDs
LINES
LINES
1.1V1.8V
1.1V1.8V
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
13
12
C129 C129 22U_0805_6.3V6M 22U_0805_6.3V6M C87 C87 22U_0805_6.3V6M 22U_0805_6.3V6M C90 C90 22U_0805_6.3V6M
C129
C129
22U_0805_6.3V6M
22U_0805_6.3V6M
C87
C87
22U_0805_6.3V6M
22U_0805_6.3V6M
C90
C90
22U_0805_6.3V6M
22U_0805_6.3V6M
C91
C91
22U_0805_6.3V6M
22U_0805_6.3V6M
C164
C164
C571
C571
470U_D2T_2VM
470U_D2T_2VM
22U_0805_6.3V6M
22U_0805_6.3V6M
C92
C92
C572
C572
470U_D2T_2VM
470U_D2T_2VM
22U_0805_6.3V6M
22U_0805_6.3V6M
C75
C75
C577
C577
470U_D2T_2VM
470U_D2T_2VM
22U_0805_6.3V6M
22U_0805_6.3V6M
C76
C76
C583
C583
C194
C194
470U_D2T_2VM
470U_D2T_2VM
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
C578
C578
C165
C165
5
4
3
2
1
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
+CPU_CORE
CPU CORE
C584
C584
C148
C148
C197
C197
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
JCPU1H
JCPU1H
JCPU1I
JCPU1I
C573
C573
C166
C166
C89
C89
AT20
AE34
VSS1
VSS81
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AT17
AE33
1 1
1 1
1 1
1
1 1
1 1
1
VSS2
VSS82
Inside cavity
AR31
AE32
K27
VSS3
VSS83
VSS161
AR28
AE31
K9
VSS4
VSS84
VSS162
AR26
AE30
K6
VSS5
VSS85
VSS163
2 2
2 2
2 2
2
2 2
2 2
2
C574
C574
C193
C193
C180
C180
AR24
AE29
K3
VSS6
VSS86
VSS164
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AR23
AE28
J32
VSS7
VSS87
VSS165
AR20
AE27
J30
VSS8
VSS88
VSS166
D
D
AR17
AE26
J21
VSS9
VSS89
VSS167
AR15
AE6
J19
VSS10
VSS90
VSS168
C579
C579
C179
C179
C196
C196
AR12
AD10
H35
VSS11
VSS91
VSS169
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AR9
AC8
H32
VSS12
VSS92
VSS170
AR6
AC4
H28
VSS13
VSS93
VSS171
AR3
AC2
H26
1
1 1
1 1
1 1
1 1
VSS14
VSS94
VSS172
AP20
AB35
H24
VSS15
VSS95
VSS173
between Inductor and socket
C580
C580
C162
C162
C88
C88
AP17
AB34
H22
VSS16
VSS96
VSS174
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AP13
AB33
H18
VSS17
VSS97
VSS175
2
2 2
2 2
2 2
2 2
AP10
AB32
H15
VSS18
VSS98
VSS176
AP7
AB31
H13
VSS19
VSS99
VSS177
AP4
AB30
H11
VSS20
VSS100
VSS178
C585
C585
C163
C163
C192
C192
AP2
AB29
H8
VSS21
VSS101
VSS179
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AN34
AB28
H5
VSS22
VSS102
VSS180
AN31
AB27
H2
VSS23
VSS103
VSS181
AN23
AB26
G34
VSS24
VSS104
VSS182
AN20
AB6
G31
1
1
1
1
VSS25
VSS105
VSS183
C568
C568
C147
C147
C195
C195
AN17
AA10
G20
1
1
1
1 1
1 1
1 1
1 1
VSS26
VSS106
VSS184
+ +
+ +
+ +
+ +
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
AM29
Y8
G9
VSS27
VSS107
VSS185
AM27
Y4
G6
VSS28
VSS108
VSS186
AM25
Y2
G3
VSS29
VSS109
VSS187
2
2
2
2 2
2 2
2
3
2
3
2
3
2
3
2 2
2 2
AM20
W35
F30
VSS30
VSS110
VSS188
AM17
W34
F27
VSS31
VSS111
VSS189
AM14
W33
F25
VSS32
VSS112
VSS190
AM11
W32
F22
VSS33
VSS113
VSS191
AM8
W31
F19
VSS34
VSS114
VSS192
Under cavity
AM5
W30
F16
VSS35
VSS115
VSS193
AM2
W29
E35
VSS36
VSS116
VSS194
AL34
W28
E32
VSS37
VSS
VSS
VSS117
VSS195
VSS
VSS
AL31
W27
E29
470uF 4.5mohm
VSS38
VSS118
VSS196
AL23
W26
E24
VSS39
VSS119
VSS197
AL20
W6
E21
VSS40
VSS120
VSS198
C
C
AL17
V10
E18
VSS41
VSS121
VSS199
AL12
U8
E13
VSS42
VSS122
VSS200
AL9
U4
E11
VSS43
VSS123
VSS201
AL6
U2
E8
VSS44
VSS124
VSS202
AL3
T35
E5
VSS45
VSS125
VSS203
AK29
T34
E2
AT35
VSS_NCTF1_R
VSS46
VSS126
VSS204
VSS_NCTF1
AK27
T33
D33
AT1
VSS_NCTF2_R
VSS47
VSS127
VSS205
VSS_NCTF2
AK25
T32
D30
AR34
VSS_NCTF3_R
VSS48
VSS128
VSS206
VSS_NCTF3
AK20
T31
D26
B34
VSS_NCTF4_R
VSS49
VSS129
VSS207
VSS_NCTF4
AK17
T30
D9
B2
VSS_NCTF5_R
VSS50
VSS130
VSS208
VSS_NCTF5
AJ31
T29
D6
B1
VSS_NCTF6_R
VSS51
VSS131
VSS209
VSS_NCTF6
AJ23
T28
D3
A35
VSS_NCTF7_R
VSS52
VSS132
VSS210
VSS_NCTF7
AJ20
T27
C34
VSS53
VSS133
VSS211
AJ17
T26
C32
VSS54
VSS134
VSS212
AJ14
T6
C29
VSS55
VSS135
VSS213
AJ11
R10
C28
VSS56
VSS136
VSS214
AJ8
P8
C24
VSS57
VSS137
VSS215
AJ5
P4
C22
VSS58
VSS138
VSS216
AJ2
P2
C20
VSS59
VSS139
VSS217
AH35
N35
C19
VSS60
VSS140
VSS218
AH34
N34
C16
VSS61
VSS141
VSS219
AH33
N33
B31
VSS62
VSS142
VSS220
AH32
N32
B25
VSS63
VSS143
VSS221
AH31
N31
B21
VSS64
VSS144
VSS222
AH30
N30
B18
VSS65
VSS145
VSS223
AH29
N29
B17
VSS66
VSS146
VSS224
AH28
N28
B13
VSS67
VSS147
VSS225
AH27
N27
B11
VSS68
VSS148
VSS226
AH26
N26
B8
VSS69
VSS149
VSS227
AH20
N6
B6
VSS70
VSS150
VSS228
AH17
M10
B4
VSS71
VSS151
VSS229
AH13
L35
A29
VSS72
VSS152
VSS230
B
B
AH9
L32
A27
VSS73
VSS153
VSS231
AH6
L29
A23
VSS74
VSS154
VSS232
AH3
L8
A9
VSS75
VSS155
VSS233
AG10
L5
VSS76
VSS156
AF8
L2
VSS77
VSS157
AF4
K34
VSS78
VSS158
AF2
K33
VSS79
VSS159
AE35
K30
VSS80
VSS160
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
ME@
ME@
ME@
ME@
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2008/10/31
2008/10/31
2008/10/31
2009/10/31
2009/10/31
2009/10/31
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Arrandale(5/5)-GND/Bypass
Arrandale(5/5)-GND/Bypass
Arrandale(5/5)-GND/Bypass
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.3
0.3
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-5751
LA-5751
LA-5751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Thursday, October 29, 2009
Thursday, October 29, 2009
Thursday, October 29, 2009
Sheet
Sheet
Sheet
9
9
9
of
of
of
51
51
51
5
4
3
2
1
NCTF
NCTF
C316 C316 0.1U_0402_10V6K 0.1U_0402_10V6K C317 C317 0.1U_0402_10V6K 0.1U_0402_10V6K C315 C315 0.1U_0402_10V6K
C316
C316
0.1U_0402_10V6K
0.1U_0402_10V6K
C317
C317
0.1U_0402_10V6K
0.1U_0402_10V6K
C315
C315
0.1U_0402_10V6K
0.1U_0402_10V6K
C314
C314
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
C308
C308
10U_0603_6.3V6M
10U_0603_6.3V6M
C570
C570
1U_0603_10V4Z
1U_0603_10V4Z
10U_0603_6.3V6M
10U_0603_6.3V6M
C301
C301
5
4
3
2
1
C309
C309
1U_0603_10V4Z
1U_0603_10V4Z
+VREF_DQ_DIMMA
+1.5V
+1.5V
10U_0603_6.3V6M
10U_0603_6.3V6M
C300
C300
3A@1.5V3A@1.5V3A@1.5V3A@1.5V
<7>
DDR_A_D[0 63]
+1.5V
C310
C310
1U_0603_10V4Z
1U_0603_10V4Z
DDR3 SO-DIMM A
<7>
DDR_A_DM[0 7]
C606
C606
JDIMM1
JDIMM1
10U_0603_6.3V6M
10U_0603_6.3V6M
<7>
DDR_A_DQS[0 7]
+VREF_DQ_DIMMA
R297
R297
1U_0603_10V4Z
1U_0603_10V4Z
1
2
VREF_DQ
VSS1
C581
3
4
DDR_A_D4
1K_0402_1%
1K_0402_1%
C581
VSS2
DQ4
<7>
DDR_A_DQS#[0 7]
+VREF_DQ_DIMMA
DDR_A_D0
C607
C607
5
6
DDR_A_D5
DQ0
DQ5
DDR_A_D1
1
1
7
8
DQ1
VSS3
<7>
DDR_A_MA[0 15]
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0603_10V4Z
1U_0603_10V4Z
9
10
DDR_A_DQS#0
VSS4
DQS#0
DDR_A_DM0
11
12
DDR_A_DQS0
DM0
DQS0
C586
C586
C605
C605
13
14
2
2
VSS5
VSS6
DDR_A_D2
15
16
DDR_A_D6
DQ2
DQ6
D
DDR_A_D3
D
17
18
DDR_A_D7
DQ3
DQ7
R305
R305
10U_0603_6.3V6M
10U_0603_6.3V6M
19
20
VSS7
VSS8
DDR_A_D8
21
22
DDR_A_D12
1K_0402_1%
1K_0402_1%
DQ8
DQ12
DDR_A_D9
C588
23
24
DDR_A_D13
C588
DQ9
DQ13
25
26
VSS9
VSS10
DDR_A_DQS#1
27
28
DDR_A_DM1
DQS#1
DM1
DDR_A_DQS1
29
30
DRAMRST#
10U_0603_6.3V6M
10U_0603_6.3V6M
DQS1
RESET#
DRAMRST#
<5,11>
31
32
VSS11
VSS12
DDR_A_D10
DDR_A_D14
C589
C589
33
34
DQ10
DQ14
DDR_A_D11
35
36
DDR_A_D15
DQ11
DQ15
37
38
VSS13
VSS14
DDR_A_D16
39
40
DDR_A_D20
DQ16
DQ20
DDR_A_D17
41
42
DDR_A_D21
For Arranale only +VREF_DQ_DIMMA
supply from a external 1.5V voltage divide
circuit.
DQ17
DQ21
43
44
VSS15
VSS16
DDR_A_DQS#2
07/17/2009
45
46
DDR_A_DM2
DQS#2
DM2
DDR_A_DQS2
47
48
DQS2
VSS17
49
50
DDR_A_D22
VSS18
DQ22
DDR_A_D18
51
52
DDR_A_D23
DQ18
DQ23
DDR_A_D19
53
54
DQ19
VSS19
55
56
DDR_A_D28
VSS20
DQ28
DDR_A_D24
57
58
DDR_A_D29
DQ24
DQ29
DDR_A_D25
59
60
DQ25
VSS21
61
62
DDR_A_DQS#3
VSS22
DQS#3
DDR_A_DM3
63
64
DDR_A_DQS3
DM3
DQS3
65
66
VSS23
VSS24
DDR_A_D26
67
68
DDR_A_D30
DQ26
DQ30
DDR_A_D27
69
70
DDR_A_D31
DQ27
DQ31
71
72
VSS25
VSS26
DDR_CKE0_DIMMA
73
74
DDR_CKE1_DIMMA
<7>
DDR_CKE0_DIMMA
CKE0
CKE1
DDR_CKE1_DIMMA
<7>
C
C
75
76
VDD1
VDD2
77
78
DDR_A_MA15
NC1
A15
DDR_A_BS2
79
80
DDR_A_MA14
<7>
DDR_A_BS2
BA2
A14
81
82
VDD3
VDD4
DDR_A_MA12
83
84
DDR_A_MA11
A12/BC#
A11
DDR_A_MA9
85
86
DDR_A_MA7
A9
A7
87
88
VDD5
VDD6
DDR_A_MA8
89
90
DDR_A_MA6
A8
A6
DDR_A_MA5
91
92
DDR_A_MA4
C355
C355
A5
A4
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
93
94
VDD7
VDD8
DDR_A_MA3
95
96
DDR_A_MA2
A3
A2
DDR_A_MA1
97
98
DDR_A_MA0
A1
A0
99
100
VDD9
VDD10
M_CLK_DDR1
C346
C346
<7>
M_CLK_DDR0
M_CLK_DDR0
101
102
CK0
CK1
M_CLK_DDR1
<7>
M_CLK_DDR#0
0.1U_0402_10V6K
0.1U_0402_10V6K
103
104
M_CLK_DDR#1
<7>
M_CLK_DDR#0
CK0#
CK1#
M_CLK_DDR#1
<7>
105
106
VDD11
VDD12
DDR_A_MA10
107
108
DDR_A_BS1
A10/AP
BA1
DDR_A_BS1
<7>
DDR_A_BS0
109
110
DDR_A_RAS#
<7>
DDR_A_BS0
BA0
RAS#
DDR_A_RAS#
<7>
111
112
VDD13
VDD14
DDR_A_WE#
113
114
DDR_CS0_DIMMA#
<7>
DDR_A_WE#
WE#
S0#
DDR_CS0_DIMMA#
<7>
DDR_A_CAS#
115
116
M_ODT0
<7>
DDR_A_CAS#
CAS#
ODT0
M_ODT0
<7>
117
118
VDD15
VDD16
DDR_A_MA13
119
120
M_ODT1
A13
ODT1
M_ODT1
<7>
+VREF_DQ_DIMMA
DDR_CS1_DIMMA#
121
122
<7>
DDR_CS1_DIMMA#
S1#
NC2
123
124
Layout Note:
VDD17
VDD18
125
126
NCTEST
VREF_CA
Place near DIMM
127
128
VSS27
VSS28
DDR_A_D32
129
130
DDR_A_D36
DQ32
DQ36
DDR_A_D33
131
132
DDR_A_D37
1
1
DQ33
DQ37
133
134
VSS29
VSS30
DDR_A_DQS#4
135
136
DDR_A_DM4
DQS#4
DM4
DDR_A_DQS4
137
138
DQS4
VSS31
2
2
B
B
139
140
DDR_A_D38
VSS32
DQ38
+1.5V
DDR_A_D34
141
142
DDR_A_D39
DQ34
DQ39
DDR_A_D35
143
144
DQ35
VSS33
145
146
DDR_A_D44
VSS34
DQ44
DDR_A_D40
147
148
DDR_A_D45
DQ40
DQ45
DDR_A_D41
149
150
1
DQ41
VSS35
151
152
DDR_A_DQS#5
1
1
1
1
1
1 1
1
1 1
1 1
VSS36
DQS#5
DDR_A_DM5
+
+
153
154
DDR_A_DQS5
C569
C569
DM5
DQS5
155
156
VDDQ(1.5V) =
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
VSS37
VSS38
DDR_A_D42
157
158
DDR_A_D46
@
@
@
@
DQ42
DQ46
2
2
2
2
2
2 2
2
2 2
2 2
2
DDR_A_D43
159
160
DDR_A_D47
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DQ43
DQ47
161
162
VSS39
VSS40
DDR_A_D48
163
164
DDR_A_D52
6*0603 10uf (PER CONNECTOR)
DQ48