Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Inverters
Panagiotis Panagis*, Fotis Stergiopoulos**, Pantelis Marabeas*** and Stefanos Manias***
* University of Newcastle Upon Tyne, Department of Electrical, Electronic and Computer Engineering, Newcastle,
United Kingdom
** Electrical Power Engineer, Thessaloniki, Greece
*** National Technical University of Athens, Department of Electrical and Computer Engineering, Athens, Greece
Abstract— In this paper, a comparison between existing presents one phase of the power circuit of a five-level
state of the art multilevel inverter topologies is performed. NPCMLI:
The topologies examined are the Neutral Point Clamp
Multilevel inverter (NPCMLI) or Diode-Clamped Multilevel
Inverter (DCMLI), the Flying Capacitor Multilevel Inverter
(FCMLI) and the Cascaded Cell Multilevel Inverter
(CCMLI). The comparison of these inverters is based on the
criteria of output voltage quality (Peak value of the
fundamental and dominant harmonic components and
THD), power circuitry complexity, and implementation cost.
The comparison results are based on theoretical results
verified by detailed simulation results.
I. INTRODUCTION
In recent years there has been a growing interest in
Voltage Source Multilevel Inverter (MLI) topologies since
they can extend the application of power electronics
systems to higher voltage and high power ratios. The
technology of multilevel converters is very attractive for
medium to high voltage range (2-13kV) applications,
which includes motor drive systems [1-3], power
distribution [4], power quality and power conditioning
applications [5]. The advantages of the multilevel
inverters compared to conventional two-level inverters are
[6]: higher voltage capability, reduction of input and
output harmonic content, lower switching losses, higher
amplitude fundamental and lower dv/dt. However, the
main disadvantages of multilevel inverters include voltage
Figure 1. One phase of the power circuit of a five-level
unbalance difficulties, unequal current stresses, and higher NPCMLI
implementation cost. The most common topology groups
of voltage source multilevel inverters are the following: Examining the power circuit of the NPCMLI shown in
the Diode-Clamped or Neutral Point Clamped Multilevel Fig. 1, the following useful relations can be found, if m is
Inverter (NPCMLI), the Flying Capacitor Multilevel the number of levels, k is the number of capacitors at the
Inverter (FCMLI) and the Cascaded Cell Multilevel dc side, l is the number of switches with freewheeling
Inverter (CCMLI). In this paper a comparison of these diodes per phase and j is the number of clamping diodes
inverters, using simulation models based on theoretical per phase, assuming that each blocking diode voltage
results, is used to derive valuable conclusions as regards rating is the same as the active device voltage rating:
the effect of the modulation strategy on the performance
characteristics of the inverters.
m = k +1
II. COMMON MULTILEVEL TOPOLOGIES l = 2(m − 1) (1)
Vdc/2 pc1
Da9 D b6 Ec4
IXGH 40N60A zero + +
Sa4 - -
IXGH 40N 60A
zero pb4
0 Sb4 E
zero Eb4
+ +
- DEb5
0 - D c10 Ec5
IXGH
Ea5 40N60A +
V3 + + Sa5 Db2 p_b1
E +
-
250Vdc D a7 -
DEa5 Db11 D c11 -
IXGH40N 60A
- Dc4
Dc3 E
E Sc5
Da2 0 DEc5
Da3
IXGH 40N 60A
IXGH 40N60A DEa6 Sb5 p_c1
Db4 p_b2 DEb6 Dc2
Sa6 Db3
0 Eb5 Dc7
p_a1 +
-Vdc/4 D b7 -
+
IXGH 40N 60A
Ec6
+ 0
-Vdc/4 Ea6
+0
-
Sb6 +
0E Eb6
-
Da4 -
+
-
+ +
-Vdc4 -
E
p_a2 DEa7 -
0 E -
IXGH 40N60A E
Sa7 -Vdc/4 D b8 p_c3
D a8 DEb7 p_c2 IXGH40N 60A
Sc6 DEc6
V4 0 Db12 Dc8
p_a3
250Vdc 0 IXGH 40N 60A Ec7
Ea7 Sb8 + +
Da12 p_a4 + Ea8 Ec8 DEc8
+
- - - 60A
IXGH40N
- + +
- p_b3
p_b4
0 D c12 E Sc7+ +-
E - -
E Eb7 E 60A
IXGH40N DEc7
IXGH
+ +40N060A
Sb7 Sc8
-
-
E 0
IXGH 40N60A
Sa8
-Vdc/2 DEa8
Eb8
0 + +
DEb8 0
-
- p_c4
E
2 2
Lb Lc
2 100mH 100mH
La 1 1
R a 100mH
50
1 Rc
50
Rb
50
m = k +1
0V 0A
l = 2(m − 1) (2)
-4.0A
Nc = (m − 1)(m − 2) / 2
>>
-500V -8.0A
20ms
1 V(Da4:1,0)
V(Da4:1,0) 2
25ms
-I(Ra)
-I(Ra)
30ms
Time
35ms 40ms
In order to verify the operation behavior and examine
Figure 3. Output phase voltage and current of a five-level the harmonic content of the FCMLI applying SPWM, the
NPCMLI circuit of Fig. 5 was simulated using PSPICE for different
modulation factors and normalized carrier values. Figure 6
500V
presents the simulation model of a three-phase five-level
FCMLI developed in SPICE:
400V
300V
200V
100V
0V
0Hz 1KHz 2KHz 3KHz 4KHz 5KHz 6KHz 7KHz 8KHz 9KHz 10KHz
V(Da4:1,0)
Frequency
4297
500V 8.0A
m = 2 Ns + 1
-4.0A
(3)
>>
l = 2(m − 1)
-500V -8.0A
20ms 25ms 30ms 35ms 40ms
1 V(Da4:1,0) 2 -I(Ra)
V(Da4:1,0) -I(Ra) Time
Figure 7. Output phase voltage and current of a five-level The most well known SPWM which can be applied to a
FCMLI CCMLI is the Phase-Shifted SPWM. This modulation
technique is the same as that of the conventional SPWM
500V technique which is applied to a conventional single-phase
full-bridge inverter, the only difference being that it
400V
utilizes more than one carrier. The number of carriers to
be used per phase is equal to the number of cells or
modules per phase leg. Moreover, these carriers are phase-
shifted with respect to each other by an angle φ equal to:
300V
180°
200V
ϕ= (4)
100V Ns
0V
In order to verify the operation behavior and examine
1KHz
0Hz V(Da4:1,0) 2KHz 3KHz 4KHz 5KHz
Frequency
6KHz 7KHz 8KHz 9KHz 10KHz
the harmonic content of the CCMLI applying phase-
Figure 8. Output phase voltage spectrum of a five-level
shifted SPWM, the circuit of Fig. 8 was simulated using
FCMLI SPICE for different modulation factors and normalized
carrier values. Fig. 10 presents the simulation model of a
three-phase five-level CCMLI developed in PSPICE.
C. The Cascaded Cell Multilevel Inverter (CCMLI) Similar to the NPCMLI and the FCMLI, Fig. 11 presents
The Cascaded Cell Multilevel Inverter (CCMLI) the simulation results obtained for the output phase
consists of a series connection of separate single (full- voltage and current of a three-phase five-level CCMLI
bridge) or three-phase inverter modules or cells [11] on with Vdc=1000V, Fnc =45, Μf = 0.225 and an R-L load
the ac output terminals. Each dc to ac module requires an (R=50Ω, L=100mH). Also Fig. 12 presents the spectrum
isolated dc input. This topology is suitable for applications of the generated output phase voltage:
where separate dc voltage sources are available, such as
photovoltaic (PV) generators, fuel cells and batteries. The
phase output voltage is generated by the sum of line-to-
line voltages of the full-bridge inverter modules. Figure 9
presents the power circuit of one phase of a five-level
CCMLI:
Figure 9. One phase of the power circuit of a three-phase Figure 10. Simulation model of a three-phase five-level
five-level CCMLI CCMLI
4298
500V
Fig. 13 presents the modulation principle of the above
techniques:
0V
-500V20ms 22ms 24ms 26ms 28ms 30ms 32ms 34ms 36ms 38ms 40ms
V(Sa4:C,0) Time
500V
400V
300V
200V
(b)
100V
Reference waveforms Carrier waveforms in phase opposition
0V0Hz 1KHz 2KHz 3KHz 4KHz 5KHz 6KHz 7KHz 8KHz 9KHz 10KHz
V(Sa4:C,0)
Frequency
4299
− Total Harmonic Distortion (THD %) of output
voltage (SPICE simulation results and [13]), TABLE I.
COMPARISON OF MULTILEVEL INVERTERS
− control complexity based on voltage unbalance and
power switches, and Two-
NPCMLI FCMLI CCMLI
Topology Level
− cost estimation ([14]).
Examining the power circuit of a NPCMLI, shown in Main power
Fig. 1, it can be seen that the NPCMLI offers the semiconductor
advantage of having common dc input capacitors for the switches with 2 2(m-1) 2(m-1) 2(m-1)
three phases. Its main disadvantage is that too many free wheeling
diodes are used for clamping, which also makes the diodes per phase
implementation of the physical layout difficult. (m-1)·
Clamping diodes 0 0 0
In a FCMLI, the clamping capacitors’ voltages can be (m-2)
per phase
balanced within a few cycles, by use of voltage synthesis
redundancies. Its main disadvantage is that many DC bus 1 (m-1) (m-1) (m-1)/2
capacitors are used for clamping, though these capacitors capacitors
are cheaper compared to the clamping diodes of the
Balancing (m-1)·
NPCMLI. Furthermore, for low switching frequency, the Capacitors per
0 0
(m-2)/2
0
clamping capacitors become large in size thus decreasing phase
the power density of the inverter. Multi-
In a CCMLI, no clamping capacitors or diodes are Most popular Single- Multi- Multi- carrier
necessary. Furthermore, a low switching frequency can be SPWM control carrier carrier PD carrier PD Phase-
used. Modularized circuit layout and packaging is possible technique Shifted
because each cell has the same structure and there are no
Normalized
extra flying capacitors or clamping diodes. Its main
amplitude of the (m-1)· (m-1)·
disadvantage is the use of an independent dc source for phase voltage
Mf/2 (m-1)Mf
Mf/2 Mf
every cell. For this reason, the CCMLI is used in many PV fundamental
and fuel cells power generation systems. component
As regards the cost of implementation of these inverters
[14], the cost for implementing a NPCMLI breaks down Order of the
phase voltage
to 80% for the construction of the power inverter unit and dominant
Fnc-2 Fnc-10 Fnc-10 2Fnc-7
20% for the construction of the inverter cabinet. The cost harmonic
for implementing a FCMLI breaks down to 45% for the component
construction of the power inverter unit, 20% cost for the
capacitor bank, and 20% for the construction of the Normalized
inverter cabinet. The cost for implementing a CCMLI amplitude of the
breaks down to 65% for the construction of the power phase voltage 0.312 0.063 0.065 0.08
dominant Mf =1 Mf = 0.7 Mf = 0.7 Mf = 0.7
inverter unit and 20% for the construction of the inverter harmonic
cabinet. component
Examining the power circuits of the three under (worst case)
comparison multilevel inverters it can be observed that
they use the same number of semiconductor switches per Normalized
amplitude of the
phase. However, the NPCMLI uses (m-1)(m-2) clamping line-to-line 0.312 0.065 0.065 0.08
diodes thus increasing the cost compared to the other two voltage dominant Mf =1 Mf = 0.7 Mf = 0.7 Mf = 0.7
topologies. The FCMLI and CCMLI need 2(m-1) heat harmonic
sinks whereas the NPCMLI needs 2(m-1)+ (m-1)(m-2). component
As regards modulation, the most popular SPWM (worst case)
control technique for the NPCMLI and the FCMLI is the THD ( %) of
phase disposition one. The most popular SPWM control 156.1% 32.9% 33.1% 33.2%
output phase
technique for the CCMLI is the phase shifted one. voltage
Moreover, examining the frequency spectrum of the
- 1 0.85 0.85
output phase voltage of the three types of multilevel Cost
inverters, it was found out that the same value of THD Very
was obtained when SPWM multi-carrier with phase Voltage Small Average High
Small
Unbalancing
disposition and SPWM with phase-shifted carriers were
Motor Motor PV, Fuel
used. Therefore, the SPWM control technique has the drive drive Cells,
same effect to all three types. Applications systems, systems, Battery
Using the above comparison statements for the three Statcom Statcom Systems
types of the multilevel inverters, Table 1 can be
developed. As it can be seen from Table 1, in order to
generate an m-level multilevel inverter the CCMLI uses
the least amount of semiconductor devices and
consequently requires the lowest implementation cost.
4300
V. CONCLUSIONS [13] D. G. Holmes, “A General Analytical Method for Determining the
Theoretical Harmonic Components of Carrier Based PWM
In the above, a comparison between existing state of the Strategies,” IEEE/IAS Annual Meeting Conf. Rec., pp. 1207-1214,
art multilevel topologies, such as the Neutral Point 1998.
Clamp, Flying Capacitor and Cascaded Cell Multilevel [14] K. Fujii, U. Shcwarzer, and R. De Doncker, “Comparison of Hard-
Switched Multilevel Inverter Topologies for STACOM by loss-
Inverters was performed. The comparison of these Implemented Simulation and Cost Estimation,“ in Proceedings
inverters was based on the criteria of output voltage IEEE PESC ’05, pp.397-403, 2005..
quality, power circuitry complexity and implementation
cost. By applying various modulation techniques to all
three types of multilevel inverters under consideration, it
was found out that multi-carrier based sinusoidal PWM
(phase disposition SPWM for NPCMLI and FCMLI and
Phase-shifted SPWM for CCMLI) have the same output
phase voltage quality, with a THD of the output phase
voltage equal to 33%. Also, it was found that for the same
switching frequency, the order of the most dominant
harmonic component of the phase voltage of the CCMLI
is almost double as that of the NPCMLI and FCMLI.
Finally, it was found out that the NPCMLI has the highest
implementation cost among the three multilevel inverters.
The implementation costs of the FCMLI and CCMLI are
almost the same but lower by 15% than that of NPCMLI.
From the overall comparison it was found out that the
FCMLI and CCMLI topologies are the most promising
ones.
REFERENCES
[1] L. Tolbert, F.Z. Peng, and T.G. Habetler, “Multilevel Inverters for
Electric Vehicle Applications,” IEEE Power Electronics in
Transportation, pp. 79-84, Dearborn, MI, October 22-23, 1998.
[2] L.M. Tolbert, F.Z. Peng, and T.G. Habetler, “Multilevel
Converters for Large Electric Drives,” IEEE Transactions on
Industry Applications, Vol. 35, No.5, pp. 36-44, January/February,
1999.
[3] G. Sinha and T.A. Lipo, “A four level rectifier inverter system for
drive applications,” Proceedings of the IEEE Industry
Applications Society, pp. 980-987, 1996.
[4] P.K. Steiner and M.D. Manjrekar, “Practical Medium Voltage
Converter Topologies for High Power Applications,” IEEE IAS
Conference records, Vol. 3, pp. 1723-1730, 2001
[5] C.K. Lee, J.S.K. Leung, R. Hui and H.S. Chung, “Circuit-Level
Comparison of STATCOM Technologies,” IEEE Transactions on
Power Electronics, Vol. 18, No.4, pp. 1084-1092, July 2003.
[6] C. Hochgraf, R.H. Lasseter, D.M. Divan, and T.A. Lipo,
“Comparison of multilevel Inverters for Static Var
Compensation,” Research Report 94-26, Wisconsin Power
Electronics Center, University of Wisconsin-Madison, 1994.
[7] A. Nabae, I. Takahashi and H. Akagi, “A new neutral-point
clamped PWM inverter,” IEEE Transactions on Industry
Applications, IA-17, No. 5, pp. 518-523, September/October 1981.
[8] P.M. Bhagwatt and V.R. Stefanovic, “Generalized structure of a
multilevel PWM inverter”, IEEE Transactions on Industry
Applications, IA-19, No.5, pp 1057-1069, November/December,
1983.
[9] T.A. Meynard and H. Foch, “Multilevel conversion: High voltage
choppers and voltage source inverters,” in Proceedings IEEE
PESC ’92, pp.397-403, 1992.
[10] A. Rufer, “An aid in teaching of multilevel converters for high
power applications,” in Proceeding IEEE PESC’95, pp.347-352,
1995.
[11] Fang. Z. Peng, John W. Mckeever, and Donald J. Adams, “A
Power Line Conditioner Using Cascade Multilevel Inverters for
Distribution Systems,” IEEE Transactions on Industry
Applications, Vol.34, No.6, pp. 1293-1298, November/ December
1998.
[12] D. G. Holmes and T. A. Lipo, “Pulse Width Modulation for
Power Converters”, Wiley Inter-Science, 2003.
4301