1. The Ebers-Moll model of a BJT is valid D.

none of these
A. only in active mode
B. only in active and saturation modes 5. In the RLC circuit shown in the figure, the input voltage is
C. only in active and cut-off modes given by
D. in active, saturation and cut-off modes

2. Assume that the diode in the figure has Von = 0.7 V, but is
otherwise ideal. The magnitude of the current i2 (in mA) is
equal to _____.

The output voltage v0 (t) is

A. cos (200t) + 2sin (500t)
B. 2 cos (200t) + 4sin (500t)
C. sin (200t) + 2cos (500t)
D. 2 sin (200t) + 4cos (500t)

6. The diodes D1 and D2 in the figure are ideal and the

3. Which one of the following statements is correct about an
capacitors are identical. The product RC is very large
ac-coupled common-emitter amplifier operating in the
compared to the time period of the ac voltage. Assuming
mid-band region?
that the diodes do not breakdown in the reverse bias, the
A. The device parasitic capacitances behave like open
output voltage V0 (in volt) at the steady state is ________.
circuits, whereas coupling and by pass capacitances
behave like short circuits.
B. The device parasitic capacitances, coupling
capacitances and bypass capacitances behave like
open circuits.
C. The device parasitic capacitances, coupling
capacitances and bypass capacitances behave like
short circuits.
D. The device parasitic capacitances behave like short
circuits, whereas coupling and bypass capacitances
behave like open circuits.

4. An op-amp has a finite open loop voltage gain of 100. Its

input offset voltage V iOS (=+5 mV) is modeled as shown
in the circuit below. The amplifier is ideal in all other A. 1
respects. V input Is 25 mV. B. 10
C. 0
D. insufficient data

7. Consider the circuit shown in the figure. Assuming V BE1=

V BE2 = 0.7volt, the value of the dc voltage V C 2 (in volts)
is _______.

The output voltage (in millivolts) is _____

A. 413.79
B. 212.45
C. 342.12
 10. The minimum number of 2-input NAND gates
required to implement a 2-input XOR gate is
A. 4
B. 5
C. 6
D. 7

11. The z-parameter matrix Z11 Z12 for the two-port

Z21 Z22
network shown in

A. 1
B. 0.5
C. 1.20
D. 3

8. In the Astable multivibrator circuit shown in the

figure, the frequency of oscillation (in kHz) at the output
pin 3 is ___________.

12. For the circuit shown in the figure, R1 = R2 = R3 = 1ohm,

L = 1 H and C =1 F If the input V in = cos(106 t) then the
𝑉 𝑜𝑢𝑡
overall voltage gain of the circuit is ______.
𝑉 𝑖𝑛
A. 6.64
B. 7.25
C. 5.64
D. 13

9. The logic functionality realized by the circuit shown below

is

A. -1
B. -3
C. -2
D. -5

13. Following is the K-map of a Boolean function of five

A. OR variables P, Q, R, S and X. The minimum sum-of-product
B. XOR (SOP) expression for the function is
C. NAND
D. AND

14. The Miller effect in the context of a Common Emitter
amplifier explains
A. an increase in the low-frequency cutoff frequency
B. an increase in the high-frequency cutoff
frequency
C. a decrease in the low-frequency cutoff frequency
D. a decrease in the high-frequency cutoff frequency
15. Consider the D-Latch shown in the figure, which is
transparent when its clock input CK is high and has
zero propagation delay. In the figure, the clock
signal CLK1 has a 50% duty cycle and CLK2 is a onefifth
period delayed version of CLK1. The duty cycle
at the output latch in percentage is ____.
A. 30% B. 28%
C. 34% D. 32%
16. For the operational amplifier circuit shown, the
output saturation voltages are ±15V. The upper and
lower threshold voltages for the circuit are,
respectively.
A. +5V and -5V B. +7V and -3V
C. +3V and -7V D. +3V and -3V
17. A good transconductance amplifier should have
A. high input resistance and low output resistance
B. low input resistance and high output resistance
C. high input and output resistances
D. low input and output resistance
18. In the circuit shown, V is a sinusoidal voltage source. The
current I is in phase with voltage V.
A. 0.2 B. 0.3
C. 1 D. 5
19. In a DRAM,
A. periodic refreshing is not required
B. information is stored in a capacitor
C. information is stored in a latch
D. both read and write operations can be performed
simultaneously
20. For the circuit shown in the figure, P and Q are the
inputs and Y is the output.
The logic implemented by the circuit is The logic implemented by the circuit is
A. XNOR B. XOR A. XNOR B. XOR
C. NOR D. OR C. NOR D. OR

21. An n-channel enhancement mode MOSFET is biased 25. The output V0 of the diode circuit shown in the figure
at V GS > VTH and V DS > (V GS -V TH), where V GS is is connected to an averaging DC voltmeter. The
the gate-to-source voltage, DS V is the drain-to-source reading on the DC voltmeter in Volts, neglecting the
voltage and V TH is the threshold voltage. voltage drop across the diode, is ______.
Considering channel length modulation effect to be
significant, the MOSFET behaves as a
A. voltage source with zero output impedance
B. voltage source with non-zero output impedance
C. current source with finite output impedance
D. current source with infinite output impedance

22. A connection is made consisting of resistance A in A. 3.18 B. 4.12

series with a parallel combination of resistances B C. 1.23 D. 10
and C. Three resistors of value 10 ohms ,5 ohms,2 ohms are
provided. Consider all possible permutations of the 26. Consider the circuit shown in the figure. Assume
given resistors into the positions A, B, C, and identify base-to- emitter voltage VBE=0.8 V and common
the configurations with maximum possible overall base current gain (α)of the transistor is unity.
resistance, and also the ones with minimum possible
overall resistance. The ratio of maximum to
minimum values of the resistances (up to second
decimal place) is _____.
A. 2.14 B. 1.12
C. 2 D. 0.24

23. An npn bipolar junction transistor (BJT) is operating

in the active region. If the reverse bias across the
base – collector junction is increased, then
A. the effective base width increases and common –
emitter current gain increases
B. the effective base width increases and common –
emitter current gain decreases
C. the effective base width decreases and common
– emitter current gain increases
D. the effective base width decreases and common
– emitter current gain decreases

24. For the circuit shown in the figure, P and Q are the
inputs and Y is the output.
The value of the collector- to – emitter voltage VCE
(in volt) is _______.
A. 6 B. 5
C. 10 D. 7

27. Assuming that transistors M1 and M2 are identical

and have a threshold voltage of 1V, the state of
transistors M1 and M2 are respectively.

A. Saturation, Saturation
B. Linear, Linear
C. Linear, Saturation
D. Saturation, Linear