INSTRUCTION SET

GROUP Mnemonic Operands Description

Arithmetic & Logical ADD Rd, Rr Add without Rd

Arithmetic & Logical Carry

Arithmetic & Logical ADC Rd, Rr Add with Rd

Arithmetic & Logical Carry

Arithmetic & Logical ADIW Rd, K Add Rd

Arithmetic & Logical Immediate to

Arithmetic & Logical Word

Arithmetic & Logical SUB Rd, Rr Subtract Rd

Arithmetic & Logical without Carry

Arithmetic & Logical SUBI Rd, K Subtract Rd

Arithmetic & Logical Immediate

Arithmetic & Logical SBC Rd, Rr Subtract with Rd

Arithmetic & Logical Carry

Arithmetic & Logical SBCI Rd, K Subtract Rd

Arithmetic & Logical Immediate

Arithmetic & Logical with Carry

Arithmetic & Logical SBIW Rd, K Subtract

Arithmetic & Logical Immediate

Arithmetic & Logical from Word

Arithmetic & Logical AND Rd, Rr Logical AND Rd

Arithmetic & Logical ANDI Rd, K Logical AND Rd

Arithmetic & Logical with

Arithmetic & Logical Immediate

Arithmetic & Logical

Arithmetic & Logical OR Rd, Rr Logical OR Rd

Arithmetic & Logical

Arithmetic & Logical ORI Rd, K Logical OR Rd

Arithmetic & Logical with

Arithmetic & Logical Immediate

Arithmetic & Logical EOR Rd, Rr Exclusive OR Rd

Arithmetic & Logical COM Rd One’s Rd

Arithmetic & Logical Complement

Arithmetic & Logical NEG Rd Two’s Rd

Arithmetic & Logical Complement

Arithmetic & Logical SBR Rd,K Set Bit(s) in Rd

Arithmetic & Logical Register

Arithmetic & Logical CBR Rd,K Clear Bit(s) in Rd

Arithmetic & Logical Register

Arithmetic & Logical INC Rd Increment Rd

Arithmetic & Logical

Arithmetic & Logical DEC Rd Decrement Rd

Arithmetic & Logical TST Rd Test for Zero Rd

Arithmetic & Logical or Minus

Arithmetic & Logical CLR Rd Clear Register Rd

Arithmetic & Logical SER Rd Set Register Rd

Arithmetic & Logical MUL Rd,Rr Multiply R1:R0

Arithmetic & Logical Unsigned

Arithmetic & Logical MULS Rd,Rr Multiply R1:R0

Arithmetic & Logical Signed

Arithmetic & Logical MULSU Rd,Rr Multiply R1:R0

Arithmetic & Logical Signed with

Arithmetic & Logical Unsigned

Arithmetic & Logical FMUL Rd,Rr Fractional R1:R0

Arithmetic & Logical Multiply

Arithmetic & Logical Unsigned

Arithmetic & Logical FMULS Rd,Rr Fractional R1:R0

Arithmetic & Logical Multiply

Arithmetic & Logical Signed

Arithmetic & Logical FMULSU Rd,Rr Fractional R1:R0

Arithmetic & Logical Multiply

Arithmetic & Logical Signed with

Arithmetic & Logical Unsigned

Arithmetic & Logical DES K Data if (H = 0) then

Arithmetic & Logical Encryption R15:R0

Arithmetic & Logical else if (H = 1)

Arithmetic & Logical then R15:R0

Branch Control RJMP k Relative Jump PC

Branch Control IJMP Indirect Jump PC(15:0)

Branch Control to (Z)

PC(21:16)
Branch Control
Branch Control EIJMP Extended PC(15:0)

Branch Control Indirect Jump

PC(21:16)
Branch Control
to (Z)
Branch Control
Branch Control JMP k Jump PC

Branch Control RCALL k Relative Call PC

Branch Control Subroutine

Branch Control ICALL Indirect Call to PC(15:0)

Branch Control (Z)

PC(21:16)
Branch Control
Branch Control EICALL Extended PC(15:0)

Branch Control Indirect Call to

PC(21:16)
Branch Control
(Z)
Branch Control
Branch Control
Branch Control CALL k Call PC

Branch Control Subroutine

Branch Control
Branch Control RET Subroutine PC

Branch Control Return

Branch Control
Branch Control RETI Interrupt PC

Branch Control Return

Branch Control
Branch Control CPSE Rd,Rr Compare, if (Rd = Rr)

Branch Control skip if Equal PC

Branch Control
Branch Control CP Rd,Rr Compare Rd - Rr

Branch Control
Branch Control CPC Rd,Rr Compare with Rd - Rr - C

Branch Control Carry

Branch Control
Branch Control CPI Rd,K Compare with Rd - K

Branch Control Immediate

Branch Control
Branch Control SBRC Rr, b Skip if Bit in if (Rr(b) = 0)

Branch Control Register PC

Branch Control Cleared

Branch Control
Branch Control SBRS Rr, b Skip if Bit in if (Rr(b) = 1)

Branch Control Register Set PC

Branch Control
Branch Control SBIC A, b Skip if Bit in if (I/O(A,b) =

Branch Control I/O Register 0) PC

Branch Control Cleared

Branch Control
Branch Control SBIS A, b Skip if Bit in If (I/O(A,b) =1)

Branch Control I/O Register PC

Branch Control Set

Branch Control
Branch Control BRBS s, k Branch if if (SREG(s) =

Branch Control Status Flag 1) then PC

Branch Control Set

Branch Control
Branch Control BRBC s, k Branch if if (SREG(s) =

Branch Control Status Flag 0) then PC

Branch Control Cleared

Branch Control
Branch Control BREQ k Branch if if (Z = 1) then

Branch Control Equal PC

Branch Control
Branch Control BRNE k Branch if Not if (Z = 0) then

Branch Control Equal PC

Branch Control
Branch Control BRCS k Branch if if (C = 1) then

Branch Control Carry Set PC

Branch Control
Branch Control BRCC k Branch if if (C = 0) then

Branch Control Carry Cleared PC

Branch Control
Branch Control BRSH k Branch if if (C = 0) then

Branch Control Same or PC

Branch Control Higher

Branch Control
Branch Control BRLO k Branch if if (C = 1) then

Branch Control Lower PC

Branch Control
Branch Control BRMI k Branch if if (N = 1) then

Branch Control Minus PC

Branch Control
Branch Control BRPL k Branch if Plus if (N = 0) then

Branch Control PC

Branch Control
Branch Control BRGE k Branch if if (N ⊕ V= 0)

Branch Control Greater or then PC

Branch Control Equal, Signed

Branch Control
Branch Control BRLT k Branch if Less if (N ⊕ V= 1)

Branch Control Than, Signed then PC

Branch Control
Branch Control BRHS k Branch if Half if (H = 1) then

Branch Control Carry Flag PC

Branch Control Set

Branch Control
Branch Control BRHC k Branch if Half if (H = 0) then

Branch Control Carry Flag PC

Branch Control Cleared

Branch Control
Branch Control BRTS k Branch if T if (T = 1) then

Branch Control Flag Set PC

Branch Control
Branch Control BRTC k Branch if T if (T = 0) then

Branch Control Flag Cleared PC

Branch Control
Branch Control BRVS k Branch if if (V = 1) then
Branch Control Overflow Flag PC

Branch Control is Set

Branch Control
Branch Control BRVC k Branch if if (V = 0) then

Branch Control Overflow Flag PC

Branch Control is Cleared

Branch Control
Branch Control BRIE k Branch if if (I = 1) then

Branch Control Interrupt PC

Branch Control Enabled

Branch Control
Branch Control BRID k Branch if if (I = 0) then

Branch Control Interrupt PC

Branch Control Disabled

Branch Control
Data Transfer MOV Rd, Rr Copy Register Rd

Data Transfer
Data Transfer MOVW Rd, Rr Copy Register Rd+1:Rd

Data Transfer Pair

Data Transfer
Data Transfer LDI Rd, K Load Rd

Data Transfer Immediate

Data Transfer
Data Transfer LDS Rd, k Load Direct Rd

Data Transfer from data

Data Transfer space

Data Transfer
LD Rd, X Load Indirect Rd
Data Transfer
Data Transfer LD Rd, X+ Load Indirect Rd

Data Transfer and Post-

X
Data Transfer
Increment
Data Transfer
Data Transfer
Data Transfer LD Rd, -X Load Indirect X

Data Transfer and Pre-

Rd
Data Transfer
Decrement
Data Transfer
Data Transfer
LD Rd, Y Load Indirect Rd
Data Transfer
Data Transfer LD Rd, Y+ Load Indirect Rd

Data Transfer and Post-

Y
Data Transfer
Increment
Data Transfer
Data Transfer
Data Transfer LD Rd, -Y Load Indirect Y

Data Transfer and Pre-

Rd
Data Transfer
Decrement
Data Transfer
Data Transfer
Data Transfer LDD Rd, Y+q Load Indirect Rd

Data Transfer with

Data Transfer Displacement

Data Transfer
LD Rd, Z Load Indirect Rd
Data Transfer
Data Transfer LD Rd, Z+ Load Indirect Rd

Data Transfer and Post-

Z
Data Transfer
Increment
Data Transfer
Data Transfer
Data Transfer LD Rd, -Z Load Indirect Z

Data Transfer and Pre-

Rd
Data Transfer
Decrement
Data Transfer
Data Transfer
Data Transfer LDD Rd, Z+q Load Indirect Rd

Data Transfer with

Data Transfer Displacement

Data Transfer
Data Transfer STS k, Rr Store Direct to (k)

Data Transfer Data Space

Data Transfer
ST X, Rr Store Indirect (X)
Data Transfer
Data Transfer ST X+, Rr Store Indirect (X)

Data Transfer and Post-

X
Data Transfer
Increment
Data Transfer
Data Transfer
Data Transfer ST -X, Rr Store Indirect X

Data Transfer and Pre-

(X)
Data Transfer
Decrement
Data Transfer
Data Transfer
ST Y, Rr Store Indirect (Y)
Data Transfer
Data Transfer ST Y+, Rr Store Indirect (Y)
Data Transfer and Post-
Y
Data Transfer
Increment
Data Transfer
Data Transfer
Data Transfer ST -Y, Rr Store Indirect Y

Data Transfer and Pre-

(Y)
Data Transfer
Decrement
Data Transfer
Data Transfer
Data Transfer STD Y+q, Rr Store Indirect (Y + q)

Data Transfer with

Data Transfer Displacement

Data Transfer
ST Z, Rr Store Indirect (Z)
Data Transfer
Data Transfer ST Z+, Rr Store Indirect (Z)

Data Transfer and Post-

Z
Data Transfer
Increment
Data Transfer
Data Transfer
Data Transfer ST -Z, Rr Store Indirect Z

Data Transfer and Pre-

Data Transfer Decrement

Data Transfer
Data Transfer STD Z+q,Rr Store Indirect (Z + q)

Data Transfer with

Data Transfer Displacement

Data Transfer
Data Transfer LPM Load Program R0

Data Transfer Memory

Data Transfer
Data Transfer LPM Rd, Z Load Program Rd

Data Transfer Memory

Data Transfer
Data Transfer LPM Rd, Z+ Load Program Rd

Data Transfer Memory and

Z
Data Transfer
Post-
Data Transfer
Data Transfer Increment

Data Transfer
Data Transfer ELPM Extended R0

Data Transfer Load Program

Data Transfer Memory

Data Transfer
Data Transfer ELPM Rd, Z Extended Rd

Data Transfer Load Program

Data Transfer Memory

Data Transfer
Data Transfer ELPM Rd, Z+ Extended Rd

Data Transfer Load Program

(RAMPZ:Z)
Data Transfer
Memory and
Data Transfer
Data Transfer
Post-
Data Transfer
Data Transfer Increment

Data Transfer
Data Transfer SPM Store (RAMPZ:Z)

Data Transfer Program

Data Transfer Memory

Data Transfer
Data Transfer SPM Z+ Store (RAMPZ:Z)

Data Transfer Program

Z
Data Transfer
Memory and
Data Transfer
Data Transfer Post-

Data Transfer Increment by

Data Transfer 2

Data Transfer
Data Transfer IN Rd, A In From I/O Rd

Data Transfer Location

Data Transfer
Data Transfer OUT A, Rr Out To I/O I/O(A)

Data Transfer Location

Data Transfer
Data Transfer PUSH Rr Push Register STACK

Data Transfer on Stack

Data Transfer
Data Transfer POP Rd Pop Register Rd

Data Transfer from Stack

Data Transfer
Data Transfer XCH Z, Rd Exchange (Z)

Data Transfer Rd

Data Transfer
Data Transfer LAS Z, Rd Load and Set (Z)

Data Transfer Rd

Data Transfer
Data Transfer LAC Z, Rd Load and (Z)

Data Transfer Clear

Rd
 Rd
Data Transfer
Data Transfer
Data Transfer
Data Transfer LAT Z, Rd Load and (Z)

Data Transfer Toggle

Rd
Data Transfer
Data Transfer
Bit and Bit LSL Rd Logical Shift Rd(n+1)

Bit and Bit Left

Rd(0)
Bit and Bit
Bit and Bit C

Bit and Bit

Bit and Bit LSR Rd Logical Shift Rd(n)

Bit and Bit Right

Rd(7)
Bit and Bit
Bit and Bit C

Bit and Bit

Bit and Bit ROL Rd Rotate Left Rd(0)

Bit and Bit Through

Rd(n+1)
Bit and Bit
Carry
Bit and Bit
C
Bit and Bit
Bit and Bit
Bit and Bit ROR Rd Rotate Right Rd(7)

Bit and Bit Through

Rd(n)
Bit and Bit
Carry
Bit and Bit
C
Bit and Bit
Bit and Bit
Bit and Bit ASR Rd Arithmetic Rd(n)

Bit and Bit Shift Right

Bit and Bit

Bit and Bit SWAP Rd Swap Nibbles Rd(3..0)

Bit and Bit

Bit and Bit SBI A, b Set Bit in I/O I/O(A, b)

Bit and Bit Register

Bit and Bit

Bit and Bit CBI A, b Clear Bit in I/O(A, b)

Bit and Bit I/O Register

Bit and Bit

Bit and Bit BST Rr, b Bit Store from T

Bit and Bit Register to T

Bit and Bit

Bit and Bit BLD Rd, b Bit load from Rd(b)

Bit and Bit T to Register

Bit and Bit
Bit and Bit BSET s Flag Set SREG(s)

Bit and Bit

Bit and Bit BCLR s Flag Clear SREG(s)

Bit and Bit

Bit and Bit SEC Set Carry C

Bit and Bit

Bit and Bit CLC Clear Carry C

Bit and Bit

Bit and Bit SEN Set Negative N

Bit and Bit Flag

Bit and Bit

Bit and Bit CLN Clear N

Bit and Bit Negative Flag

Bit and Bit

Bit and Bit SEZ Set Zero Flag Z

Bit and Bit

Bit and Bit CLZ Clear Zero Z

Bit and Bit Flag

Bit and Bit

Bit and Bit SEI Global I

Bit and Bit Interrupt

Bit and Bit Enable

Bit and Bit

Bit and Bit CLI Global I

Bit and Bit Interrupt

Bit and Bit Disable

Bit and Bit

Bit and Bit SES Set Signed S

Bit and Bit Test Flag

Bit and Bit

Bit and Bit CLS Clear Signed S

Bit and Bit Test Flag

Bit and Bit

Bit and Bit SEV Set Two’s V

Bit and Bit Complement

Bit and Bit Overflow

Bit and Bit

Bit and Bit CLV Clear Two’s V

Bit and Bit Complement

Bit and Bit Overflow

Bit and Bit

Bit and Bit SET Set T in T

Bit and Bit SREG

Bit and Bit

Bit and Bit CLT Clear T in T

Bit and Bit SREG

Bit and Bit

Bit and Bit SEH Set Half Carry H

Bit and Bit Flag in SREG

Bit and Bit

Bit and Bit CLH Clear Half H

Bit and Bit Carry Flag in

Bit and Bit SREG

Bit and Bit

MCU Control BREAK Break (See also in

MCU Control Debug interface

MCU Control description)

MCU Control
MCU Control NOP No Operation

MCU Control
MCU Control SLEEP Sleep (see also power

MCU Control management and

MCU Control sleep description)

MCU Control
MCU Control WDR Watchdog Reset (see also

MCU Control Watchdog

MCU Control Controller

MCU Control description)

MCU Control

Note:  “RETI – Return from Interrupt”

“LAC - Load and Clear”
"LAS – Load and Set"
"LAT – Load and Toggle"
"XCH – Exchange"
"CBI – Clear Bit in I/O Register"
"LD – Load Indirect from Data Space to Register using Index X"
"LD (LDD) – Load Indirect from Data Space to Register using Index Y"
"LD (LDD) – Load Indirect From Data Space to Register using Index Z"
"RCALL – Relative Call to Subroutine"
"SBI – Set Bit in I/O Register"
"ST – Store Indirect From Register to Data Space using Index X"
"ST (STD) – Store Indirect From Register to Data Space using Index Y"
"ST (STD) – Store Indirect From Register to Data Space using Index Z"
"LDS (16-bit) – Load Direct from Data Space"
"STS (16-bit) – Store Direct to Data Space"
STRUCTION SET
#Clocks #Clocks #Clocks #Clocks

Op Flags
AVR AVRxm AVRxt AVRrc

← Rd + Rr Z,C,N,V,S,H 1 1 1 1

← Rd + Rr + C Z,C,N,V,S,H 1 1 1 1

← Rd + 1:Rd + K Z,C,N,V,S 2 2 2 N/A

← Rd - Rr Z,C,N,V,S,H 1 1 1 1

← Rd - K Z,C,N,V,S,H 1 1 1 1

← Rd - Rr - C Z,C,N,V,S,H 1 1 1 1

← Rd - K - C Z,C,N,V,S,H 1 1 1 1

← Rd + 1:Rd - K Z,C,N,V,S 2 2 2 N/A

← Rd • Rr Z,N,V,S 1 1 1 1

← Rd • K Z,N,V,S 1 1 1 1

← Rd v Rr Z,N,V,S 1 1 1 1

← Rd v K Z,N,V,S 1 1 1 1

← Rd ⊕ Rr Z,N,V,S 1 1 1 1

← $FF - Rd Z,C,N,V,S 1 1 1 1

← $00 - Rd Z,C,N,V,S,H 1 1 1 1

← Rd v K Z,N,V,S 1 1 1 1

← Rd • ($FFh - Z,N,V,S 1 1 1 1

K)

← Rd + 1 Z,N,V,S 1 1 1 1
← Rd - 1 Z,N,V,S 1 1 1 1

← Rd • Rd Z,N,V,S 1 1 1 1

← Rd ⊕ Rd Z,N,V,S 1 1 1 1

← $FF None 1 1 1 1

← Rd x Rr (UU) Z,C 2 2 2 N/A

← Rd x Rr (SS) Z,C 2 2 2 N/A

← Rd x Rr (SU) Z,C 2 2 2 N/A

← Rd x Rr<<1 Z,C 2 2 2 N/A

(UU)

← Rd x Rr<<1 Z,C 2 2 2 N/A

(SS)

← Rd x Rr<<1 Z,C 2 2 2 N/A

(SU)

← Encrypt(R15: N/A 2-Jan N/A N/A

R0, K)
←
Decrypt(R15:

R0, K)

← PC + k + 1 None 2 2 2 2

← Z None 2 2 2 2

← 0

← Z None 2 2 2 N/A

← EIND

← k None 3 3 3 N/A

← PC + k + 1 None (1) (1) 3-Feb (1)

3/4 2/3 3

← Z None (1) (1) 3-Feb (1)

3/4 2/3 3

← 0

← Z None (1) (1) 3-Feb N/A

4 3

← EIND
← k None 4 / 5(1) 3 / 4(1) 4-Mar N/A

← STACK None 4 / 5(1) 4 / 5(1) 5-Apr

6
(1)

← STACK I 4 / 5(1) 4 / 5(1) 5-Apr

6
(1)

← PC + 2 or 3 None 1/2/2003 1/2/2003 1/2/2003 2-Jan

Z,C,N,V,S,H 1 1 1 1

Z,C,N,V,S,H 1 1 1 1

Z,C,N,V,S,H 1 1 1 1

← PC + 2 or 3 None 1/2/2003 1/2/2003 1/2/2003 2-Jan

← PC + 2 or 3 None 1/2/2003 1/2/2003 1/2/2003 2-Jan

← PC + 2 or 3 None 1/2/2003 2/3/2004 1/2/2003 2-Jan

← PC + 2 or 3 None 1/2/2003 2/3/2004 1/2/2003 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← PC + k + 1 None 2-Jan 2-Jan 2-Jan 2-Jan

← Rr None 1 1 1 1

← Rr+1:Rr None 1 1 1 N/A

← K None 1 1 1 1

← (k) None (1) (1) (1) 2

2 2 3

← (X) None (1) (1) (1) 2-Jan

2 1 2
← (X) None (1) (1) (1) 3-Feb
2 1 2

← X+1

← X-1 None (1) (1) (1) 3-Feb

2 2 2

← (X)

← (Y) None (1) (1) (1) 2-Jan

2 1 2
← (Y) None (1) (1) (1) 3-Feb
2 1 2

← Y+1
← Y-1 None (1) (1) (1) 3-Feb
2 2 2

← (Y)

← (Y + q) None (1) (1) (1) N/A

2 2 2

← (Z) None (1) (1) (1) 2-Jan

2 1 2
← (Z) None (1) (1) (1) 3-Feb
2 1 2

← Z+1

← Z-1 None (1) (1) (1) 3-Feb

2 2 2

← (Z)

← (Z + q) None (1) (1) (1) N/A

2 2 2

← Rd None (1)(2) (1)(2) (1)(2) 1

2 2 2

← Rr None (1)(2) (1)(2) (1)(2) 1

1 1 1
← Rr None (1)(2) (1)(2) (1)(2) 1
1 1 1

← X+1

← X-1 None (1)(2) (1)(2) (1)(2) 2

2 2 1

← Rr

← Rr None (1)(2) (1)(2) (1)(2) 1

2 1 1
← Rr None (1)(2) (1)(2) (1)(2) 1
2 1 1
← Y+1

← Y-1 None (1)(2) (1)(2) (1)(2) 2

2 2 1

← Rr

← Rr None (1)(2) (1)(2) (1)(2) N/A

2 2 1

← Rr None (1)(2) (1)(2) (1)(2) 1

2 1 1
← Rr None (1)(2) (1)(2) (1)(2) 1
2 1 1

← Z+1

← Z-1 None (1)(2) (1)(2) (1)(2) 2

2 2 1

← Rr None (1)(2) (1)(2) (1)(2) N/A

2 2 1

← (Z) None 3 3 3 N/A

← (Z) None 3 3 3 N/A

← (Z) None 3 3 3 N/A

← Z+1

← (RAMPZ:Z) None 3 3 3 N/A

← (RAMPZ:Z) None 3 3 3 N/A

← (RAMPZ:Z) None 3 3 3 N/A

← (RAMPZ:Z) +

← R1:R0 None -4 -4 4
(3) N/A

← R1:R0 None -4 -4 4
(3) N/A

← Z+2

← I/O(A) None 1 1 1 1

← Rr None 1 1 1 1

← Rr None 2 (1) 1 (1)

1 1

← STACK None 2 (1) 2 (1)

2 3

← Rd None N/A 1 N/A N/A

← (Z)

← Rd v (Z) None N/A 1 N/A N/A

← (Z)

← ($FF – Rd) • None N/A 1 N/A N/A

(Z)
←
←

(Z)

← Rd ⊕ (Z) None N/A 1 N/A N/A

← (Z)

← Rd(n) Z,C,N,V,H 1 1 1 1

← 0

← Rd(7)

← Rd(n+1) Z,C,N,V 1 1 1 1

← 0

← Rd(0)

← C Z,C,N,V,H 1 1 1 1

← Rd(n)

← Rd(7)

← C Z,C,N,V 1 1 1 1

← Rd(n+1)

← Rd(0)

← Rd(n+1), Z,C,N,V 1 1 1 1

n=0..6

↔ Rd(7..4) None 1 1 1 1

← 1 None 2 1 1 1

← 0 None 2 1 1 1

← Rr(b) T 1 1 1 1

← T None 1 1 1 1
← 1 SREG(s) 1 1 1 1

← 0 SREG(s) 1 1 1 1

← 1 C 1 1 1 1

← 0 C 1 1 1 1

← 1 N 1 1 1 1

← 0 N 1 1 1 1

← 1 Z 1 1 1 1

← 0 Z 1 1 1 1

← 1 I 1 1 1 1

← 0 I 1 1 1 1

← 1 S 1 1 1 1

← 0 S 1 1 1 1

← 1 V 1 1 1 1

← 0 V 1 1 1 1

← 1 T 1 1 1 1
 ← 0 T 1 1 1 1

← 1 H 1 1 1 1

← 0 H 1 1 1 1

None 1 1 1 1

None 1 1 1 1

None 1 1 1 1

None 1 1 1 1

g Index X"
er using Index Y"
er using Index Z"

ng Index X"
ce using Index Y"
ce using Index Z"