A5 Microelectronic Systems 5 Nyquist AD

Microelectronic SYSTEMS
Part 5: Nyquist rate A/D converters
D. Strle
E-mail: drago.strle@fe.uni-lj.si
Overview:
1. Introduction
2. Flash AD converter
3. Sub ranging and two-step converter
4. Folding and interpolation
5. Time-interlieved converter
6. Successive approximation converter
7. Pipeline converter
8. Algorithmic converter
9. Integrating converter
10. Voltage to frequency converter
2018/2019 Microelectronic systems 2
1
Introduction
This session presents some architectures, features and limitis of Nyquist rate A/D
Converters.
The main feature is low ratio between sampling frequency and usefull frequency
Band.
The main problem is complicated antialiasing filter and therefore big silicon area and
high power consumption.
Important basic characteristics: x(t) Antialiasing

y(nt)
Nyquist A/D Digital
• Max. Frequency for high speed Analog filter
output
input
• Timing accuracy
fs=fn
• Metastability
|H(ω)|
• Reference voltage
fo fs/2 fs f
Introduction - Max. Frequency for high speed
Usable speed of the technology:
f T   f Tech   ;   2  6 For OTA or OPAMP  v  t   Au  t 

in Input to a system 

vout  t   vin  t  1  e t    Output of a first order system;
1
= ;  is feedback factor; f T is GBW of the opamp
2 f T
N bit ADC needs accuracy better than 2  N 1 ;  tsett     N  1 ln  2 
1   fT fT  N  1 ln  2 
f clk   ;   
2  tsett  N  1 ln  2  f clk 
2
Introduction - Max. Frequency for high speed
Example 1: Calculate max. Band of input signal!

• N=10
• ftech=1.6GHz
• α=2, β=0.5
• AAF uses 1 octave for the transition band
Solution:
f tech 1
fT   0.8GHz;    0.398ns; tsett    n  1 ln  2   2.7ns;
 2 f T 
1 f
f CK   T  164.8MHz;   4.85
2  tsett 
f CK
f sig   82.4 MHz;
2
Transition band is from: f B to f sig  f B
f sig  f B f sig
 2     f sig f B  ;    3; fB   27.5MHz
fB 3
Introduction – Timing accuracy
Sampling jitter produce error:

dVin
 Vin  Tij ; Tij  1 ps for N  12; f s  20MHz; A  1
dt
Clock propagation delay:

RU CU L2
TD   ; RU CU  1017 s / m2 ;
4 4
At what length L the delay is 1ps?
3
Introduction – Metastability error
Metastabiliy occurs when output of a comparator is undefined at the end of sampling

causing „buble“ error in a termometer code.
Cp
Regenerative time-constant : L 
gm
t
V0  rL
Metastability Error probability : PE  e
Vin A0
V0 is voltage swing required for valid logic level
1
tr = is period of latch phase
Example: 2  fs
VFS  V0 , N  8,  L  2 1010 ; PE  PE ,max for Vin 

VFS
2 N 1
A0  103 , PE ,max  104  Vo 2 N 1  1
f s  ln  
1  P V A  2
fs   293MHz  E ,max FS 0  L
17  L
Flash AD converter - 1
Na ADC Identifies quantization interval that contains input signal.

Flash converter do that in parallel:
i 1 2
Vr ,i  Vref  
2 1
N Vref   Vref   ; i  1, 2,...2 N  1
Errors (Vref):
• Static
• Matching
• Dynamic
Errors (comparators):
• Offset
• Meta-stability
4
Layout strategies for resistor string:
Expected matching: 0.05% to 0.1% with careful layout

a) Series connection: pitch=7.5um, L=485um (poor layout)
b) More compact arrangement: pitch=3.5um, L=230um ( better )
c) Folded line arrangement: pitch=1.75um, L=125um ( much
better )
INL estimation due to gradient:
Rpoly=25Ω/□
Runit=50 Ω
Gradient= 300ppm (linear)
Error sources:
b • Temperature gradient
• TC<=10000ppm/°C
• Voltage dependency
• Dynamic errors (resistance-
capacitance)
5
Offset of comparators is added directly to the reference voltage and modifies the
transition threshold.
 i  Vth ,i  Vth ,i 1    Voff ,i  Voff ,i 1
LSB
For monotonous ADC and no missing codes Voff ,i 
2   
For example:
N  8, VFS  1V ,   3.3 to ensure 99.9% yield: Voff  0.59mV
AVth I  W L    Cox   V gs VTH  L

VTH  ;  dim  d    
WL g m  W L  Cox   2 L
Voff , MOS  VTH2   dim

2
0.6mV
For 0.18um process: AVT  1 mV  m ; VGS  Vth   0.12; VTH   dim  ;
2
Voff is several mV for CMOS.
Flash AD converter – 4: example
Estimate the offset of a CMOS comparator:
W  5 m mA 2mV L
  ; g m  0.8 ; I bias  80uA; AVT  ;  1.8%
 L  0.18 m V m L
Solution:
2
4 106  80 106 
Voff , MOS   3 
0.00182  2.77mV
0.9  0.8 10 
The offset of a comparator is too big to be useful and to reach good yield (99.9%
for example)
LSB
3.3 off    off  LSB  0.15 sub mV range
2
 Auto-zero technique
6
Flash AD converter – 5: auto zero
 AZ : Vout  Vos   AZ 
V in  Vos   AZ 
VCos   AZ   V1   AZ   Vos   AZ 
 AZ : Vout   AZ   A0Vd ,in   AZ  (decision HI or LO )
 
Vd ,in   AZ   Vin    AZ   Vin    AZ  
Vd ,in   AZ   V2   AZ   V1   AZ   Vos   AZ   Vos   AZ  

for Vos   AZ   Vos   AZ 
Vd ,in   AZ   V2   AZ   V1   AZ 
Flash AD converter – 5: auto zero: Home work
N=8, Ru=25Ω, VFS=1V, Cpar=6.25fF

Estimate the transient of the tap voltage for conversion of 0.5625V.
Use the approximate model (b) for the spice simulation:
7
Flash AD converter – 6:
Practical limits:
• Small unit resistance is needed to maintain the speed and small area
 Loading the reference (DC to HF)
 For fs>100MHz, reference is critical
• Exponential increase (with N) of area and power
• Metastability of a comparator
• Capacitive load of the S&H circuit:
• For N=8, α=0.1, fs=500MHz, 2^NCp=2.5pF
f s  2 N C par  Vin,max
I S & H , peak   16mA
2
 For fs>500MHz and N=8 the circuit is impractical
 For fs>2GHz and N=6 the circuit is impractical
Sub ranging A/D converter
Vco for Vco  i  1  Vin  Vco  i  ;

Vres Vin   K Vin  Vdac  i  
For M=N=4 we need:

• 2(2^4-1)=30 comparators compared to 256 for full flash
• Smaller area and power
• Much smaller load of S&H
reduced conversion rate ( potentially; it can be even faster because of
reduced cap. load )
8
Sub ranging A/D converter - accuracy requirements
S&H circuit noise: Error of coarse ADC:
– kT/C < 1/2LSB  CS&H=0.5pf
– leads to Vn,kT/C=90uV (not very demanding )
• Error of coarse ADC
• Error of DAC:
• Error of fine ADC
The errors of the ADC are easy to correct

because they are localized around brake-points.
The errors of the DAC are hard to correct

because they extend over entire fine conversion
intervals
Nonlinearity spread the spectrum over entire band.

The band larger than fN
Sub ranging A/D converter – as a nonlinear process
Residue of the two-step converter can be described as a non-linear transformation.

Nonlinearity spread the spectrum over entire band.
The band larger than fN
9
Folding and interpolation - 1
Folding bends the input in

sectors.
Folding M times leads to
2M sectors.
Critical points are at the
Edges of the segments:
Critical points
• Real circuit can not
realize that
• Operating in different
segments means
different speed
• High band is needed
n bit ADC with M bit folder
requires N=2n  M -1 comparators
Folding and interpolation – double folding
Ideal and real folding
Double folding to avoid

nonlinear regions:
Discard the unwanted
regions.
Linear regions are
quantized with fine
Quantizer.
10
Folding architectures: Current based
Problem:
• Describe the circuit and determine basic equations of its operation
Folding architectures: Voltage based
11
Interpolation
Definition:
An interpolator generates value that is intermediate between two other values
(voltage,…) using resistive or capacitive dividers for voltage or current division.
V1 R2  V2 R1 V1C1  V2C2
Vint er  Vint er  1   I int er    I1  1     I 2
R1  R2 C1  C2
W L 1,i W L 2,i
 ; 1  ;
W L 1 W L 2
Interpolation in flash converters
Reduction of
• Preamplifiers,
• parasitic caps,
• reference taps,
• Improved settling
12
Interpolation in folding converters
Possible use of multiple interpolators in the fine flash converter
Response of 2 folded responses.

Zero crossing must be mid-way
Between 2 zero crossing of the
generating signal.
Internal impedance of the

preamplifiers does not need to be
much smaller than interpolation
resistor network because the
zero crossing is important.
Interpolation circuit averages the

offset of amplifiers; next slide
Interpolation – improved linearity
Preamplifier
equivalent circuit
13
Time interlieved converter
Increase the conv. Rate by N
Very demanding S&H because

It runs with fs
Alternative is to use N S&H

stages running at fs/N but
delayed by appr. time. This
solution demands:
• precise clock
• Low or equal offset
• Low or equal gain difference
Time interlieved converter – Accuracy requirements:clock
Clock misaligment:
• Similar problem as jitter.
• If delay errors are fixed the error occurs with period fs/N:
• For clock missaligment between K-th channel and 1st channel δK and sinewave input signal
the error is ( sampled at fs/N) :
dVin
 clk , K   K   K Ainin cos in nT  ; n  i  N  K
dt nT
Pin K2  in2
P ,clk 
N
Pin P 1
SNDR   in
Pn  P ,clk Pn  Pin 
1   K  in
2 2

 N  Pn 
14
Time interlieved converter – Accuracy requirements: offset
• Identical offset in all chanells causes only overall offset  usually not a problem
• Different offsets bring tones at fs/N and its multiples  fall into the base-band of
signal band
• Allowed Vof missmatch is defined by SFDR. Worst case scenario have offsets with
+Voff and –Voff for adjacent chanels, which leads to square-wave with 1st
harmonic with amplitude:
Voff , H 1   4 Voff  
   VFS 
SFDR  20 log10  
 2  4 V
 off 
 8
Voff    0.32 LSB for SNR=SFDR
8 12
For 10bits, VFS  1V , and 99% yield  2.57 off  0.5 LSB 
 off  0.19mV
Time interlieved converter – Accuracy requirements: gain
• Identical gain errors are not a problem  gain error of the complete converter
• Different gains: causes tones because of multiplication of input signal with different
chanel gains. Worst case occurs for alternating gains (1+εG) and (1-εG), which is
equivalent as multiplication of input signal with square-wave having amplitude 2 εG
at fs/2 and/or its multiples.
The largest component occur at: (fs/2±fin) or (fs/4±fin) ....with amplitude:
4
AG , H 1    G  Ain

   Ain    
SFDR  20  log10    20  log10  
 4   G  Ain   4  G 
For example:
 G  0.1% leads to SFDR  58dB
15
Time interlieved converter- Example
4 chanel interlieved ADC uses:

B=10, fs=60MS/s, VFS=1V,
Required SFDR=70dB at input signal Vin=-6dB, fin=120MHz.
Determine:
• Offset and gain missmatch
• Max. Clock missaligment for SNDR>59dB at Vin=Vfs
Solution:
 VFS
Voff  103.5  0.12mV very difficult to achieve
8

 G  103.5
 2.5 104 very difficult to achieve
4
SFDR=SnR-3dB;  mis
2
 in2 Pin =NPQ
4 8
 mis   2.1 ps This is not very critical for low resolution converters;
12  2 120 106  210
For higher resolution and frequency it requires special care in clock distribution
Succesive approximation converters: priciples of operation
16
Succesive approximation converters: errors - 1
An error of the bit estimation propagates through all remaining steps.

For example the error on figure below produces 01110000 instead of 01101110: 2LSB
Vfs=1.0V, Vsh=0.430V
Error sources:
• S&H
• Comparator
• DAC
They produce random term and INL and DNL
Succesive approximation converters: errors - 2
Home-work:
Simulate with matlab a static behavior of an 8-bit successive approximation converter.
Use slow ramp as an input and estimate INL and DNL. Model the non-ideality of the
DAC using 2nd and 3rd order harmonic distortions terms.
Write first a matlab program for ideal SA ADC.
17
Succesive approximation converters: charge redistribution - 1
C1
1st : step Φs pre-charging phase: Qtot  2 CuVin

n
2nd : step C1 connected to Vref; all other capacitors to ground:

V
Vcomp  2   ref  Vin ;
2
3Vref
if Vcomp  2   1 than C1 remains connected to Vref ; MSB=1; Vcomp  3   Vin
4
Vref
if Vcomp  2   0 than C1 connects to ground ; MSB=0 ; Vcomp  3   Vin
4
Succesive approximation converters: charge redistribution - 2
Parasitic capacitance of the top plate Cp attenuates the voltage on comparator input
by factor α but does not change the sign, so it is not a contributor to the errors:
Cu 2n

Cu 2n  C p
This happens because of pre-charging phase.
Auto-zero of the comparator could be used for offset cancellation
To reduce the capacitor spread a capacitive attenuation…
18
Pipeline converters: architecture
Basic principle of pipe-line ADC

The first correct output appears
after (K+1) clock periods.
Rearranging clocks of a 2 step flash:

The first stage determines MSBs
while at the same time the second
stage determines LSBs of previous
phase.
Pipeline converters: residue generator transfer characteristics
 
Vres  j   Vres  j  1  VDAC  b j  K j
n
For DAC gain GDAC  2 j the DR of residue is equal to DR of input
This allows the same reference voltage used in all stages
1 bit ADC and DAC, K=2 3 bit ADC and DAC, K=8
19
Pipeline converters: accuracy - 1
Residue response ADC error:

1 bit ADC and DAC, K=2
Ideal DAC and K
Residue response ADC error:

3 bit ADC and DAC, K=8
Ideal DAC and K
ADC:
Accuracy requirement is greatest for the first stage in the pipeline and S&H stage.
Figure above show error of the ADC threshold for 1 bit and 3 bit case with
• ideal DAC
• Ideal amplifier (K)
An error will not occur until ADC of the next stage will not be able to convert
residue voltage outside the range (±Vref).
This is the basis for error correction.
Pipeline converters: accuracy - 2
DAC:
• DAC error of the first stage modify residue over complete LSBs segment.
• Input referred INL of any DAC must be better than INL of the converter
and better than 1LSB to maintain monotonicity ( at the input !! ). Therefore, the
accuracy requirement for each successive DAC is relaxed since residue is divided
by 2k. After a few stages INL of DAC becomes of no concern
GAIN:
• Interstate increases or decreases the slope of the residue; the error is zero in the
middle and max at the ending of the segment.
Gj  2
nj
1   G 
V   G  2Vref
• ΔV referred to the input must be less than INL ( less than LSB to ensure
monotonicity )
20
Pipeline converters: digital correction - 1
Errors caused by non-idealities in the ADC can be cancelled out using digital
correction technique.
The error occurs when next stage can not properly convert out-of-range signal.
Solution:
Add additional levels to the ADC. This redundant levels:
• Avoids out-of-range residuals
• Provide info for digital domain
For example 1 bit DAC requires 1 threshold.
Adding 2 threshold (symmetrical around zero) levels to the ADC has name
1.5bit/stage
(1.5bits because 2 bits ADC employs 3 levels)
Pipeline converters: dynamic performances

The dynamic performances of a pipe-line converters depend on:
• Bandwidth
• Slew-rate
of circuits used in S&H, and residue generator
Real approach requires behaviour analysis prior to time-consuming transistor

level study. It can haelp in definition of active block specifications.
Similar analysis as for S&H dynamic behaviour could be used also for residue
generator.
S&H of next stage samples the
Vout  t   SR  t t  tslew residue at Ts/2

Vout  t   V out  V  e
 t tslew  
 t  tslew
 Exponential settling produce
nonlinear error.
Settling error is important at the
V out 1 begenning and is reduced in later
V  SR  ; tslew   ;  
SR 2 fT  stages ( errors devided by previous
interstage gains)
fT is unity gain bandwidth Use this equ. for behavioral.
 is feedback factor simulations
21
Algorithmic A/D converter
Vout1  2 Vin  Vref 

 V 
 2  Vin  ref 
 2 
Integrating A/D converter
2n Tclk kTclk
Vin  Vref
 
Vref
Vin  k ;
2n
k is digital conversion result
22
Voltage to frequency converter
Problems
1. Repeat Example 2 but for the interconnection use polysilicon with specific
resistance of 20 Ω/□ and parasitic capacitance of 0.7 fF /µm2 . The length of the
interconnection is 100 µm.
2. A comparator must be able to detect an input signal with 5 mV accuracy. The
parasitic capacitance of the regenerative loop of the latch is 0.1 pF and the gain of
the pre amplifier is 100. Determine the transconductance of the regenerative loop
that ensures a metastability error probability equal to 0.001 at 400 MHz.
3. The resistive divider used to generate the reference voltages for 8-bit flash
converter is a serpentine made by 32 unity elements per linear segment. The value
of resistances is affected by a gradient by 0.1% per resistance position in both y
and x directions. Determine the maximum INL and estimates the harmonic
distortion for a full scale input sine wave.
4. Determine the transistor sizing of an MOS pre-amplifier which differential pair
uses 300 µA bias current and uses 300 mV overdrive. The variance of the
offset must be 1 mV with dominant contribution from the tem controlled by the
process parameter AVT = 1.6 mV /µ.
23
Problems
5. Estimate the attenuation of a sinusoidal component of the 1/f noise at 2 kHz in an

auto-zeroed comparator running at 2 MHz. Solve the problem assuming
considering at the input of the offset a normal sine wave with amplitude 1.
6. Repeat the Example 4.5 but assume a finite on-resistance of the switch is
5Ω. Estimate the improvement with two equal shunting resistances connecting
the two reference voltages to the middle point.
7. The overdrive of the input differential pair of a preamplifer is 360 mV and its output
load is 0.2pF. Estimate required bias current that obtains a gain equal to 6 when
the preamplifier run at 1 GHz.
8. Determine the optimum splitting of the bits in a 10-bit two step converter taking as
decision factor the power consumption. The converter runs at 200 MHz and use
Vref = 2 V. The power consumption of a comparator is given by Pcomp =
0.3+10/∆[mW ] where ∆ is the resolution required at the input of the comparator.
The power of the residue generator that obtains an amplification by 2NMSB is
2+1.2 · 2NMSB [mW] .
9. Repeat the Example 6 for a 5+5 bit converter. The required maximum resolution
loss is 0.5-bit and the SFDR must be better than70dB.
Problems
10. Use the simulation file of the Example 6 for a 5+5-bit converter. The maximum
loss in resolution is 0.5 bits and the SFDR must be better than 70 dB.
11. Describe with a behavioral language the non-linear response of a 3-bit folder and
determine the output spectrum with a full scale input sine wave. Compare the
results with the input-output characteristics of a 3-bit residue generator.
12. Assume that the real folding response of Fig. 4.19 (with 4-bit) is approximated by
parabolas joining together the 10% terminations of the linear segments with
continuous derivative. Unfold the response and use the result to estimate the
output spectrum with a half-scale sine wave.
13. The input-output transfer function of a preamplifier is modeled by
Vout=2/πatan(Vin/0.1). Determine the minimum number of preamplifiers that
obtain, with interpolation, a 6-bit flash.
14. The folding response of a 4-bit folder is linear in the 20% to 80% fraction of each
folding segment. The joining parts are part of sine waves. Determine the 1/8, 1/4,
and 1/2 interpolation curves and estimate possible errors in the zero crossings.
15. Estimate the INL improvement obtained by the interpolation network used in
Example 7 by averaging the results of 100 simulations. Use interpolating
resistances equal to 2 and 1/2 Rout.
24
Problems
16. Repeat the Example 9 studying separately effect of time jitter, random noise in the
comparator, and random and systematic errors of the DAC.
17. Determine the input-output characteristics of a residue generator that uses a 6
comparator flash with thresholds uniformly distributed on the dynamic range.
Assume that the residue is converted by a 5-bit flash and the system uses digital
correction. What is the obtained number of bits?
18. Repeat the Example 4.10 but use a gain error in the residue generator. Assume
that the gain of the three stages are 2.1, 1.96, 2.07 respectively. Use a linear
ramp at the input and determine the analog equivalent of the output. Plot the error
as a function of the input amplitude.
19. Extend the number of stages of the pipeline of Example 4.10 to 6 and convert the
residue of the last stage with a 4-bit flash. Use a gain equal to (2+2/27) in the last
pipeline stage and plot the input-output characteristics. Try different gain errors
and explain the results.
Problems
20. Use the stage model of Example 4.11 for a 10-bit pipeline made by k stages
followed by a (10-k)-bit flash. The pipeline runs at 100MHz. An empiric equation
for estimating the power consumption of the residue generator is P = (SR+fT /β)/10
mW while the power consumption of a comparator is 2 mW. Scale the
performance requirements along the pipeline so that the SFDR is better than 70
dB. Determine the value of k that minimizes the power consumption.
21. Determine the result of 8 bit SAR ADC if Vref=1V, Vin=0.353V and during 4th bit
determination the output mad a wrong decision because of a spike. All other steps
are correct.
22. 4 bit algorithmic converter with Veref=1V converts Vin=0.21 V. The error is in
multiplication by 2 capacitor ( 1,95 instead of 2 ). Determine the result.
25

A5 Microelectronic Systems 5 Nyquist AD

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A5 Microelectronic Systems 5 Nyquist AD

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Microelectronic SYSTEMS

Part 5: Nyquist rate A/D converters

2018/2019 Microelectronic systems 2

Important basic characteristics: x(t) Antialiasing

2018/2019 Microelectronic systems 3

Introduction - Max. Frequency for high speed

Usable speed of the technology:

f T   f Tech   ;   2  6 For OTA or OPAMP  v  t   Au  t 

N bit ADC needs accuracy better than 2  N 1 ;  tsett     N  1 ln  2 

2018/2019 Microelectronic systems 4

Example 1: Calculate max. Band of input signal!

Introduction – Timing accuracy

Sampling jitter produce error:

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Metastabiliy occurs when output of a comparator is undefined at the end of sampling

VFS  V0 , N  8,  L  2 1010 ; PE  PE ,max for Vin 

Na ADC Identifies quantization interval that contains input signal.

2018/2019 Microelectronic systems 8

Layout strategies for resistor string:

Expected matching: 0.05% to 0.1% with careful layout

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AVth I  W L    Cox   V gs VTH  L

Voff , MOS  VTH2   dim

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Flash AD converter – 4: example

Estimate the offset of a CMOS comparator:

2018/2019 Microelectronic systems 12

Vd ,in   AZ   V2   AZ   V1   AZ   Vos   AZ   Vos   AZ  

2018/2019 Microelectronic systems 13

Flash AD converter – 5: auto zero: Home work

N=8, Ru=25Ω, VFS=1V, Cpar=6.25fF

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Sub ranging A/D converter

Vco for Vco  i  1  Vin  Vco  i  ;

For M=N=4 we need:

The errors of the ADC are easy to correct

The errors of the DAC are hard to correct

Nonlinearity spread the spectrum over entire band.

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Sub ranging A/D converter – as a nonlinear process

Residue of the two-step converter can be described as a non-linear transformation.

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Folding bends the input in

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Folding and interpolation – double folding

Ideal and real folding

Double folding to avoid

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Folding architectures: Voltage based

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Interpolation in flash converters

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Possible use of multiple interpolators in the fine flash converter

Response of 2 folded responses.

Internal impedance of the

Interpolation circuit averages the

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Interpolation – improved linearity

2018/2019 Microelectronic systems 26

Increase the conv. Rate by N

Very demanding S&H because

Alternative is to use N S&H