Module 1

8086 Architecture & Pin Configuration

 Minimum and Maximum modes of
8086.
 Read and Write bus cycle of 8086.
 BASIC BUS OPERATION
• T-State: One complete cycle is called as T-state.

• Duty cycle is the ratio between ON and OFF time of a clock

signal. So 33% means that the clk pulse is on 1/3 of the total
cycle.

• For a 5 MHz clock, one T-state = 200 ns

2
 BASIC BUS OPERATION
• Machine Cycle: The basic microprocessor operation such as
reading a byte from I/O port or writing a byte to memory.

• Each machine cycle equals four system-clocking periods (T1-

T4)

• For a 5 MHz clock, one bus cycle lasts 800 ns.

3
 BASIC BUS OPERATION
• Instruction Cycle: The time a microprocessor needs to fetch
and execute on entire instruction.

• Microprocessor reads or writes data between itself and memory

or I/O at a maximum rate of 1.25 (1/800 ns) million times a
second.

4
 Timing Diagram Signals (Minimum Mode)
Direction 8085 8086 (Minimum Mode)
I/P CLK CLK
A16/S3 TO A19/S6 &
O/P -
BHE’/S7
O/P A8 TO A15 -
I/P OR O/P AD0 TO AD7 AD0 TO AD15
O/P ALE ALE
O/P IO/M’ M/IO’
O/P RD’ / WR’ RD’ / WR’
O/P - DT/R’
O/P - DEN’
I/P READY READY (from 8284)
5
Memory Read Cycle of the 8086 (Minimum Mode)
 Memory Read Cycle of the 8086 (Minimum Mode)
During T 1 : The address is placed on the Address/Data bus.
 Control signals M/IO’ , ALE and DT/R’ specify memory or I/O, latch the address onto
the address bus and set the direction of data transfer on data bus.

During T 2 : 8086 issues the RD’ or WR’, DEN’ signals.

 DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.

During T 3 : This cycle is provided to allow memory to access data.

 READY is sampled at the end of T 2 .
1. If low, T 3 becomes a wait state.
2. Otherwise, the data bus is sampled at the end of T 3 .

During T 4 : All bus signals are deactivated, in preparation for next bus
cycle.
 Data is sampled for reads, writes occur for writes.
7
Memory Write Cycle of the 8086 (Minimum Mode)
 Timing Diagram Signals
Direction 8086 (Minimum Mode) 8086 (Maximum Mode)
I/P CLK CLK
A16/S3 TO A19/S6 & A16/S3 TO A19/S6 &
O/P
BHE’/S7 BHE’/S7
I/P OR O/P AD0 TO AD15 AD0 TO AD15
O/P ALE ALE (from 8288)
O/P M/IO’ MRDC’ / IORC’ / MWRC’ /
O/P RD’ / WR’ IOWC’ (from 8288)

O/P - S2’, S1’, S0’

I/P READY (From 8284) READY (From 8284)
O/P DT/R’ DT/R’ (from 8288)
O/P DEN’ DEN (from 8288)
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Read Cycle of the 8086 (Maximum Mode)
Write Cycle of the 8086 (Maximum Mode)
 External hardware for 8086 in Minimum mode
 8284 (1): Clock generator and driver (to generate
Clock, Reset and Ready signals )
 8282 (3): Octal latch (To Separate Address &
Data Lines)
 8286 (2): Octal bus transceiver. (To increase driving
capacity of data bus)
 74LS138 (1): 3:8 decoder (To generate control signals
for Memory & I/O)
 8284 Clock Generator
The clock Generator 8284 performs the following tasks
in addition to generating the system clock for the
8086/8088.
 Generating the Ready signal for 8086/8088
 Generating the Reset signal for 8086/8088
 Features of 8284
 Generate system clock signal for 8086, 8088 processor and
the peripherals.
 Operates on a single +5V supply.
 Available in the 18 pin package.
 Can use either a crystal or a TTL external signal as frequency
source.
 Provides the synchronization between local ready and
microprocessor ready signal.
 Capable of clock synchronization with other 8284 chips.
 8284 Block Diagram
TANK
F/C CSYNC

X1 OSC
X2 CLOCK PCLK
EF LOGIC CLK
RDY1I
AEN1
READY READY
RDY2 LOGIC
AEN 2

RES RESET RESET

LOGIC
Clock Logic
 Pin functions of 8284A:
X1 and X2 The Crystal Oscillator pins connect to an
external crystal used as the timing source for the
clock generator and all its functions.

EFI The External Frequency input is used when the

F/C’ is pulled high. EFI supplies the timing
whenever the F/C’ pin is high.

F/C’ The Frequency/Crystal select input results the

clocking source for the 8284A. If this pin is held
high, an external clock is provided to the EFI
input pin, and if it is held low, the crystal
oscillator provides the timing signal. Continued
…
 Pin functions of 8284A:
CSYNC The clock synchronization input pin is used
whenever the EFI input provides synchronization in
systems with multiple processors (synchronize CPU
Clock with an external event). When the crystal
oscillator is used, this pin must be grounded.

OSC The Oscillator output is a TTL level signal that is at

the same frequency as the crystal or EFI input. (The
OSC output provides and EFI input to other 8284A
clock generators in some multiple processor
systems).
Frequency at this pin is equal to frequency of the
crystal (i.e. 3 times desired clock freq.)
Continued
…
 Pin functions of 8284A:
CLK The clock output pin provides CLK input signal
to the 8086/8088 microprocessors (and other
components in the system). The CLK pin has an
output signal that is one-third of the crystal or
EFI input frequency and has a 33 percent duty
cycle, which is required by the 8086/8088.

PCLK The Peripheral Clock signal is one-sixth the

crystal or EFI input frequency and has a 50
percent duty cycle. The PCLK output provides a
clock signal to the peripheral equipment in the
system.
Continued
…
 Pin functions of 8284A:
RES’ Reset Input, used for generating Reset signal for
the processor. It is an active low pin.
External RC integrator is connected to this pin
in order to obtain the power ON reset signal of
proper duration.

READY Output signal generated by 8284. It is connected

directly to READY input of the 8086.
This output signal is synchronized with two
ready signals (RDY1 & RDY2) of 8284.

Continued
…
 Pin functions of 8284A:
RDY1 & Input signal available from the external devices.
RDY2 Whenever an external device wants to introduce
a “wait” T-state for proper data transfer, it will
activate (force to 1) the RDY1 & RDY2 input.

AEN1’ & Active low input signals. They are enable

AEN2’ inputs for RDY1 & RDY2 inputs respectively.
A low AEN1’ signal validated RDY1 input and a
low AEN2’ signal validates the RDY2 input.

Continued
…
Interfacing 8284 to 8086
8282 : An Octal Latch
 Interfacing Latch to 8085
HIGHER ADDRESS BUS
A15-
20
A8

74373 LOWER ADDRESS BUS

8 (latch)
AD7- 01
0 AD0 34
8
G OE
5
ALE

DATA BUS
 Interfacing Latch to 8085
HIGHER ADDRESS BUS
A15-
20
A8

74373 LOWER ADDRESS BUS

8 (latch)
AD7- 01
0 AD0
8
G OE
5
ALE

34

DATA BUS
8286 : Octal Bus Transceiver
Interfacing 8286 to 8086
74LS138 : 3:8 decoder
 Minimum Mode System
A minimum mode of 8086 configuration depicts a stand alone
system of computer where no other processor is connected.
This is similar to 8085 block diagram with the following
difference.

The Data transceiver block which helps the signals traveling a

longer distance to get boosted up.

Two control signals data transmit/ receive are connected to

the direction input of transceiver (Transmitter/Receiver) and
DEN* signal works as enable for this block.
 +5V
+5V 3
F/C’ 2
Vcc GND GND 1 BHE’
BHE’/S7 8282
A16/S3 –
X1 X2 Octal A0 – A19
A19/S6
R CLK CLK AD0 – Latch
AD15 (3)
S/W RESET RESET
RES’ ALE STB
READY READY OE’
C
8284
8 1
2
RDY1 RDY2 0 8286
Transceivers D0 – D15
8 (2)
Wait State 6 DEN’ OE’
Generator
DT/R’ T
+5V
MN/MX’ +5V

NMI G MEMR’
M/IO’ C Y5’
INTR MEMW’
3:8 Y6’
RD’ B
INTA’ IOR’
Typical Minimum WR’ A
Decoder Y1’
IOW’
HOLD G2A’ G2B’Y2’
mode configuration HLDA
 Minimum Mode Vs Maximum Mode
 Minimum Mode Operation:
 Least expensive way to operate the 8086/8088
microprocessors
 All control signals for the memory and i/o are generated by
the microprocessor only.
 Control signals are identical to those of the Intel 8085A.

 Maximum Mode Operation:

 Expensive way to operate the 8086/8088 microprocessors.
 Control signals must be externally generated.
 Requires the addition of an external bus controller i.e. 8288
bus controller.
 Used only when the system contains external coprocessors
such as the 8087 arithmetic coprocessor.
 External hardware for 8086 in Maximum Mode
 8284 (1): Clock generator and driver (to generate
Clock, Reset and Ready signals )
 8282 (3): Octal latch (To Separate Address &
Data Lines)
 8286 (2): Octal bus transceiver. (To increase driving
capacity of data bus)
 8288 (1): Bus controller (Used in Maximum mode to
generate control signals)
 8288 Bus Controller
 It is used in maximum mode configuration of 8086.

 The 8288 bus controller accepts the CLK along with

S0*, S1* and S2* outputs of 8086 and generates the
command, control and timing signals at its output.
8288 Bus Controller
 Maximum Mode System
 In the maximum mode of operation of 8086, wherein either a
numeric coprocessor of the type 8087 or another processor is
interfaced with 8086.

 The Memory, Address Bus, Data Buses are shared resources

between the two processors.

 The control signals for Maximum mode of operation are

generated by the Bus Controller chip 8288.

 The three status outputs S0*, S1*, S2* from the processor are
input to 8288.
 Maximum Mode System
 The outputs of the bus controller are the Control Signals,
namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*,
ALE etc.

 These control signals perform the same task as the minimum

mode operation.

 However the DEN is an active HIGH signal which has to be

converted to active LOW by means of an inverter.
 +5V
+5V 3
F/C’ 2
Vcc GND GND 1 BHE’
BHE’/S7 8282
A16/S3 –
X1 X2 Octal A0 – A19
A19/S6
R CLK CLK AD0 – Latch
AD15 (3)
S/W RESET RESET
RES’ STB
READY READY OE’
C
8284
8 1
2
RDY1 RDY2 0 8286
Transceivers D0 – D15
8 (2)
Wait State 6 OE’
Generator
T

MN/MX’
0
DT/R’ CLK MRDC’
NMI MWTC’
DEN
INTR ALE 8288 AMWC’
S0’ S0’ Bus IORC’
Typical Maximum S1’ S1’
controller
(1)
IOWC’
AIOWC’
S2’ S2’
mode configuration INTA’