Sei sulla pagina 1di 10

This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

Voltage-Source Parallel Resonant Class E Inverter


Akinobu Shigeno, Student Member, IEEE, and Hirotaka Koizumi, Member, IEEE
.
Abstract―This paper proposes a voltage-source parallel iLs Ls
resonant Class E inverter. The proposed circuit has a + vLs - io
shunt capacitor including parasitic capacitance of a RL
switching device and achieves zero-voltage switching Vin Cs iCs L r Ca Cb +
vo
(ZVS) and zero-voltage derivative switching (ZVDS) at - vds + -
Cr
turning-on like a classical Class E inverter. Therefore, iS
high power conversion efficiency is achieved under high
operating frequency. Unlike the other Class E inverters, S
the proposed circuit has no choke inductor or dc blocking Fig. 1. Voltage-source parallel resonant Class E inverter.
capacitor. Moreover, it has a parallel resonant tank unlike ON OFF
the classical Class E inverter. Thus, a circuit protection is Vin
not required in WPT system. A circuit analysis, circuit
ωt ON OFF
simulations, and circuit experiments were carried out. The vds
0 vo
Vsm Vo
experimental circuit performed the desired operation and -
the power conversion efficiency was 93.2 % with the 0 ωt
output power 4.76 W at the operating frequency 1 MHz. 0 ωt -Vo
vLs
iS
Index Terms―Class E tuned power amplifier, inverter, Ism
ωt
resonant power conversion. 0
0 ωt
iCs iLs
I. INTRODUCTION Ism

M iniaturization, high efficiency, low cost, and low noise


are required for wireless communication systems and
devices. In order to downsize such devices, increasing
0
2πD 2π
ωt 0
2πD 2π
ωt

switching frequency of inverters is effective [1]. However, Fig. 2. Theoretical waveforms.


switching loss becomes a serious problem in high frequency
operation. Class E inverters with parallel resonant circuit are introduced
Class E tuned power amplifiers [2]-[6], which can be used as in [3], [7]-[10], [22], [23], where Class E-1 inverter has an
inverters, achieve high efficiency DC/AC power conversion inductor in series with the switch [3], [9]-[10]. The series
in high frequency, and they are applied to DC-DC converters, inductor reduces the influence of the parasitic inductance.
transmitters, wireless power transfer (WPT), etc. Class E This inverter achieves zero-current switching (ZCS) and zero-
inverters, whose theoretical power conversion efficiency is current derivative switching (ZCDS) at turning-off, which
100%, satisfy Class E switching condition, i.e. zero-voltage lead to low switching loss. Its peak drain-source voltage is
switching (ZVS) and zero-voltage derivative switching lower than the classical Class E inverter. However, the Class
(ZVDS) at turning-on. This condition realizes low switching E-1 inverter, which has no shunt capacitor, is more affected by
loss in high operating frequency. Classical Class E inverter [2] the parasitic capacitance than the classical Class E inverter. In
has a shunt capacitor, which includes the drain-source [10], [22], [23], Class E inverter with shunt capacitor and
capacitance of the switching device in design. In high shunt filter is introduced. This inverter has a shunt capacitor
frequency operation, charge and discharge of the parasitic and achieves Class E switching condition. However, it has a
capacitance becomes a problem [5]. The shunt capacitor choke inductor and a dc blocking capacitor. The choke
reduces the influence of the parasitic capacitance. Various inductor and the dc blocking capacitor prevent downsizing
topologies, Class E-1 [7]-[10], Class DE [11], [12], Class EF2 and fast transient response.
[13], [14], Class  [15], etc. have been derived from the This paper proposes voltage-source parallel resonant Class E
classical Class E topology. inverter. This circuit is based on the dual topology of the Class
Recently, applying these circuits to WPT has been E inverter with shunt capacitor and shut filter [10], [22].
researched [16]-[18]. In WPT, robustness against However, no choke inductor or the dc blocking capacitor are
misalignment is required. The parallel resonant tank of the required by connecting the switch and the shunt capacitor in
inverter is more robust than series one [19]. Also, in the case series with the resonant tank. This circuit has a shunt capacitor
of the series resonant tank, misalignment leads to small and achieves Class E switching condition like the classical
impedance, which may cause an over loaded situation. Thus, Class E inverter. Therefore, high power conversion efficiency
a circuit protection is needed [20], [21]. is achieved under high operating frequency. In addition, it has
the parallel resonant tank unlike the classical Class E inverter,
which is suitable for WPT.
In section II, a circuit topology and theoretical waveforms of
The authors are with Tokyo University of Science, 6-3-1 Nijuku, the proposed circuit are shown. In section III, circuit
Katsushika-ku, Tokyo 125-8585 Japan (e-mail: as1995@ieee.org; simulation and experiment results are shown and compared.
littlespring@ieee.org
In section IV, conclusion is presented.

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

II. VOLTAGE-SOURCE PARALLEL RESONANT CLASS E vds (t ) = 0 , (10)


INVERTER iCs (t ) = 0 . (11)
The voltage-source parallel resonant Class E inverter is
shown in Fig. 1. It consists of a voltage source Vin, a switch S, From (5) and (10), the inductor voltage vLs is
a series inductor Ls, a shunt capacitor Cs, a parallel resonant vLs (t ) = Vin - vo (t ) . (12)
circuit Lr-Cr, and a load resistor RL. The capacitance Cr is From (6) and (11), the switch current iS is,
regarded as two capacitances Ca and Cb. The switch S is driven iS (t ) = iLs (t ) . (13)
at the operating frequency f. The theoretical waveforms are From (12), the inductor current iLs is,
shown in Fig. 2, where Vin is a dc input voltage, vds is a drain- 1 t
iLs (t ) = V - V sin (t +  )  d t
 Ls 0  in o
source voltage of the switch S, Vsm is a peak voltage of the
drain-source voltage vds, iS is a switch current flowing through 1 (14)
the switch S, Ism is a peak current of the switch current iS, iCs = V t + Vo cos (t +  ) - Vo cos   .
 Ls  in
is a capacitor current flowing through the shunt capacitor Cs,
vo is an ac output voltage, Vo is an amplitude of the output In state 2 [2πD ≤ ωt < 2π], the switch S is off. The switch
voltage vo,  is an initial phase of the output voltage vo, vLs is current iS satisfies
an inductor voltage of the series inductor Ls, and iLs is an iS ( t ) = 0 . (15)
inductor current flowing through the series inductor Ls. From (6) and (15),
In order to simplify gate driving, the source pin is grounded. iCs (t ) = iLs (t ) . (16)
It is also possible to ground the load and the voltage source by From (5) and (16),
placing the switch with the shunt capacitor next to the inductor
d
Ls.  Cs vds (t )
d t
1 t
Vin - Vo sin (t +  ) - vds (t )  d t
 Ls 2πD 
A. Theoretical Equations = (17)
The waveform equations are derived based on the following
assumptions. + iLs ( 2πD ) .
1) The switch S instantly turns on and off and has no on- Laplace transform of (17) is
resistance. The drain-source capacitance is constant and 1  Vin cos  + s sin  
Cs sVds ( s ) = - Vo - Vds ( s ) 
included in the shunt capacitor Cs. s Ls  s s2 + 1 
2) The loaded quality factor Q of the parallel resonant iLs ( 2πD )
(18)
circuit composed of the resonant capacitor Ca and the + .
s
resonant inductor Lr is sufficiently high. That is, the
From (18),
output voltage vo is a sinusoidal wave.
3) The switch S achieves ZVS and ZVDS at turning on. Vds ( s ) 1 cos  + s sin  Vds ( s ) 
s2 = a2   b - - 
4) All passive elements are ideal. Vo  s s2 + 1 Vo 
(19)
The loaded quality factor Q of the parallel resonant circuit is iLs ( 2πD )
+ ,
expressed as CsVo
Q = Cr RL . (1) where
The capacitance Cr can be divided into two capacitances Ca 1 ,
a= (20)
and Cb.  Cs Ls
Cr = Ca + Cb (2) Vin
The resonant angular frequency of the parallel resonant circuit b= . (21)
Vo
Lr-Ca is equal to the operating angular frequency , where 
= 2f. The theoretical waveform equations are considered in two
1
cases of a = 1 and a ≠ 1.
= (3) At a = 1, (19) is
Lr Ca
Vds ( s )
From the assumption 2), the output voltage vo is expressed as Vo
vo (t ) = Vo sin (t +  ) . (4) 1 cos  + s sin  1 iLs ( 2πD ) (22)
= b - +  .
From Kirchhoff’s voltage law and current law, (
s s +1
2
) (s 2
+1 )
2
s 2 + 1 CsVo
Vin = vLs (t ) + vo (t ) + vds (t ) , (5)
Inverse Laplace transform of (22) is
iLs (t ) = iCs (t ) + iS (t ) . (6) vds (t ) 1
From the assumption 3), so-called Class E switching = b (1 - cos t ) - cos  sin t
Vo 2
conditions are satisfied. 1 iLs ( 2πD )
vds ( 0 ) = vds ( 2π ) = 0 (7) + t cos (t +  ) + sin t (23)
2 CsVo
1
d
vds (t ) =
d
v (t ) =0 (8) = c1 sin t + c2 cos t + b + t cos (t +  ) .
d t t = 0 d t ds  t = 2π
2
where
iS ( 0 ) = iS ( 2π ) = 0 . (9) iLs ( 2πD ) 1
The circuit operation for one period is divided into two states c1 = - cos  , (24)
CsVo 2
depending on the on and off states of the switch S.
In state 1 [0 ≤ ωt < 2πD], the switch S is on. The drain-source c2 = -b . (25)
voltage vds and the capacitor current iCs are From (16) and (23),

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

iLs (t ) iCs (t ) d vds ( t )  RL


0  t  2πD 
= = Cs RL   L bt + cos (t +  ) - cos  
Io Io d t Vo iLs (t ) 
 s
= Cs RL  c1 cos t - c2 sin t (26) Io
= Cs RL c1 cos t - c2 sin t + 1 cos (t +  )
 (49)
  2
 2πD  t  2π 
1 1 
+ cos (t +  ) - t sin (t +  )  . 
 -
1
 t sin (t +  )
2 2   2 
At ωt = 2πD, from (10) and (23), vo (t ) = Vo sin (t +  ) (50)
c1 sin 2πD + c2 cos 2πD + d1 = 0 , (27) When a ≠ 1, (19) is
where Vds ( s )
d1 = b + πD cos ( 2πD +  ) . (28) Vo
Applying boundary condition to (14) and (26), a2 a2
=  b - ( cos  + s sin  )
c1 cos 2πD - c2 sin 2πD + d2 = 0 , (29) (
s s2 + a2 ) (
s2 + 1 s2 + a2 )( ) (51)
where a iLs ( 2πD )
1 +  .
d 2 = πD sin ( 2πD +  ) + cos ( 2πD +  ) s + a aCsVo
22
2 (30)
+ 2πbD - cos  . Inverse Laplace transform of (51) is
From (27) and (29), vds (t ) a2
c1 = -d1 sin 2πD - d2 cos 2πD , (31) = b (1 - cos at ) - 2 sin (t +  )
Vo a -1
c2 = -d1 cos 2πD + d2 sin 2πD . (32) a a2
+ 2 cos  sin at + 2 sin  cos at
Appling Class E switching condition (7) to (23), a -1 a -1
vds ( 2π ) iLs ( 2πD ) (52)
= c2 + b + π cos  = 0 + sin at
Vo
(33) aCsVo
= g1 sin at + g 2 cos at + b
which can be rewritten as a2
e1b = e2 sin  + e3 cos  (34) - 2 sin (t +  ) ,
a -1
where where
e1 = 1 - 2πD sin 2πD - cos 2πD , (35) iLs ( 2πD ) a
g1 = + cos  , (53)
1 (36) aCsVo a2 - 1
e2 = - sin 2 2πD ,
2 a2
1 (37) g 2 = -b + sin  . (54)
e3 = πD + sin 4πD - sin 2πD - π . a -12

4 From (16) and (52),


From (8) and (26), iLs (t ) iCs (t ) d vds (t )
= = Cs RL
d vds (t ) 1 d t Vo
= c1 + cos  - π sin  = 0 (38) Io Io
d t Vo t = 2π
2 = Cs RL  ag1 cos at - ag 2 sin at (55)
which can be rewritten as a2 
- 2 cos (t +  )  .
e4b = e5 sin  + e6 cos  (39) a -1 
where At ωt = 2πD, from (10) and (52),
e4 = sin 2πD - 2πD cos 2πD , (40) g1 sin 2πaD + g2 cos 2πaD + h1 = 0 , (56)
1 (41) where
e5 = πD - sin 4πD - π , a2
4 h1 = b - 2 sin ( 2πD +  ) . (57)
1 1 (42) a -1
e6 = + cos 2 2πD - cos 2πD . Applying boundary condition to (14) and (55),
2 2
From (34) and (39), g1 cos 2πaD - g2 sin 2πaD + h2 = 0 , (58)
e e -e e where
tan  = 3 4 1 6 , (43)
e1e5 - e2 e4 a3
h2 = - 2 cos ( 2πD +  ) - 2πabD + a cos  . (59)
e e a -1
b = 2 sin  + 3 cos  . (44)
e1 e1 From (56) and (58),
g1 = -h1 sin 2πaD - h2 cos 2πaD , (60)
The waveform equations at a = 1 are summarized as follows,
0
vds (t )  0  t  2πD  g2 = -h1 cos 2πaD + h2 sin 2πaD . (61)
= (45)
Vo
1
c1 sin t + c2 cos t + b + t cos (t +  )
 2
 2πD  t  2π  Appling Class E switching condition (7) to (52),
 RL vds ( 2π ) a2
iS (t )  bt + cos (t +  ) - cos   0  t  2πD  = g1 sin 2πa + g 2 cos 2πa + b - sin 
=   Ls (46) Vo a -1
2 (62)
Io 
0  2πD  t  2π  =0
0 0  t  2πD  which can be rewritten as
iCs (t ) 

 1 j1b = j2 sin  + j3 cos  (63)

= Cs RL c1 cos t - c2 sin t + 2 cos (t +  ) (47)
  2πD  t  2π 
Io  1  where
 - t sin (t +  ) 

 2  j1 = 1 + 2πaD sin 2πa (1 - D ) - cos 2πa (1 - D ) , (64)
b - sin (t +  ) 0  t  2πD 
vLs (t ) 
= b - sin (t +  ) + c1 sin t (48)
Vo  1
+ c2 cos t + b + t cos (t +  )
 2πD  t  2π

 2

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

a3 Vo 1
j2 = sin 2πa (1 - D ) sin 2πD M VR = =
a - 12
2
(65) 2Vin 2b
a a2 (80)
cos 2πa (1 - D ) cos 2πD + 2
j1
- 2 , = .
a -1 a -1 2 ( j2 sin  + j3 cos  )
a3 From (79), the output current io and the current iCb flowing
j3 = - 2 sin 2πa (1 - D ) cos 2πD
a -21 through the capacitance Cb are
a (66)
- 2 cos 2πa (1 - D ) sin 2πD V
io (t ) = o sin (t +  )
a -1
+ a sin 2πa (1 - D ) . (81)
RL
= I o sin (t +  ) ,
From (8) and (55),
iCb (t ) = CbVo cos (t +  )
d vds (t ) = I Cb cos (t +  ) , (82)
d t Vo  t = 2π (67) where Io and ICb are the amplitudes of the output current io and
a2 the current iCb. The current through the parallel resonant
= ag1 cos 2πa - ag 2 sin 2πa - 2 cos  = 0
a -1 circuit is equal to the inductor current iLs.
which can be rewritten as 1 2π
j4b = j5 sin  + j6 cos  I o =  iLs (t )sin(t +  )dt
(68) π 0 (83)
where = CsVo k ,
j4 = sin 2πa (1 - D ) + 2πaD cos 2πa (1 - D ) , 1 2π
(69) I Cb =  iLs (t ) cos(t +  )dt
3 π 0 (84)
j5 =
a
cos 2πa (1 - D ) sin 2πD = CsVo l ,
a2 -1 2 (70) where
a
+ 2 sin 2πa (1 - D ) cos 2πD,
a -1 k=
1 2
π2
(a b sin ( 2πD +  ) - 2πD cos ( 2πD +  ) 
a3 a
j6 = - 2 cos 2πa (1 - D ) cos 2πD - cos 2 ( 2πD +  ) + a 2 cos  cos ( 2πD +  )
a - 12 4
a a2
+ 2 sin 2πa (1 - D ) sin 2πD (71) -a 2 b sin  + cos 2 - a 2 cos 2 
a -1 4
a2 a2
cos 2 ( 2πD +  )
a
+ a cos 2πa (1 - D ) + 2 . + cos 2 -
a -1 4(a 2 - 1) 4(a 2 - 1)
From (63) and (68), g  cos[2π(1 - a) +  ] cos[2π(1 + a) +  ]  (85)
+ 1 - 
j j -j j 2  a -1 a +1 
tan  = 3 4 1 6 , (72) g 2  sin[2π(1 - a) +  ] sin[2π(1 + a) +  ] 
j1 j5 - j2 j4 +  + 
2  a -1 a +1 
j2 j g  cos[2πD(1 - a ) +  ] cos[2πD(1 + a ) +  ] 
b= sin  + 3 cos  . (73) - 1 -
j1 j1 
2  a -1 a +1 
The waveform equations at a ≠ 1 are summarized as follows, g 2  sin[2πD(1 - a ) +  ] sin[2πD(1 + a ) +  ]  
0 0  t  2πD  -  +  ,
vds (t ) 

2  a -1 a +1 
=  g1 sin at + g 2 cos at + b
(74)
Vo  - 2
a2
sin (t +  )
 2πD  t  2π 

iS (t ) 
 RL

 a -1

bt + cos (t +  ) - cos   0  t  2πD 


l=
1 2
π
(
a b cos ( 2πD +  ) + 2πD sin ( 2πD +  ) 
=   Ls
2
a
Io 0  2πD  t  2π 
(75) + sin 2 ( 2πD +  ) + a 2 πD
 4
0  t  2πD a2
0
 -a 2 cos  sin ( 2πD +  ) - a 2 b cos  + sin 2
iCs (t ) Cs RL  ag1 cos at - ag 2 sin at 4
= (76) a2  1 
Io  a2
- 2 cos (t +  ) 
  2πD  t  2π - 
1
sin 2 + ( 2π +  ) 

 a - 1  a -1 
2
4 2 
a2  1 1 
b - sin (t +  )

0  t  2πD  + 2  sin 2 ( 2πD +  ) + ( 2πD +  ) 
vLs (t ) b - sin (t +  )
 a -1  4 2  (86)
=  -  g1 sin at + g 2 cos at  2πD  t  2π  (77) g1  sin[2π(1 - a) +  ] sin[2π(1 + a) +  ] 
Vo  a2  +  + 
 +b- 2 sin (t +  )  2  1- a 1+ a 

 a -1 
g 2  cos[2π(1 + a) +  ] cos[2π(1 - a) +  ] 
 RL +  - 
  L bt + cos (t +  ) - cos   0  t  2πD  2  1+ a 1- a 
iLs (t )  g1  sin[2πD(1 - a) +  ] sin[2πD (1 + a ) +  ] 
s

= Cs RL  ag1 cos at - ag 2 sin at (78) -  + 


Io  a2   2πD  t  2π 2  1- a 1+ a 
 - 2 cos (t +  ) 
 a -1  g 2  cos[2πD(1 + a ) +  ] cos[2πD(1 - a ) +  ]  
-  -  .
vo (t ) = Vo sin (t +  ) (79) 2  1+ a 1- a 
From (81) and (83), the shunt capacitance Cs is
B. Design Equations 1
Cs = . (87)
From (21) and (73), the voltage transfer function MVR is  RL k
From (20) and (87), the inductance Ls is

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

RL k 5.50
. Ls = (88) a=0.500
a 2

Normalized peak voltage Vsm/Vin


5.00 a=0.750
From (1), the resonant capacitance Cr is a=1.00
a=1.25
Q 4.50 a=1.50
Cr = . (89)
 RL 4.00
a=1.75
a=2.00
From (82), (84), and (87), the capacitance Cb is
l 3.50
Cb = . (90)
 RL k 3.00
From (2), the capacitance Ca is
Ca = Cr - Cb . (91) 2.50
0.35 0.40 0.45 0.50 0.55 0.60 0.65
From (3), the resonant inductance Lr is On duty ratio D
1 Fig. 4. Normalized peak voltage Vsm/Vin as a function of on duty ratio
Lr = . (92)
 2 Ca D.
16.00

C. Peak Values and Power Output Capability 14.00 a=0.500

Normalized peak current Ism/Iin


a=0.750
Fig. 3 shows normalized resistance ωCsRL as a function of 12.00
a=1.00
the on duty ratio D. From (74) and (75), a drain-source voltage a=1.25
10.00
stress and a switch current stress are determined by the on duty a=1.50
ratio D and the parameter a. Fig. 4 shows the normalized peak 8.00 a=1.75
voltage Vsm/Vin as a function of the on duty ratio D. Fig. 5 6.00 a=2.00
shows the normalized peak current Ism/Iin as a function of the
on duty ratio D. Fig. 6 shows the power output capability cp 4.00
as a function of the on duty ratio D. The power output 2.00
capability cp is defined as 0.35 0.40 0.45 0.50 0.55 0.60 0.65
V I On duty ratio D
c p = in in . (93)
Vsm I sm Fig. 5. Normalized peak current Ism/Iin as a function of on duty ratio D.
0.12
Fig. 7 shows the power output capability cp as a function of
the on duty ratio D around D = 0.55. From Fig. 7, the power
Power output capability cp

0.10
output capability cp reaches a maximum about D =0.55 and a
= 1.75.
Table I shows comparison of the proposed circuit with the 0.08

conventional Class E inverters for the normalized resistance a=0.500


a=0.750
ωCsRL, the normalized peak voltage Vsm/Vin, the normalized 0.06
a=1.00
peak current Ism/Iin, and the power output capability cp in case a=1.25
of the highest power output capability cp condition. The 0.04 a=1.50
a=1.75
normalized peak voltage Vsm/Vin of the proposed circuit is the a=2.00
largest, however the power output capability cp is the second 0.02
0.35 0.40 0.45 0.50 0.55 0.60 0.65
largest. Since the normalized resistance ωCsRL of the On duty ratio D
proposed circuit is the largest, the maximum frequency in
Fig. 6. Power output capability cp as a function of on duty ratio D.
design is higher than the others.
0.110
Power output capability cp

3.00
a=0.500 0.105
a=0.750
2.50 a=1.00
a=1.25
2.00 a=1.50 0.100
a=1.75
ωCsRL

a=2.00 a=1.60 a=1.65


1.50
0.095 a=1.70 a=1.75
1.00 a=1.80 a=1.85
a=1.90
0.50 0.090
0.50 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.60
On duty ratio D
0.00
0.35 0.40 0.45 0.50 0.55 0.60 0.65 Fig. 7. Power output capability cp as a function of on duty ratio D
On duty ratio D around D = 0.55.
Fig. 3. Normalized resistance ωCsRL as a function of on duty ratio D.

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

TABLE I COMPARISON OF PROPOSED CIRCUIT AND CONVENTIONAL CLASS E INVERTERS


Normalized Normalized peak Normalized peak Power output
On duty ratio D
resistance ωCsRL voltage Vsm/Vin current Ism/Iin capability cp
Class E [4] 0.5 0.1836 3.56 2.86 0.0982
Class DE [4] 0.25 0.318 1.00 6.28 0.0796
Class EF2 [14] 0.375 0.132 2.32 3.26 0.132
Class E/F3 [4] 0.5 0.209 3.14 3.06 0.104
Class E with
0.5 0.26 (approx. 3)* (approx. 3.5)* 0.0982
shunt filter [23]
Proposed
0.55 1.26 4.07 2.26 0.108
(a = 1.75)
*Read from Fig. 2 (c) in [23]

D. Power Conversion Efficiency The conduction loss PLs is expressed as


PLs = rLs I Ls
2 , (99)
The conduction loss and the core loss of the switch S, the , rms

inductor Ls, the capacitor Cs, the resonant capacitor Cr, and the where rLs is the ESR of the inductor Ls and ILs,rms is the RMS
resonant inductor Lr are considered. The switching loss is value of the inductor Ls. From (78), the RMS inductor current
neglected. The power conversion efficiency is expressed as ILs,rms is
I Ls , rms (t )
Po
= , (94) 1 2π 2
Po + PS + PCs + PLs + PR + PLscore + PLrcore =
2π 0 iLs (t ) dt
1  2πD 2
where Po is the output power, PS, PCs, PLs, and PR are iS (t ) d t +  iCs 2 (t ) d t 

2π  0
=
2πD 
conduction losses of the switch S, the capacitor Cs, the Vo  8 3 2 3 1
inductor Ls, and the parallel resonant circuit Lr-Cr, and PLscore =  π b D + 2π D + sin(4πD + 2 )
 Ls 2π   3 4
and PLrcore are core losses of the inductor Ls and the resonant + πD cos 2 + 2b cos(2πD +  ) + (4πbD - 2 cos  ) sin(2πD +  )
inductor Lr. 3 
-(4π 2 bD 2 + 2b) cos  + sin 2 
4 
The conduction loss PS is expressed as 1  1
+ 2 a 2 ( g12 + g 22 )π + a 2 ( g12 - g 22 ) sin 4πa
PS = ron I S2, rms , (95) a  4a
a4 1 1
where ron is the on resistance of the switch S and IS,rms is the + 2 (π + sin 2 ) + ag1 g 2 cos 4πa
(a - 1) 2 4 2 (100)
RMS value of the switch current iS. From (75), the RMS 2a 3 g
- 2 1 2 (a cos  sin 2πa - cos 2πa sin  )
switch current IS,rms is (a - 1)
1 2πD 2 2a 3 g
- 2 2 2 (a cos  cos 2πa + sin  sin 2πa )
I S , rms (t ) = iS (t ) d t
2π 0
(a - 1)
a
-a 2 ( g12 + g 22 )πD - ( g12 - g 22 ) sin 4πaD
Vo 8 3 2 3
= π b D + 2πD 4
 Ls 2π  3
a4  1  1
- 2 2 
πD + sin(4πD + 2 )  - ag1 g 2 cos 4πaD
(a - 1)  4  2
1
+ sin(4πD + 2 ) + πD cos 2 (96) 2a 3 g
+ 2 1 2  a cos(2πD +  ) sin 2πaD - cos 2πaD sin(2πD +  ) 
4 (a - 1)
+2b cos(2πD +  ) 1
  2
+(4πbD - 2 cos  )sin(2πD +  ) 2a 3 g
+ 2 2 2  a cos(2πD +  ) cos 2πaD + sin(2πD +  ) sin 2πaD   .
1 (a - 1)  
3 2
-(4π bD + 2b) cos  + sin 2  .
2 2
The conduction loss PR is expressed as
4  Vo2 ( RLP + RCP )
The conduction loss PCs is expressed as PR = , (101)
2 RLP RCP
PCs = rCs I Cs
2 , (97)
, rms
where RLP and RCP are the EPRs of the resonant inductor Lr
where rCs is the ESR of the capacitor Cs and ICs,rms is the RMS and the resonant capacitor Cr. The relationships between the
value of the capacitor current iCs. From (76), the RMS EPRs are
capacitor current ICs,rms is 
  ωL  
2
I Cs , rms (t ) 
RLP = rL 1 +  r   , (102)
=
1 2π 2
2πD iCs (t ) dt 
  rL  


CsVo  
  1  
1 2
= a ( g1 + g 2 )π + a ( g1 - g 2 ) 
2 2 2 2 2 2
sin 4πa
2π  4a RCP = rL 1 +   . (103)
a 4
1 1   ωC r  
+ 2 (π + sin 2 ) + ag1 g 2 cos 4πa  r C
(a - 1) 2 4 2
2a 3 g1 The core loss PLscore and PLrcore are derived based on the data
- 2 (a cos  sin 2πa - cos 2πa sin  )
(a - 1) 2 sheet [24]-[26].
2a 3 g 2
- 2 (a cos  cos 2πa + sin  sin 2πa ) (98)
(a - 1) 2
a
-a ( g1 + g 22 )πD - ( g12 - g 22 ) sin 4πaD
2 2

4
  1
4
a 1
- 2 2 
πD + sin(4πD + 2 )  - ag1 g 2 cos 4πaD
(a - 1)  4  2
2a 3 g
+ 2 1 2  a cos(2πD +  ) sin 2πaD - cos 2πaD sin(2πD +  ) 
(a - 1)
1
2
 a cos(2πD +  ) cos 2πaD + sin(2πD +  ) sin 2πaD  .
2a 3 g 2
+
(a 2 - 1) 2 

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

TABLE III. SIMULATIONS RESULTS


Case I: Q = 2 Case II: Q = 5 Case III: Q = 8
Designed Simulation Designed Simulation Designed Simulation
Vin [V] 19.5 19.5 19.5 19.5 19.5 19.5
Iin [A] 257 0.269 257 0.261 257 0.259
Pin [W] 5.00 5.23 5.00 5.08 5.00 5.05
Vo,rms [V] 15.8 16.1 15.8 15.9 15.8 15.9
Io,rms [A] 0.316 0.323 0.316 0.319 0.316 0.318
Po [W] 5.00 5.23 5.00 5.08 5.00 5.05
Vsm [V] 79.2 82.5 79.2 80.7 79.2 80.1
Ism [A] 0.581 0.605 0.581 0.581 0.581 0.577

III. SIMULATION AND CIRCUIT EXPERIMENT 30

The circuit simulations and the circuit experiments were

Vin,vo[V]
carried out. Experimental circuits were designed based on the 0

following conditions.
1) The operation frequency f = 1.00 [MHz] -30
(a)
100
2) The output power Po = 5.00 [W]
3) The load resistance R = 50 [Ω]

vds[V]
4) The parameter a = 1.75
5) The on duty ratio D = 0.55 0

6) The loaded quality factor Q = 2.00, 5.00, and 8.00


(b)
0.8

iS[A]
A. Simulation Results
To confirm the designed circuit operation under the ideal 0

condition, the proposed circuit was simulated with PSIM ver. -0.2
(c)

11.0. Table II shows parameters in the simulations. In this 1.500 1.501 1.502 1.503 1.504 1.505
Time [ms]
simulation, all the components were assumed to be ideal. Figs.
Fig. 8. Simulation waveforms at Q = 2, (a) input voltage Vin, output
8-10 show simulation waveforms of the input voltage Vin, the voltage vo, (b) drain-source voltage vds, (c) switch current iS.
output voltage vo, the drain-source voltage vds, and the switch 30
current iS. As shown in Figs. 8-10, the switch S achieved ZVS
Vin,vo[V]

and ZVDS when the switch turned on. The simulation 0


waveforms were in good agreement with the theoretical
waveforms. Table III shows the simulation results. The -30
(a)
simulation results were also in good agreement with the 100

theoretical values. The difference between the theoretical and


vds[V]

the measured values is caused by the low loaded quality factor


Q. The waveform equations are derived based on the 0
assumption that the output voltage is the sinusoidal wave in 0.8
(b)

section II.
iS[A]

TABLE II. PARAMETERS IN SIMULATIONS 0


Case I: Q = 2 Case II: Q = 5 Case III: Q = 8 -0.2
Vin [V] 19.5 19.5 19.5 (c)
1.500 1.501 1.502 1.503 1.504 1.505
Ls [μH] 10.1 10.1 10.1
Time [ms]
Cs [nF] 0.823 0.823 0.823
Lr [μH] 4.33 1.64 1.02 Fig. 9. Simulation waveforms at Q = 2, (a) input voltage Vin, output
Cr [nF] 6.37 15.9 25.5 voltage vo, (b) drain-source voltage vds, (c) switch current iS.
RL [Ω] 50.0 50.0 50.0 30
Vin,vo[V]

-30
(a)
100
vds[V]

0
(c)
0.8
iS[A]

0
-0.2
(d)
1.500 1.501 1.502 1.503 1.504 1.505
Time [ms]

Fig. 10. Simulation waveforms at Q = 2, (a) input voltage Vin, output


voltage vo, (b) drain-source voltage vds, (c) switch current iS.

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

TABLE IV. PARAMETERS IN EXPERIMENTAL CIRCUIT


Case I: Q = 2 Case II: Q = 5 Case III: Q = 8
Measured Measured Measured
Designed Designed Designed
(ESR[mΩ]) (ESR[mΩ]) (ESR[mΩ])
Ls [μH] 10.1 10.1 (324) 10.1 10.0 (267) 10.1 10.0 (313)
Cs [nF] 0.823 0.798 (199) 0.823 0.798 (209) 0.823 0.798 (180)
Lr [μH] 4.33 4.31 (172) 1.64 1.66 (143) 1.02 1.04 (60.8)
Cr [nF] 6.37 6.38 (73.6) 15.9 15.8 (89.3) 25.5 24.9 (78.7)
RL [Ω] 50.0 49.9 50.0 50.0 50.0 49.9

TABLE V. EXPERIMENTAL RESULTS


Case I: Q = 2 Case II: Q = 5 Case III: Q = 8
Calculated Measured Calculated Measured Calculated Measured
Vin [V] 19.5 19.5 19.5 19.5 19.5 19.5
Iin [A] 0.257 0.263 0.257 0.283 0.257 0.292
Pin [W] 5.00 5.11 5.00 5.51 5.00 5.67
Vo,rms [V] 15.4 15.4 14.8 15.4 13.9 14.6
Io,rms [A] 0.309 0.309 0.297 0.309 0.279 0.292
Po [W] 4.77 4.76 4.40 4.76 3.89 4.25
η [%] 95.4 93.2 88.1 86.3 77.8 75.0
THD [%] - 13.7 - 5.54 - 5.48

B. Circuit Experiment
The experimental circuits were built and tested. Table IV
shows parameters in the experimental circuits. MOSFET Vin
(IRFR120Z [27]) was selected as the switch S. Fig. 11 shows vds
observed waveforms of the input voltage Vin, the drain-source
voltage vds, the switch current iS, and the output voltage vo. As
iS
shown in Fig. 11, the observed waveforms were in good
agreement with the theoretical waveforms. However, in Fig. vo
11 (a), the drain-source voltage vds didn’t completely achieve
ZVS or ZVDS at turning-on and a ringing was occurring in
the switch current iS, which was caused by low value of loaded
quality factor Q. The waveform equations are derived based
on the assumption that the output voltage is the sinusoidal
(a)
wave in section II. The output waveform was not completely
sinusoidal waveform because of the low loaded quality factor
Q, which affected the other waveforms. Judging from the
observed waveforms, the peak voltage Vsm was about 80 V and Vin
the peak current Ism was about 0.60 A, which were in good vds
agreement Table I. iS
Table V shows the experimental results. From Table V, the
power conversion efficiency and THD decrease as the loaded
vo
quality factor Q increases. Fig. 12 shows the theoretical power
losses breakdown of the experimental circuits. From Fig. 12,
as the loaded quality factor Q increases, the conduction loss
of the resonant circuit Lr-Cr and the core loss of the resonant
inductor Lr increase.
Table VI shows the comparison of Class E families. From (b)
Table VI, the number of components is smaller than the other
Class E inverters. In addition, the choke inductor and the dc
blocking capacitor are needless. To preserve the impartiality Vin
of comparison, each data is based on the original references. vds
Since efficiency is depend on frequency, voltage, power, and
iS
load resistance, it is difficult to simply compare them each
other. The proposed circuit has similar power conversion
efficiency to the other topologies. vo

(c)
Fig. 11. Observed waveforms of the input voltage Vin, the drain-source
voltage vds, the switch current iS, and the output voltage vo, Vin: 20.0
V/div, vds: 50.0 V/div, iS: 1.00 A/div, vo: 20.0 V/div, horizontal: 0.250
μs/div,
(a) Case I: Q = 2, (b) Case II: Q = 5, (c) Case III: Q = 8.

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

1.20
Core loss of resonant inductor Lr
1.00

Power losses [W]


Core loss of inductor Ls
0.80
Conduction loss of resonant circuit Lr-Cr
0.60
Winding loss of inductor Ls
0.40
Conduction loss of capcitor Cs
0.20
On-resistance
0.00
Q=2 Q=5 Q=8
Fig. 12. Theoretical power losses breakdown of the experimental circuits.

TABLE VI. COMPARISON OF CLASS E FAMILIES


Resonant Choke DC Block Vin RLoad Po f η
Inductor Capacitor Switch
Tank Inductor Capacitor [V] [Ω] [W] [MHz] [%]
Class E [6] 2 2 1 S Yes No 130 50 300 7.29 91.1
Class DE [12] 1 3 2 S No No 90 57.2 6.86 1.45 97.7
Class E-1 [9] 3 2 1 P Yes Yes 20 34.7 10 4.00 87
Class EF2 [14] 3 3 1 S Yes No 30.0 5.00 22.7 6.78 91.1
Class  [15] 3 3 1 S No No 200 50 500 30 92
Class E with 1.4-2.7 63-
3 3 1 P Yes Yes 24 50 10
shunt filter [22] GHz 73
This work 2 2 1 P No No 19.5 50 4.76 1.00 93.2

IV. CONCLUSION Circuits Syst. I: Fundam. Theory Appl., vol. 43, no. 1, pp. 51-60, Jan.
1996.
The voltage-source parallel resonant Class E inverter has
[12] H. Sekiya, X. Wei, T. Nagashima, and M. K. Kazimierczuk, “Steady-
been proposed. The proposed circuit has a shunt capacitor and state analysis and design of Class-DE inverter at any duty ratio,” IEEE
achieves zero-voltage switching (ZVS) and zero-voltage Trans. Power Electron., vol. 30, no. 7, pp. 3685-3694, Jul. 2014.
derivative switching (ZVDS) at turning-on like the classical [13] Z. Kaczmarczyk, “High-effciency Class E, Class EF2, Class E/F3
inverters,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1584-1593,
Class E inverter. Therefore, high power conversion efficiency
Oct. 2006.
is achieved under high operating frequency. The proposed [14] S. Aldhaher, D. C. Yates, and P. D. Mitcheson, “Modeling and analysis
circuit has no choke inductor or dc blocking capacitor. of Class EF and Class E/F inverters with series-tuned resonant
Therefore, it is possible to reduce the size. In addition, it has networks,” IEEE Trans. Power Electron., vol. 31, no. 5, pp. 3415-3430,
May 2016.
the parallel resonant circuit. The experimental results were in
[15] J. M. Rivas, Y. Han, O. Leitermann, A. D. Sangneri, and D. J. Perreault,
good agreement with the theoretical waveforms. Measured “A High-frequency resonant inverter topology with low-voltage stress,”
power conversion efficiency was 93.2 % with the output IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1759-1771, Jul. 2008.
power 4.76 W at the operating frequency 1 MHz. [16] P. C. K. Luk, S. Aldhaher, W. Fei, and J. F. Whidborne, “State-space
modeling of a ClassE2 converter for inductive links,” IEEE Trans.
Power Electron., vol. 30, no. 6, pp. 3242-3251, Jul. 2015.
REFERENCES [17] M. Liu, Y. Qiao, S. Liu, and C. Ma, “Analysis and design of a robust
[1] A. Knott, T. M. Andersen, P. Kamby, J. A. Perdersen, M. P. Madsen, M. Class E2 DC–DC converter for megahertz wireless power transfer,”
Kovacevic, and M. A. Andersen, “Evolution of very high frequency IEEE Trans. Power Electron., vol. 32, no. 4, pp. 2835-2845, Apr. 2017.
power supplies,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 2, [18] S. Liu, M. Liu, S. Han, X. Zhu, and C. Ma, “Tunable Class E2 DC–DC
no. 3, pp. 386-394, Sep. 2014. converter with high efficiency and stable output power for 6.78-MHz
[2] N. O. Sokal and A. D. Sokal, “Class E-a new Class of high-efficiency wireless power transfer,” IEEE Trans. Power Electron., vol. 33, no. 8,
tuned single-ended switching power amplifiers,” IEEE Journal Solid- pp. 6877-6886, Aug. 2018.
State Circuits, vol. 10, no. 3, pp. 168-176, Jun. 1975. [19] C. S. Wang, O. H. Stielau, and G. A. Covic, “Design considerations for
[3] F. H. Raab, “Idealized operation of the class E tuned power amplifier,” a contactless electric vehicle battery charger,” IEEE Trans. Ind.
IEEE Trans. Circuits Syst., vol. 24, no. 12, pp. 725-735, Dec. 1977. Electron., vol. 52, no. 5, pp. 1308-1314, Oct. 2005.
[4] M. K. Kazimierczuk and D. Czarkowski, Resonant Power Converters, [20] J. L. Villa, J. Sallan, J. F. S. Osorio, and A. Llombart, “High-
2nd ed., New Jersy: John Wiley & Sons, 2011. misalignment tolerant compensation topology for ICPT systems,”
[5] A. Grebennilov and F. H. Raab, “A History of switching-mode Class- IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 945-951, Feb. 2012.
E techniques: The development of switching-mode Class-E techniques [21] V. Ravikiran and R. K. Keshri, “Comparative evaluation of S-S and P-
for high-efficiency power amplification,” IEEE Microw. Mag., vol. 19, S topologies for wireless charging of electrical vehicles,” in Proc. 2017
no. 5, pp. 26-41, Jul. 2018. 43rd IEEE Ind. Electron. Soc. Conf., Beijing, 2017, pp. 5324-5329.
[6] D. J. Kessler and M. K. Kazimierczuk, “Power losses and efficiency of [22] A. Grebennikov, “High-efficiency Class-E power amplifier with shunt
class-E power amplifier at any duty ratio,” IEEE Trans. Circuits Syst., capacitance and shunt filter,” IEEE Trans. Circuits Syst. I: Reg. Papers,
vol. 51, no. 9, pp. 1675-1689, Sep. 2004. vol. 63, no. 1, pp. 12-22, Jan. 2016.
[7] T. Mury and V. F. Fusco, “Series-L/parallel-tuned comparison with [23] P. Chen, K. Yang, and T. Zhang, “Analysis of a Class-E power
shunt-C/series-tuned class-E power amplifier,” IEE Proc. Circuits amplifier with shunt filter for any duty ratio,” IEEE Trans. Circuits Syst.
Devices Syst., vol. 153, no. 6, pp. 709-717, Dec. 2005. II: Express Briefs, vol. 64, no. 8, pp. 857-861, Aug. 2017.
[8] T. Mury and V. F. Fusco, “Sensitivity Characteristics of inverse Class- [24] Micrometals, T80-2 datasheet. [Online]. Available:
E power amplifier,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 54, https://micrometalsarnoldpowdercores.com/pdf/T80-2-DataSheet.pdf.
no. 4, pp. 768-778, Apr. 2007. [25] Micrometals, T106-2 datasheet. [Online]. Available:
[9] A. Sheikhi, M. Hayati, and A. Grebennikov, “High-efficiency Class- https://micrometalsarnoldpowdercores.com/pdf/T106-2-
E−1 and Class-F/E power amplifiers at any duty ratio,” IEEE Trans. Ind. DataSheet.pdf.
Electron., vol. 63, no. 2, pp. 840-848, Feb. 2016. [26] Micrometals, T130-2 datasheet. [Online]. Available:
[10] M. Thian and V. F. Fusco, “Idealised operation of zero-voltage- https://micrometalsarnoldpowdercores.com/pdf/T130-2-
switching series-L/parallel-tuned Class-E power amplifier,” IET DataSheet.pdf.
Circuits Devices Syst., vol. 2, no. 3, pp. 337-346, Jun. 2008. [27] Infineon, IRFR120Z datasheet. [Online]. Available:
[11] H. Koizumi, T. Suetsugu, M. Fujii, K. Shinoda, S. Mori, and K. Ikeda, http://www.infineon.com/dgdl/irfr120zpbf.pdf.
“Class DE high-efficiency tuned power amplifier,” IEEE Trans.

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics

Akinobu Shigeno (S’17) received the B.E.


degree in electrical engineering from the
Tokyo University of Science, Tokyo,
Japan, in 2017, where he is currently
working toward the M.E. degree. His
research interests include resonant power
converters.

Hirotaka Koizumi (S'98-M'01) was born


in Tokyo, Japan, in 1970. He received the
B.E., M.E., and Ph.D. degrees in electrical
engineering from Keio University,
Yokohama, Japan, in 1993, 1995, and
2001, respectively.
From 1995 to 2001, he was an electrical
engineer with Tokyo Electric Power
Company Inc., Tokyo. From 1998 to 2001,
he was with the Graduate School, Keio
University. From 2001 to 2007, he was
with Tokyo University of Agriculture and
Technology, Tokyo, as a research associate. Since April 2007, he has
been with Tokyo University of Science, Tokyo, where he is a
Professor. His research interests include photovoltaic systems, high-
frequency high-efficiency tuned power amplifiers, resonant dc/dc
power converters, dc/ac inverters, and high-frequency rectifiers.
Prof. Koizumi is a member of the Institute of Electrical Engineers
of Japan (IEEJ), and the Institute of Electronics, Information, and
Communication Engineers (IEICE) of Japan. From May 2008 to
May 2010, he was the Secretary of the IEEE Circuits and Systems
Society Power Systems and Power Electronic Circuits Technical
Committee. From May 2012 to May 2013 and from May 2013 to
May 2014, he was the Chair and the Past Chair of the IEEE Circuits
and Systems Society Power and Energy Circuits and Systems
Technical Committee.

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

Potrebbero piacerti anche