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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics
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Transactions on Power Electronics
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics
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Transactions on Power Electronics
a3 Vo 1
j2 = sin 2πa (1 - D ) sin 2πD M VR = =
a - 12
2
(65) 2Vin 2b
a a2 (80)
cos 2πa (1 - D ) cos 2πD + 2
j1
- 2 , = .
a -1 a -1 2 ( j2 sin + j3 cos )
a3 From (79), the output current io and the current iCb flowing
j3 = - 2 sin 2πa (1 - D ) cos 2πD
a -21 through the capacitance Cb are
a (66)
- 2 cos 2πa (1 - D ) sin 2πD V
io (t ) = o sin (t + )
a -1
+ a sin 2πa (1 - D ) . (81)
RL
= I o sin (t + ) ,
From (8) and (55),
iCb (t ) = CbVo cos (t + )
d vds (t ) = I Cb cos (t + ) , (82)
d t Vo t = 2π (67) where Io and ICb are the amplitudes of the output current io and
a2 the current iCb. The current through the parallel resonant
= ag1 cos 2πa - ag 2 sin 2πa - 2 cos = 0
a -1 circuit is equal to the inductor current iLs.
which can be rewritten as 1 2π
j4b = j5 sin + j6 cos I o = iLs (t )sin(t + )dt
(68) π 0 (83)
where = CsVo k ,
j4 = sin 2πa (1 - D ) + 2πaD cos 2πa (1 - D ) , 1 2π
(69) I Cb = iLs (t ) cos(t + )dt
3 π 0 (84)
j5 =
a
cos 2πa (1 - D ) sin 2πD = CsVo l ,
a2 -1 2 (70) where
a
+ 2 sin 2πa (1 - D ) cos 2πD,
a -1 k=
1 2
π2
(a b sin ( 2πD + ) - 2πD cos ( 2πD + )
a3 a
j6 = - 2 cos 2πa (1 - D ) cos 2πD - cos 2 ( 2πD + ) + a 2 cos cos ( 2πD + )
a - 12 4
a a2
+ 2 sin 2πa (1 - D ) sin 2πD (71) -a 2 b sin + cos 2 - a 2 cos 2
a -1 4
a2 a2
cos 2 ( 2πD + )
a
+ a cos 2πa (1 - D ) + 2 . + cos 2 -
a -1 4(a 2 - 1) 4(a 2 - 1)
From (63) and (68), g cos[2π(1 - a) + ] cos[2π(1 + a) + ] (85)
+ 1 -
j j -j j 2 a -1 a +1
tan = 3 4 1 6 , (72) g 2 sin[2π(1 - a) + ] sin[2π(1 + a) + ]
j1 j5 - j2 j4 + +
2 a -1 a +1
j2 j g cos[2πD(1 - a ) + ] cos[2πD(1 + a ) + ]
b= sin + 3 cos . (73) - 1 -
j1 j1
2 a -1 a +1
The waveform equations at a ≠ 1 are summarized as follows, g 2 sin[2πD(1 - a ) + ] sin[2πD(1 + a ) + ]
0 0 t 2πD - + ,
vds (t )
2 a -1 a +1
= g1 sin at + g 2 cos at + b
(74)
Vo - 2
a2
sin (t + )
2πD t 2π
iS (t )
RL
a -1
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Transactions on Power Electronics
RL k 5.50
. Ls = (88) a=0.500
a 2
0.10
output capability cp reaches a maximum about D =0.55 and a
= 1.75.
Table I shows comparison of the proposed circuit with the 0.08
3.00
a=0.500 0.105
a=0.750
2.50 a=1.00
a=1.25
2.00 a=1.50 0.100
a=1.75
ωCsRL
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Transactions on Power Electronics
inductor Ls, the capacitor Cs, the resonant capacitor Cr, and the where rLs is the ESR of the inductor Ls and ILs,rms is the RMS
resonant inductor Lr are considered. The switching loss is value of the inductor Ls. From (78), the RMS inductor current
neglected. The power conversion efficiency is expressed as ILs,rms is
I Ls , rms (t )
Po
= , (94) 1 2π 2
Po + PS + PCs + PLs + PR + PLscore + PLrcore =
2π 0 iLs (t ) dt
1 2πD 2
where Po is the output power, PS, PCs, PLs, and PR are iS (t ) d t + iCs 2 (t ) d t
2π
2π 0
=
2πD
conduction losses of the switch S, the capacitor Cs, the Vo 8 3 2 3 1
inductor Ls, and the parallel resonant circuit Lr-Cr, and PLscore = π b D + 2π D + sin(4πD + 2 )
Ls 2π 3 4
and PLrcore are core losses of the inductor Ls and the resonant + πD cos 2 + 2b cos(2πD + ) + (4πbD - 2 cos ) sin(2πD + )
inductor Lr. 3
-(4π 2 bD 2 + 2b) cos + sin 2
4
The conduction loss PS is expressed as 1 1
+ 2 a 2 ( g12 + g 22 )π + a 2 ( g12 - g 22 ) sin 4πa
PS = ron I S2, rms , (95) a 4a
a4 1 1
where ron is the on resistance of the switch S and IS,rms is the + 2 (π + sin 2 ) + ag1 g 2 cos 4πa
(a - 1) 2 4 2 (100)
RMS value of the switch current iS. From (75), the RMS 2a 3 g
- 2 1 2 (a cos sin 2πa - cos 2πa sin )
switch current IS,rms is (a - 1)
1 2πD 2 2a 3 g
- 2 2 2 (a cos cos 2πa + sin sin 2πa )
I S , rms (t ) = iS (t ) d t
2π 0
(a - 1)
a
-a 2 ( g12 + g 22 )πD - ( g12 - g 22 ) sin 4πaD
Vo 8 3 2 3
= π b D + 2πD 4
Ls 2π 3
a4 1 1
- 2 2
πD + sin(4πD + 2 ) - ag1 g 2 cos 4πaD
(a - 1) 4 2
1
+ sin(4πD + 2 ) + πD cos 2 (96) 2a 3 g
+ 2 1 2 a cos(2πD + ) sin 2πaD - cos 2πaD sin(2πD + )
4 (a - 1)
+2b cos(2πD + ) 1
2
+(4πbD - 2 cos )sin(2πD + ) 2a 3 g
+ 2 2 2 a cos(2πD + ) cos 2πaD + sin(2πD + ) sin 2πaD .
1 (a - 1)
3 2
-(4π bD + 2b) cos + sin 2 .
2 2
The conduction loss PR is expressed as
4 Vo2 ( RLP + RCP )
The conduction loss PCs is expressed as PR = , (101)
2 RLP RCP
PCs = rCs I Cs
2 , (97)
, rms
where RLP and RCP are the EPRs of the resonant inductor Lr
where rCs is the ESR of the capacitor Cs and ICs,rms is the RMS and the resonant capacitor Cr. The relationships between the
value of the capacitor current iCs. From (76), the RMS EPRs are
capacitor current ICs,rms is
ωL
2
I Cs , rms (t )
RLP = rL 1 + r , (102)
=
1 2π 2
2πD iCs (t ) dt
rL
2π
CsVo
1
1 2
= a ( g1 + g 2 )π + a ( g1 - g 2 )
2 2 2 2 2 2
sin 4πa
2π 4a RCP = rL 1 + . (103)
a 4
1 1 ωC r
+ 2 (π + sin 2 ) + ag1 g 2 cos 4πa r C
(a - 1) 2 4 2
2a 3 g1 The core loss PLscore and PLrcore are derived based on the data
- 2 (a cos sin 2πa - cos 2πa sin )
(a - 1) 2 sheet [24]-[26].
2a 3 g 2
- 2 (a cos cos 2πa + sin sin 2πa ) (98)
(a - 1) 2
a
-a ( g1 + g 22 )πD - ( g12 - g 22 ) sin 4πaD
2 2
4
1
4
a 1
- 2 2
πD + sin(4πD + 2 ) - ag1 g 2 cos 4πaD
(a - 1) 4 2
2a 3 g
+ 2 1 2 a cos(2πD + ) sin 2πaD - cos 2πaD sin(2πD + )
(a - 1)
1
2
a cos(2πD + ) cos 2πaD + sin(2πD + ) sin 2πaD .
2a 3 g 2
+
(a 2 - 1) 2
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Transactions on Power Electronics
Vin,vo[V]
carried out. Experimental circuits were designed based on the 0
following conditions.
1) The operation frequency f = 1.00 [MHz] -30
(a)
100
2) The output power Po = 5.00 [W]
3) The load resistance R = 50 [Ω]
vds[V]
4) The parameter a = 1.75
5) The on duty ratio D = 0.55 0
iS[A]
A. Simulation Results
To confirm the designed circuit operation under the ideal 0
condition, the proposed circuit was simulated with PSIM ver. -0.2
(c)
11.0. Table II shows parameters in the simulations. In this 1.500 1.501 1.502 1.503 1.504 1.505
Time [ms]
simulation, all the components were assumed to be ideal. Figs.
Fig. 8. Simulation waveforms at Q = 2, (a) input voltage Vin, output
8-10 show simulation waveforms of the input voltage Vin, the voltage vo, (b) drain-source voltage vds, (c) switch current iS.
output voltage vo, the drain-source voltage vds, and the switch 30
current iS. As shown in Figs. 8-10, the switch S achieved ZVS
Vin,vo[V]
section II.
iS[A]
-30
(a)
100
vds[V]
0
(c)
0.8
iS[A]
0
-0.2
(d)
1.500 1.501 1.502 1.503 1.504 1.505
Time [ms]
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Transactions on Power Electronics
B. Circuit Experiment
The experimental circuits were built and tested. Table IV
shows parameters in the experimental circuits. MOSFET Vin
(IRFR120Z [27]) was selected as the switch S. Fig. 11 shows vds
observed waveforms of the input voltage Vin, the drain-source
voltage vds, the switch current iS, and the output voltage vo. As
iS
shown in Fig. 11, the observed waveforms were in good
agreement with the theoretical waveforms. However, in Fig. vo
11 (a), the drain-source voltage vds didn’t completely achieve
ZVS or ZVDS at turning-on and a ringing was occurring in
the switch current iS, which was caused by low value of loaded
quality factor Q. The waveform equations are derived based
on the assumption that the output voltage is the sinusoidal
(a)
wave in section II. The output waveform was not completely
sinusoidal waveform because of the low loaded quality factor
Q, which affected the other waveforms. Judging from the
observed waveforms, the peak voltage Vsm was about 80 V and Vin
the peak current Ism was about 0.60 A, which were in good vds
agreement Table I. iS
Table V shows the experimental results. From Table V, the
power conversion efficiency and THD decrease as the loaded
vo
quality factor Q increases. Fig. 12 shows the theoretical power
losses breakdown of the experimental circuits. From Fig. 12,
as the loaded quality factor Q increases, the conduction loss
of the resonant circuit Lr-Cr and the core loss of the resonant
inductor Lr increase.
Table VI shows the comparison of Class E families. From (b)
Table VI, the number of components is smaller than the other
Class E inverters. In addition, the choke inductor and the dc
blocking capacitor are needless. To preserve the impartiality Vin
of comparison, each data is based on the original references. vds
Since efficiency is depend on frequency, voltage, power, and
iS
load resistance, it is difficult to simply compare them each
other. The proposed circuit has similar power conversion
efficiency to the other topologies. vo
(c)
Fig. 11. Observed waveforms of the input voltage Vin, the drain-source
voltage vds, the switch current iS, and the output voltage vo, Vin: 20.0
V/div, vds: 50.0 V/div, iS: 1.00 A/div, vo: 20.0 V/div, horizontal: 0.250
μs/div,
(a) Case I: Q = 2, (b) Case II: Q = 5, (c) Case III: Q = 8.
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Transactions on Power Electronics
1.20
Core loss of resonant inductor Lr
1.00
IV. CONCLUSION Circuits Syst. I: Fundam. Theory Appl., vol. 43, no. 1, pp. 51-60, Jan.
1996.
The voltage-source parallel resonant Class E inverter has
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“Class DE high-efficiency tuned power amplifier,” IEEE Trans.
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2892421, IEEE
Transactions on Power Electronics
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