Republic of the Philippines

CAVITE STATE UNIVERSITY

Don Severino de las Alas Campus
Indang, Cavite
 (046) 415-0010 / (046) 415-0021
www.cvsu.edu.ph

AND GATE IMPLEMENTATION

Given
𝐹 =𝐴𝑥𝐵𝑥𝐶

Truth Table
𝑨 B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Screenshots

1. Circuit from Electric (Schematic Diagram)

Iruguin, Jan Marielle Laboratory Activity 8 Engr.Sumadsad 1

201511407 / BSECE 5-1 AND GATE 10/07/2019 00 2

2.
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 2. Netlist
*** TOP LEVEL FACET: AND3{sch}
** GROUND NET: 0 (net1)
** PORT A (network: A)
** PORT B (network: B)
** PORT C (network: C)
** PORT F (network: F)
Cnode28 0 F 100F
Mnode5 F net2 0 0 N L=0.70U W=1.60U
Mnode6 F net3 0 0 N L=0.70U W=1.60U
Mnode7 F net4 0 0 N L=0.70U W=1.60U
Mnode8 net6 net4 F net5 P L=0.70U W=9.60U
Mnode9 net7 net3 net6 net5 P L=0.70U W=9.60U
Mnode10 net5 net2 net7 net5 P L=0.70U W=9.60U
Mnode22 net4 C 0 0 N L=0.70U W=1.60U
Mnode23 net5 C net4 C P L=0.70U W=6.40U
Mnode24 net3 B 0 0 N L=0.70U W=1.60U
Mnode25 net5 B net3 B P L=0.70U W=6.40U
Mnode26 net5 A net2 A P L=0.70U W=6.40U
Mnode27 net2 A 0 0 N L=0.70U W=1.60U
** Sources and special nodes:
Vnode12 net5 0 3
Vnode19 C 0 pulse 0 3 0 1n 1n 50n 100n
Vnode20 B 0 pulse 0 3 0 1n 1n 100n 200n
Vnode21 A 0 pulse 0 3 0 1n 1n 200n 400n
.PRINT TRAN V(F)+18 V(C)+12 V(B)+6 V(A)
.TRAN 1p 400n 1n 1n
.END
3. Simulation Results

Iruguin, Jan Marielle Laboratory Activity 8 Engr.Sumadsad 2

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201511407 / BSECE 5-1 AND GATE 10/07/2019 2