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A Zero-Voltage-Transition Bidirectional DC/DC

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IEEE Transactions on Industrial Electronics 1

A Zero-Voltage-Transition Bidirectional Three-

Level DC/DC Converter
Serkan Dusmez, Student Member, IEEE, and Alireza Khaligh, Senior Member, IEEE
Abstract— A three-level (TL) bidirectional dc/dc converter is a iS1 + +
suitable choice for power electronic systems with high voltage dc +
link, as the voltage stress on the switches is half and inductor S1 D1 vS1

current ripple frequency is twice of the converter’s switching ZVT Circuit 1

frequency. This study proposes a zero-voltage-transition (ZVT) iLr1 icr1
TL dc/dc converter to enable operation with higher switching +
Lr1 Cr1 vcr1
frequency in order to achieve higher power density and enhance Co1
efficiency. Two identical ZVT cells, each one composed of two +
+ iLin Lin Sa1 Da1 va1
resonant inductors, a capacitor, and an auxiliary switch are Lr2 Vco1
integrated with the conventional TL topology to enable soft- iLr2
switching in all four switches in both buck and boost operation iS2
modes. In addition, a variable dead-time control is proposed to +
increase the effective duty ratio at heavy loads. The proposed S2 D2 vS2
soft-switching feature has been demonstrated under different Vo
Vin +
loading conditions. A 650W prototype is designed and fabricated, +
S3 D3 vS3
which exhibits 95.5% at full load.
Index Terms-- bidirectional three-level converter, zero-voltage- ZVT Circuit 2
transition cell, non-isolated dc/dc converter, power electronics.
+ Vco2
Lr3 Cr2 vcr2
I. INTRODUCTION + Co2
Sa2 Da2 va2
In bidirectional non-isolated buck/boost dc/dc converter Lr4
applications, a two-quadrant non-isolated buck/boost
converter has been preferred in many studies due to its simple
two-switch structure, low cost, and high efficiency [1]-[6]. +
However, in high-voltage (400V-600V) and medium to high S4 D4 vS4

power applications such as the dc/dc bidirectional converter in

electric vehicles (EV), two-switch structure exhibits several
shortcomings; 1) low efficiency at light load due to high
power losses associated with the parasitic capacitances of the
switches, 2) utilization of IGBTs instead of MOSFETs in high
voltage applications, while switching frequency of converter is
limited by the IGBT’s maximum switching frequency under
hard-switching. As a result, the passive components such as
the inductors and capacitors render a large volume. To
increase the input current ripple frequency, interleaved
structures are studied [7]-[9]. Interleaving reduces the size of
the passive components, however; still requires high voltage
rating switches. In order to equally distribute the voltage stress
among the switches, and to use MOSFETs at high voltages
Manuscript received June 22, 2014; revised September 22, 2014;
accepted November 10, 2014.
Copyright © 2014 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org.
This work was supported in part by the NSF ECCS under Grant 1307228,
and the Genovation Cars Inc, which are gratefully acknowledged.
S. Dusmez was with the Power Electronics, Energy Harvesting and
Renewable Energies Laboratory (PEHREL), Electrical and Computer
Engineering Department, University of Maryland. He is now with the
Electrical and Computer Engineering Department, University of Texas at
Dallas, Richardson, TX 75080 USA (e-mail: serkan.dusmez@utdallas.edu).
A. Khaligh is with the Power Electronics, Energy Harvesting and
Renewable Energies Laboratory (PEHREL), Institute for System Research
and Electrical and Computer Engineering Department, University of
Maryland, College Park, MD 20742 USA (e-mail: khaligh@ece.umd.edu).
Fig. 1. Proposed bidirectional three-level dc/dc converter with auxiliary ZVT
cell.
while still increasing the inductor current ripple frequency to
twice of the switching frequency, a three-level (TL) output
voltage buck/boost dc/dc converter has been proposed and
suggested for use in high voltage applications [10].
To increase power density through higher switching
frequencies without sacrificing converter efficiency, soft-
switching techniques are employed [11]-[13]. A common way
to achieve soft-switching is to use interleaving circuits where
the stored energy in the interleaving inductor is used to
discharge the parasitic capacitances of the switches [14]-[17].
Similarly, an auxiliary inductor can be coupled to the main
inductor to reduce the cost of the circuit [18]-[23].
Another method to effectively achieve soft-switching is
through employing auxiliary switch to store the switching
energy in the auxiliary capacitor, which is then used to soft-
switch the main switch either during turn-on or turn-off
instants. Soft-switching cells, consisting of an auxiliary
switch, a resonant inductor and a capacitor, are common [24]-
[27]. In [24], the soft-switching cell is used to turn off the
switch under zero current, and turn on the auxiliary switch
under near zero current. Another ZCS was introduced in [25]
for boost converter, which is then generalized for other
converter types such as buck, buck/boost, SEPIC, and Cuk. In
[26], unified analysis for these soft-switching cells was
IEEE Transactions on Industrial Electronics 2

S1 C1 S1 D1 S1 D1

Lin Lin Lr1 Cr1 Lin Lr1 Cr1 Lin Lr1 Cr1
Co1 Co1 Co1
Sa1 Da1 Sa1 Da1 Sa1 Da1
Lr2 Lr2 Lr2 Lr2

Vin S2 C2 Vin S2 C2 Vin S2 C2 Vin S2 C2

S3 C3 S3 D3 S3 D3 S3 D3

Lr3 Lr3 Lr3 Lr3

(a) (b) (c) (d)

S1 D1 S1 D1 S1 D1 S1 D1

Lr1 Cr1 Lin Lr1 Cr1 Lr1 Cr1 Lr1 Cr1

Lin Lin Lin
Co1 Co1 Co1 Co1
Sa1 Da1 Sa1 Da1 Sa1 Da1 Sa1 Da1
Lr2 Lr2 Lr2 Lr2

Vin S2 C2 Vin S2 C2 Vin S2 D2 Vin S2 D2

S3 D3 S3 D3 S3 D3 S3 D3

Lr3 Lr3 Lr3 Lr3

(e) (f) (g) (h)

Fig. 2. Operation intervals and equivalent circuits; (a) Operation interval 1: t<t 0, (b) Operation interval 2: t0<t<t1, (c) Operation interval 3: t1<t<t2, (d) Operation
interval 4: t2<t<t3, (e) Operation interval 5: t3<t<t4, (f) Operation interval 6: t4<t<t5, (g) Operation interval 7: t5<t<t6, (h) Operation interval 8: t6<t<t7.

Table I. Summary of the ZVT Operation. switching cells are deployed for each pair of switches,
Resonant Auxiliary ZVT ensuring that all four switches are turned on under zero-
Inductor Switch Switch voltage in both boost and buck modes. Thus, the proposed
Lr2 Sa1 S2 ZVT TL converter can be operated at higher switching
Boost mode
Lr3 Sa2 S3 frequencies, the input current ripple frequency can be doubled,
Lr4 Sa2 S4 and the size of the inductor can be significantly reduced.
Buck mode The common issue with the soft-switching converters is the
Lr1 Sa1 S1
limited soft-switching operation range due to the output
current dependency of the soft-switching operation. When the
explored. In [27], a similar soft-switching cell used in this
ZVT cell designed for light load condition operates under
paper has been proposed for bidirectional non-isolated
heavy load, the effective on-time of the switches becomes less
buck/boost dc/dc converter. Yet, no soft-switched non-isolated
than the reference. To partially compensate this negative effect
TL converter has been explored in literature.
on the duty ratio of the main switch, the auxiliary switch is
Reducing the switching losses is critical to achieve higher
controlled through adjusting the dead-time with respect to
efficiency. In this regard, this manuscript proposes a zero-
peak inductor current. The improvement on the effective duty
voltage-transition TL bidirectional dc/dc converter for wide
ratio using the proposed variable dead-time control is analyzed
load range, as illustrated in Fig. 1. Two identical soft-
IEEE Transactions on Industrial Electronics 3

t01 t45
t23 t67
t12 t34
t56

vgs2
vgsa1

iS1

iS2

iCr1

iLr1
iLr2

vS1

vS2

vCr1
vLr1

vLr2

t0 t 1 t 2 t3 t4 t5 t6 t7
Fig. 3. The switching scheme and circuit waveforms of the proposed ZVT converter.

and compared with the conventional fixed dead-time approach
within the content of the manuscript. Even though, the
improvement on the duty ratio is analyzed in this paper, the
proposed technique is a possible solution for secondary
control objectives, such as capacitor voltage balancing.
II. PROPOSED BIDIRECTIONAL ZVT TL DC/DC CONVERTER
The proposed converter achieves ZVT for all the switches
during turn-on instants in all operation modes. The ZVT cell
contains two resonant inductors, one resonant capacitor and an
auxiliary switch to eliminate the turn-on losses of switches by
creating a resonance between the inductor and capacitor. The
energy stored in the auxiliary inductor during the normal
operation, is transferred to the capacitor when the main switch
is turned off. This energy is then recycled through the body-
diode of the main switch before it is turned on. An identical
ZVT cell is placed between switches S3 and S4 to soft switch
the bottom two switches. The basic operation principle of the
ZVT cell is identical in each transition mode for both boost
and buck operations. Table I summarizes the ZVT cell
operation depending on the buck and boost modes, used
resonant inductor, auxiliary switch and soft-switched
MOSFET.
The equivalent circuits and operation waveforms are given
in Fig. 2 and Fig. 3, respectively. Here, the operation principle
will be given for turning-on instant of S2 in boost mode when
d>0.5. It should be noted that Lr3 is not involved during this
switching-state transition and can be assumed as an additional
contributing inductance to Lin. For the sake of the symmetrical
operation, the resonant inductors are chosen equal, Lr1=Lr2
Lr3=Lr4=Lr.
Operation interval 1 [t < t0]: Before t0, both S2 and S3 are on,
Lin stores energy, and converter operates in boost operation
mode of the TL converter. In this mode, iLr1(t0)=0. If on-time
of the auxiliary switch is equal to the quarter of the resonance
period, the resonant capacitor voltage becomes zero at t0,
(vCr1(t0)=0). This will be explained in latter sections. The
current of Lr2 is equal to
IEEE Transactions on Industrial Electronics 4

Vin Operation interval 5 [t3 ≤ t < t4]: Before S2 is turned on, the
i Lr 2 t   i Lr 2 t 7   t (1)
Lin  2 L r auxiliary switch, Sa1, is turned on to transfer the energy stored
This time interval is determined by the effective on-time duty in the capacitor to the resonant inductor, iLr2. Sa1 is turned on
ratio of S2. under zero-current, thus there is no switching turn-on loss for
the auxiliary switches. vLr2 is half of the vCr1 and iLr2 increases
Operation interval 2 [t0 ≤ t < t1]: At t=t0, S2 is turned off. The sinusoidally. C2 is first quickly charged to vCr1+Vo/2, then is
current of Lr2 begins to resonate in the resonance tank discharged as vCr1 decreases. At t=t3, the initial conditions are
composed of Lr1-Lr2-Cr1. The sum of the voltages of the as follows; iLr2(t3)=0, vcr1(t3)=vcr1(t2). In this interval, the
inductors vL1+vL2 is equal to vcr1. During this short time resonant inductor currents and capacitor voltage are
interval, the parasitic capacitance of the upper switch, C1,
discharges over the output capacitor, and transfers its energy vCr1 t   vCr1 t 3 cost  (13)
while C2 is charged as vS1(to)=Vo/2, and vS1+vCr1+vS2 =Vo/2
during t01. The initial conditions can be noted as iLr 2 t   Cr vCr1 t3  sint  (14)
1  Vin 
iLr 2  t0   iLr 2  t7     t70 (2) iLr1 t   iLr1 t3   Cr vCr1 t3  sint  (15)
2  Lin  2 L r 

iLr1 t0   0 (3) t 34 
2
(16)

vCr1  t0   0 (4) At the end of this mode, vCr1(t4)=vCr1(t0)=0.

The natural frequency of the resonant tank is expressed as Operation interval 6 [t4 ≤ t < t5]: When the energy stored in
1 the resonant capacitor is completely transferred via Sa1, C2
 (5) quickly discharges to zero. This time interval can be expressed
2 Lr Cr 1
as
Operation interval 3 [t1 ≤ t < t2]: C1 is discharged completely  CV
2 
2 Lr  iLr 2 t4   iLr 2 t4   2 o 
2
at the end of operation interval 2, as current begins  2 Lr  (17)
commutating from Lr2 to Lr1, and D1 conducts. C2 continues to t45   
get charged. This interval occurs very quickly as C1 is Vo
typically in the order of several hundreds of pF, and is not At t=t5, the current of D1 increases to approximately twice of
included in the calculations for simplicity. The energy stored the load current.
in Lr2 is transferred to resonant capacitor Cr1 through Da1. For Operation interval 7 [t5 ≤ t < t6]: When vS2 reaches to -0.7V,
this interval, the resonant inductor currents can be expressed the body diode of S2 conducts. This time period is the ZVT
as period. S2 can be turned-on at any time during this interval. At
iLr 2 t   iLr 2 t0  cost  (6) t=t5, the initial conditions are

Cr1 vCr12  t2 
iLr1 t   iLr 2 t0 1  cost  (7) iLr 2  t5    (18)
2 Lr
The resonant capacitor voltage can be written as
iLr 2 t0  iLr1 t5   iLr1 t 4   Cr1vCr1 t 4  sint 4  (19)
vCr1 t   sin t  (8)
Cr1 vLr2 is equal to Vo/4, and iLr2 decreases linearly.
At t=t2, iLr2 becomes zero as it transfers all its energy to the Vo
i Lr 2 t   iLr 2 t 5   t (20)
resonant capacitor. 4 Lr
iLr 2 t 2   0 (9) V
i Lr1 t   i Lr1 t 5   o t (21)
4 Lr
From this final state condition, t02 can be found as
 Operation interval 8 [t6 ≤ t < t7]: This interval starts after the
t 02  (10) main switch S2 is turned on. At t=t6, the main switch S2 is
2 turned on while its body diode is conducting. The zero-
Operation interval 4 [t2 ≤ t < t3]: At t=t2, the resonant voltage-transition can be achieved at this instant. With the
inductor current iLr1 is same as iLr2(t0). The resonant capacitor assumption of negligible t45 in comparison to t56, t46  t56; the
voltage can be found from the energy transfer between vcr1 and ZVT time interval can be expressed as
iLr2 as 4 Lr  iLr 2  t6   iLr 2  t5  
2 Lr t56  (22)
vCr1  t2   iLr 2 2  t0  (11) Vo
Cr1
First, the current of the body diode of S2 reaches to zero. In
The energy stored in vcr1 will be used to achieve soft-switching this time interval, S2 begins to conduct, and input current
in latter stage. In this time interval, the resonant inductor commutes from Lr1 to Lr2. At t=t6, iLr1 is
current iLr1 can be written as V
 V / 2  Vin  iLr1 t6   iLr1 t5   o t56 (23)
iLr1  t   iLr1  t2    o 4 Lr
t (12)
 Lin  Lr  The resonant inductor currents for this interval can be
expressed as
IEEE Transactions on Industrial Electronics 5

Vo t67 = DLTS
i Lr1 t   i Lr1 t 6   t (24) tdt=0 t45
4 Lr
Fixed Dead-time
V Vgs2
i Lr 2 t   i Lr 2 t 6   o t (25) Vgsa1
4 Lr
At t=t7, the input current commutation from Lr1 to Lr2 is Is1
completed, and iLr1 becomes zero. This time interval can be
expressed as Is2
4 Lr  iLr 2  t7   iLr 2  t6  
tm
(a)
t67  (26)
Vo t45
tm=0
III. DESIGN CONSIDERATIONS FOR ZVT FEATURE Variable Dead-time Control
Vgs2
The time between the turning-off action of Sa1 and turning- Vga
on action of the main switch S2, denoted by t46, should be as
short as possible to achieve ZVT with smallest amount of Is1
energy stored in the resonance tank. This would minimize the
Is2
size of the resonant tank elements and allows achieving higher t67 = DLTS
efficiency as the circulating current in the resonant tank would (b) tdt
be less. To achieve ZVT, the auxiliary switch should be turned Fig. 4. Illustration of ZVT operation with fixed and variable dead-times for
on at least t36 before the main switch is turned on. It should be evaluation of t67; (a) fixed dead time, (b) variable dead-time.
highlighted that t34 is the time duration in which the stored
energy in the auxiliary capacitor is transferred to the auxiliary 2 Lr
inductor, t45 is the time required to discharge the parasitic vcr1  t2   iLr 2  t0  (30)
Cr1
capacitance of the switch. For ideal case, the minimum
required time is t35. t56 is the time duration added to guarantee B. Variable Power Loads:
the soft-switching of the main switch taking the mismatch From Eq. (27), it can be observed that the ZVT feature is
between the actual and datasheet values of the switch. dependent on the load current as it determines the stored
Considering this added time margin, the auxiliary switch energy in the resonant inductor. Therefore, for wide load range
should be turned on at least t36 before the main switch is applications, the minimum input current at which ZVT feature
turned on. Once t46 is determined, Lr can be calculated is desired should be determined for the given application.
accordingly.
tZVS  tdt  tm (31)
A. Constant Power Loads:
where, tdt denotes the selected dead-time, and tm is the time
The minimum value of Lr can be determined for constant
margin, representing the time from turn-on instant of the main
power loads with predefined Po, Vo, Vin, Lin, and steady-state switch till iLr2 becomes zero, and should be included in the
duty ratio (D). For simplicity in calculations, it is assumed that calculations ensuring that the switch is switched under zero-
iLr2 does not vary during t45, and |iLr2(t5)|=|iLr2(t0)|, which yields
voltage. Minimum Lr for variable power loads can be
to
determined as
Vo
Lr  t 46 (27) Vo
4iL r 2 t0  Lr  t ZVT (32)
4iL r 2 t0 
In order to have zero voltage across Cr1 from t=t4 to t=t0, the In case the auxiliary switch is turned off tdt seconds before the
reverse resonance time, t34, should be equal to the one fourth
main switch is turned on, D1 would conduct for the time
of the natural resonance period, t02, which is initiated by
duration of tZVT.
turning on Sa1. If t34 is forced to be shorter than t02, vCr1(t0)
The selected Lr should be sufficiently large to achieve soft-
would be higher than zero. Cr1 can be calculated from Eq. (5) switching for S2 at minimum load current. However, the
and Eq. (10), by equalizing t34 and t02 time periods, as selected Lr would cause losing effective on-time of the switch
2
Cr 1  t 02
2
(28) as the load gets heavier. This issue has been illustrated in Fig.
Lr  2 4(a). Here, it is assumed that the load current is larger than
Since two quarter resonance periods take place during the off- I_min, and Lr is found using Eq. (27) for the ideal case,
time of the switch, the sum of them should be shorter than (1- assuming tdt=0. As it can be seen from the figure, the
D)Ts, where Ts represents the switching period. reduction in the duty ratio, denoted by DL, increases under
Ts 1  D  heavy load. The reduction in the duty cycle should be
t 02  (29)
2 compensated similar to dead-time compensation applied in
As the quarter resonance period t02 increases, the required three-phase inverters [28]. To reduce this effect, the phase of
capacitance also increases while the voltage stress on S2 the gating signal of the auxiliary switch should be varied such
reduces. The additional voltage stress across S2 is equal to that that the main switch is turned on right before the current of the
of vcr1(t2), and can be expressed as main switches body diode reaches to zero.
In this regard, a variable dead-time control is proposed in
this paper, as shown in Fig. 4(b). The gating signals for the
IEEE Transactions on Industrial Electronics 6

Table II. Design Parameters several nanoseconds. The variation of t45 at minimum load
Output Power (Po) 650W-250W current according to Lr is plotted in Fig. 5(a) for maximum and
Output Voltage (Vo) 200V-180V minimum output voltages. As the output voltage increases,
Input Voltage (Vin) 100V
more energy is stored in the parasitic capacitances of the
Input Inductor (Lin) 100µH
Switch Parasitic Capacitance (Coss) 120pF switches, which extends the discharge time to 5 ns. At
Switching Frequency 200kHz Po=250W, the dead-time, tdt, is chosen as 30 ns. This would be
5 ns for ideal case; however, it is reasonable to insert a dead-
Table III. Acquired Data for ZVT Operation time to ensure that soft-switching will be robust to the
Vo,min Vo,min Vo,max Vo,max mismatch of the actual and datasheet values as well as to
Po,min Po,max Po,min Po,max compensate the previous simplifications. Since the switching
t57/2 [ns] 55 145 50 130
D [%] 44 44 50 50 period is 5 µs and considering the turn-on and turn-off time of
Fixed Dead-time MOSFETs, tm is chosen as 20 ns to ensure the auxiliary switch
tdt [ns] 30 30 30 30 turns off 30 ns before the main switch is turned on. In this
t67 [ns] 80 260 70 230 way, the resonant current will become zero after tm+tdt=50 ns.
DL [%] 3.6 11.6 2.8 9.2
The ZVT time period corresponds to 1% of the switching
Variable Dead-time
tdt [ns] 35 125 30 110 period. The reduction in the duty cycle, t67/DTs, can be
t67 [ns] 75 165 70 150 expressed as
DL [%] 3.4 7.4 2.8 6
DL 
 tdt  2tm 
(33)
DTs
auxiliary switches are practically achieved by right-aligned
pulse-width-modulation (PWM) signal with inserted fixed To find Lr, worst condition should be considered; that is
dead-time. At heavy loads, instead of turning off the auxiliary Po=Po,min and Vo=Vo,max. Assuming that Lin is large enough and
switch with fixed tdt seconds, before the main switch is turned input current is constant, iLr2(t0) in Eq. (32) can be
on, the discharging of resonant capacitor can be initiated approximately equal to the input current. For this example, Lr
earlier by adjusting the dead-time between the main and is calculated as 1 µH. The highest ZVT time, t57/2, is 50 ns for
auxiliary switch signals. Hence, the resonant inductor current minimum load at Vo=Vo,max. At maximum load, the ZVT
crosses zero tm seconds after the main switch is turned on. At period increases to 130 ns. For Vo=Vo,min, the ZVT period for
ideal case, tm=0, this could reduce DL to DL/2 as illustrated in minimum load is 55 ns, and at maximum output power it
Fig. 4(b). increases up to 145 ns. The same amount of time is required
It is important note that the proposed variable dead-time for the main switch current to reach to the input current, t57/2.
approach can be used for achieving supplementary control For a fixed tdt of 30 ns, t67 can be calculated using t57-tdt as 70
objectives such as dc link capacitor voltage balancing. The ns and 230 ns for lightest and heaviest load conditions at
variable dead-time has not been considered in any soft- Vo=Vo,max, respectively. Similarly, when Vo=Vo,min, t67 becomes
switching literature because it may not be necessary in two- 80 ns and 260 ns for lightest and heaviest load conditions,
level converters. One of the difficulties in three-level respectively.
converters is the unbalanced dc link capacitor voltages, which In CCM mode, the duty ratios for Vo=Vo,min and Vo=Vo,max
may occur due to the unsymmetrical circuit layout, differences are 44% (corresponding to 2.22 µs) and 50% (corresponding
in the ESR of capacitors, delays in the gate driver circuit, etc. to 2.5 µs). Using Eq. (33), DL is calculated as 3.6% and 11.6%
The unbalanced voltage problem could be solved by for light and heavy load conditions at Vo=Vo,min, respectively.
controlling the duty cycles of the main switches Similarly, for Vo=Vo,max it is calculated as 2.8% and 9.6%,
independently, letting capacitors charge/discharge more or less respectively. Using the proposed variable dead- time
with respect to the other dc link capacitor. However, the approach, DL can be reduced effectively as shown in Fig. 5(b).
common approach is to use the same PWM duty cycle The dead-time curve used to accomplish DL reduction is given
generator for both of the switches due to its simple control and in Fig. 5(c).
more importantly for stable operation. In this regard, The acquired data is summarized in Table III. It can be seen
developed secondary variable dead-time control can be that DL is reduced from 11.6% to 7.4% for low output voltage
adopted to balance the dc link capacitors as well as contribute and heavy load conditions. If tm is chosen smaller at the initial
to the duty cycle compensation, correcting the unbalanced step, DL can be reduced even further, to half of DL value with
ZVT current injection due to unsymmetrical ZVT circuit fixed dead-time at ideal case, when tm=0. However, further
parameters and so on. However, in this paper, only partial duty duty cycle compensation is still required.
cycle compensation has been studied and capacitor voltage Once tdt and Lr are determined, Cr can be determined from
balancing is out of the scope of the paper. Eq. (28) and Eq. (29). As mentioned before, the pulse-width of
C. Example Application Sa1 should be equal to t02 to have zero voltage across vcr at t=t0.
When a dead-time is inserted, Eq. (29) should be modified to
This section provides a ZVT cell design procedure for a
incorporate tdt.
variable power load. The example design specifications are
provided in Table II. The converter operates in CCM at full
Ts 1  D 
load range. t02   tdt (34)
The first design parameter to be determined is the tZVT. As 2
discussed previously, t45 is relatively short, in the order of
IEEE Transactions on Industrial Electronics 7

6 12 dtc:dead time 140 dtc:dead time

compensation compensation

Discharge Time of Parasitic

120
10

Required dead-time [ns]

∆Duty Cycle (DL) [%]
Vo,max Vo,max(w/o dtc) 100
Switch, t45 [ns]
5 Vo,min(w/o dtc) Vo,min(with dtc)
8 80

6 60
Vo,min
4
40 Vo,max(with dtc)
4 Vo,max(with dtc) 20
Vo,min(with dtc)
3 2 0
0 0.5 1.0 1.5 2.0 2.5 250 300 350 400 450 500 550 600 100 200 300 400 500 600
Lr [µH] Output Power [W] Output Power [W]
(a) (b) (c)
Fig. 5. Curves for the ZVT operation; (a) Switch parasitic capacitance discharge time according to various Lr, (b) reduction in effective duty ratio for various
output powers when Lr=1 µH, (c) required dead-time for the proposed variable dead-time control at various output powers.

250 Table IV. Component Parameters

200
Hard-Switched Three- Soft-Switched Three-
160 200 Level Converter Level Converter
Main switch FQPF16N25 FQPF16N25
120 150 S2&S3
VCr [V]

Cr [nF]
250V/9.5A 250V/9.5A
Aux switch FQPF6N25
80 100 Sa1&Sa2 -
250V/4A
D1&D4 Body Diodes Body Diodes
40 50
Lin 100uH 100uH
0 0 Co 470uF x 2 470uF x 2
300 500 700 900 1100
t02 [ns] Lr - 1uH x 4

Fig. 6. Capacitance and voltage stress variation of the resonant capacitor at Cr - 100nF x2
various t02 values.
capacitor voltage is almost zero. The simulation waveforms
The highest tdt is achieved when output power is maximum, agree with the theoretical analysis.
and output voltage is lowest. However, for this case, Ts(1- The simulation waveforms for boost operation utilizing
D)/2-tdt for Vo=Vo,max condition is smaller; hence, t02 should be non-ideal switches when d=0.4, are presented in Fig. 7(c).
determined based on maximum output voltage. This From the figures, it can be clearly seen that Coss of the
determines the upper bound for choosing t02, which is switches, particularly that of the auxiliary switches, causes to
calculated as 1.14 µs. The variation of capacitance value and form a resonant tank between Lr - Lr - Cr - Coss. Without
voltage stress of resonant capacitor for various t02 from 0.1 µs including the internal resistances, this oscillation keeps
– 1.14 µs, is given for heaviest load condition in Fig. 6. Here, circulating back and forth. As seen from the input inductor
Cr can be determined based on the tradeoff between the voltage, this oscillation causes inductor current to have a small
capacitance value and the voltage stress. In addition, there oscillating current in addition to the linearly increasing
should be sufficient margin for duty cycle compensation. Once current.
t02 is determined, the duty ratio of Sa1 can be found by dividing A 650W proof-of-concept prototype, shown in Fig 8, is
t02 by Ts. designed to serve as a proof-of-concept and to show ZVT
IV. SIMULATION AND EXPERIMENTAL RESULTS operation of the circuit. The circuit parameters are same as of
the simulation. The current ratings of the switches are chosen
In this section, simulation and experimental results are
based on the rms value. As the ZVT circuit does not impose
provided to verify the operation of the converter. The
additional current stress on the main switches, the main switch
switching frequency of the main and auxiliary switches is 200
rms current can be found as in traditional three-level converter
kHz, where the frequency of the inductor and output capacitor
[10]. The voltage rating of the main switches is the sum of the
current ripples is 400 kHz. The resonant inductors, Lr, are 1
half of the output voltage and the resonant capacitor voltage,
µH and the resonant capacitors, Cr, are 100 nF each. Only
which was given in Eq. (30). It can be expressed as
boost operation mode is presented in here, as buck operation is
Vo 2 Lr
similar to boost operation. Vmain   iLr 2  t0  (35)
The simulation waveforms for d=0.53 and d=0.4 using 2 Cr1
ideal switches are given in Fig. 7(a) and Fig. 7(b), On the other hand, the current rating of the auxiliary switch
respectively. In boost operation only S2 and S3 are switched is equal to
while body diodes of S1 and S4 conduct. The additional voltage  fs
stress on the main switches can be clearly observed. The duty I aux  iLr 2  t0  (36)
2
ratio of the auxiliary switch calculated from the analysis match
with one fourth of the resonant period, such that the resonant
IEEE Transactions on Industrial Electronics 8

Gate Voltages of S2-S3 [V] Gate Voltages of S2-S3 [V] Gate Voltages of S2-S3 [V]
S2 S2 S2
15 S3 15 S3 15 S3

0 0 0
Gate Voltages of Sa1-Sa2 [V] Gate Voltages of Sa1-Sa2 [V] Gate Voltages of Sa1-Sa2 [V]
Sa1 Sa1 Sa1
Sa2 Sa2 Sa2
15 15 15

0 0 0
S2 Drain-Source Voltage-Current S2 Drain-Source Voltage-Current [V] S2 Drain-Source Voltage-Current [A]
[V] [A] [V] [A] 120
ids2 12 100 12
120 ids2 10 ids2
vds2 8 vds2 80 vds2 8
80 60 6 40 4
40 4 20 2 0 0
0 0 -20 -2 -40 -4
-40 -4 -60 -6 -80 -8
[V] S3 Drain-Source Voltage-Current [A] [V] S3 Drain-Source Voltage-Current [A] [V] S3 Drain-Source Voltage-Current [A]
120 ids3 12 100 ids3 10 ids3
80 vds3 8 vds3 80 vds3 8
60 6
40 4 20 40 4
2
0 0 -20 0 0
0
-2 -40 -4
-40 -4
-60 -6 -80 -8
[V] Resonant Capacitor Voltage-Current [A] [V] Resonant Capacitor Voltage-Current [A] [V] Resonant Capacitor Voltage-Current [A]
icr1 icr2 icr1 4 icr1
20 vcr1 vcr2 4 20 v 20 vcr1 4
cr1

0 0 0 0 0 0
-20 -4 -20 -4 -20 -4
Auxiliary Switch Voltages [V] Auxiliary Switch Voltages [V] Auxiliary Switch Voltages [V]
vdsa2 80 vdsa2 80 vdsa2
vdsa1 vdsa1 vdsa1
80 60 60
40 40 40
20 20
0 0 0
Inductor Voltage [V] Inductor Voltage [V] Inductor Voltage [V]
40
20
40
0 0
20
-20
0
-40 -40
-20
-60
-40
-80 -80
Inductor Current [A] Inductor Current [A] Inductor Current [A]
5.0 5.7 5.6
4.8 5.5
4.6 5.4
5.4
4.4 5.2
4.2 5.3
4.0 5.2 2 4 6 8 10 5.0
0 2 4 6 8 10 0 0 2 4 6 8 10
Time [µs] Time [µs] Time [µs]
(a) (b) (c)
Fig. 7. Simulation waveforms for boost operation mode; (a) d=0.53 with ideal switches, (b) d=0.4 with ideal switches, (c) d=0.4 with non-ideal switches.

The component parameters used in the experiments are
given in Table IV. Fig. 9 presents the input inductor current
waveform and gate-source voltages of S2 and S3. This figure
illustrates the boost mode operation of the three-level
converter, where the current ripple frequency is twice of the
switching frequency.
The ZVT operation of the converter has been presented in
the experimental results provided in Figs. (10)-(11). Fig. 10
presents the ZVT operation during boost mode of operation
for d<0.5 under low current. The peak value of IS2 is
approximately 2.2A. As depicted before, the auxiliary switch
is turned on before the main switch is turned on to conduct the
body diode of the main switch. The ZVT can be clearly
observed from Fig. 10(b). In Fig. 10(c), auxiliary current and
voltage waveforms are presented, from which ZCS operation
can be clearly seen. The experimental waveforms are agrees
with the simulation results presented in Fig. 7(c). Different
than simulation, the oscillations are damped due to the internal
resistances of the components in the experiments. Likewise,
ZVT operation for boost mode for d<0.5 under higher current
(peak switch current of 4A) profile is given in Fig. 11.
It should be noted that the proposed ZVT cell causes some
undesirable oscillations on the drain-source voltage as well as
the current of the main switches. These oscillations are due to
output parasitic capacitance of the auxiliary switches, Coss. In
the experiments, a low Coss switch with rated Coss of 140pF at
Vds=200V is utilized to minimize the oscillation amplitude and
increase the resonance frequency. Yet, these oscillations are
inevitable as there is Lr - Lr - Cr - Coss resonant network.
Meantime, half of the output voltage is equal to the sum of Vs1,
Vs2, Vcr1, and Vsa1. Therefore, any oscillation within the
resonant network affects the switch voltage and current
waveforms. Nevertheless, this energy keeps oscillating back
and forth until it is damped by the internal resistances of the
resonant tank components.
The equivalent capacitance involving in the oscillations is
equal to (Cr*Coss)/(Cr+Coss), which makes it close to the value
IEEE Transactions on Industrial Electronics 9

vDS2 iS2

vGS2
vGSa1

Fig. 8. Photo of the designed experimental prototype.

(a)

iL

vDS2 iS2
vGS3 vGS2

vGSa1 vGS2
ZVT

(a)

(b)

vDSa1

iSa1

vGS2
vGSa1
(b)
Fig. 9. Experimental waveforms of normal boost operation; gate-source
voltages S2 and S3, and inductor current for, a) d<0.5, b) d>0.5.

of Coss. The energy stored in Coss, starts to resonate.

Considering its capacitance, the stored energy is very small.
The voltage of Cr, which can be observed from the additional
voltage stress on the main switches, remains almost the same
between charging and discharging instants of Cr, which also
shows that energy is conserved and not wasted. This can also
be observed from the auxiliary switch current given in Fig. 10
(c), and Fig. 11 (c), which is same as the resonant capacitor
current. The peak values of the resonant capacitor current are
same for charging and discharging instants. This also verifies
that this oscillation does not cause significant power loss.
Consequently, it can be concluded as this oscillation 1) does
not create any additional voltage stress on the components, 2)
causes very small current stress on the inductors and switches,
3) the circulating energy is very small, yet, most of it is not
wasted.
In addition, the very high frequency oscillation observed on
(c)
Fig. 10. Experimental waveforms of ZVT operation boost mode when d<0.5
(low current); (a) gate-source and drain-source voltages and current of S2, and
gate-source voltage of Sa1 for two switching periods, (b) zoom-in snapshot, c)
gate-source and drain-source voltages and current of Sa1, and gate-source
voltage of S2.
the gate signals is due to the high parasitic capacitance of the
differential probe. Since the grounds of the probes should be
isolated, a regular and a differential voltage probe are used for
sensing gates of the signals. To prove this claim, the regular
and differential probes have been connected to the gate-source
terminal of S2 (purple waveform) and Sa1 (green waveform) in
Fig. 10(b), respectively. As it can be seen, the very high
frequency oscillations are only on the Sa1 gate signal. In Fig.
10(c), these two probes are replaced. This time, the
oscillations are observed on the S2 gate signal. Thus, the high
IEEE Transactions on Industrial Electronics 10

96 Soft-switched
Vo=180V
vDS2 iS2 94

Efficiency [%]
92 Vo=220V
vGSa1 vGS2
90
Vo=180V
Hard-switched
88

(a) 86
100 200 300 400 500 600 700
Output Power [W]
Fig. 12. Efficiency curve of; a) proposed topology at Vo=180V and Vo=220V,
vDS2 iS2 b) hard-switched three-level converter.

Table V. Loss Comparison of Hard-Switched and Soft-Switched Converters at

Vo=180V and Po=650W

Hard-Switched Three- Soft-Switched Three-

vGSa1 ZVT vGS2 Level Converter Level Converter
Pswt [W] Pcon [W] Pswt [W] Pcon [W]
Main switch
38 5 8.1 5.3
S2&S3
Aux switch
- - 3.2 2.8
Sa1&Sa2
(b) D1&D4 - 12 - 12.6

vDSa1 counterparts. In addition, it should be noted that the proposed

iSa1
vGSa1 vGS2
(c)
Fig. 11. Experimental waveforms of ZVT operation boost mode when d<0.5
(high current); (a) gate-source and drain-source voltages and current of S2, and
gate-source voltage of Sa1 for two switching periods, (b) zoom-in snapshot, c)
gate-source and drain-source voltages and current of Sa1, and gate-source
voltage of S2.
frequency oscillations on the gate signals are completely due
to the differential probe parasitics.
The efficiency curves for two different output voltage
levels, along with hard-switched converter efficiency, are
presented in Fig. 12. It can be seen that the designed prototype
exhibits 95.5% at full load, while the peak efficiency of hard-
switched converter is 91%. The individual losses of
semiconductors are presented in Table V. Considering the
typical efficiencies of industrial non-isolated bidirectional
dc/dc converters, which are between 90-95%, the proposed
ZVT converter provides competitive efficiency to its
ZVT converter inherently reduces the required input boost
inductance and output filter capacitance by half due to the
three-level structure, in comparison to the state-of-the-art
converters. Moreover, it allows using low-voltage rated
switched.
V. CONCLUSION
In this paper, a ZVT bidirectional TL dc/dc converter,
employing two identical ZVT cells to fully soft-switch all four
switches in bidirectional power flow during turning on instants
of the main switches, is introduced. The design procedures of
the ZVT cell components are provided. Furthermore, an
actively controlled variable dead-time approach has been
introduced to minimize the reduction in the duty ratio due to
the soft-switching period, during converter’s operation under
heavy loads. A 650W prototype has been designed to
demonstrate the operation of the converter. The peak
efficiency at 200 kHz switching frequency is recorded as
95.5%.
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Serkan Dusmez (S’11) received the B.S.
(Hons) and M.S. degrees in electrical
engineering from Yildiz Technical
University, Istanbul, Turkey, in 2009 and
2011, respectively. He received the M.S.
degree in electrical engineering from Illinois
Institute of Technology, Chicago, in 2013. He
is currently working toward the Ph.D. degree
at the University of Texas at Dallas.
From 2012-2013, he worked as a Faculty
Research Assistant in the Power Electronics,
Energy Harvesting and Renewable Energies
Laboratory (PEHREL) in the Electrical and
Computer Engineering Department at the University of Maryland at
College Park. He is the author/co-author of over 35 journal and conference
papers. His research interests include design of power electronic interfaces
and energy management strategies for renewable energy sources, integrated
power electronic converters for plug-in electric vehicles, and real-time fault
diagnosis of power converters.
Alireza Khaligh (S’04–M’06–SM’09) is
an Assistant Professor at the Electrical and
Computer Engineering (ECE) Department
and the Institute for Systems Research in
the University of Maryland. He is an
author/coauthor of over 120 journal and
conference papers.
Dr. Khaligh is the recipient of various
awards and recognitions including the
2013 George Corcoran Memorial Award
from the ECE Department of the
University of Maryland, 2013 and 2012
Best Vehicular Electronics Awards from
the IEEE Vehicular Technology Society
(VTS), and 2010 Ralph R. Teetor Educational Award from the Society of
Automotive Engineers. He is the Program Chair of the 2015 IEEE Applied
Power Electronics Conference and Exposition. He was the General Chair
of the 2013 IEEE Transportation Electrification Conference and
Exposition, and Program Chair of the 2011 IEEE Vehicle Power and
Propulsion Conference. He is an Editor or an Associate Editor for various
IEEE Transactions and Journals. He is an IEEE VTS Distinguished
Lecturer.