HARDWARE DESCRIPTION LANGUAGE

UNDER THE GUIDANCE OF: SUBMITTED BY:

- DR. SIVA KUMAR TADEPALLI Krishankant Mani
BT17ECE040
S NO. EXPERIMENT DATE REMARKS
NAME

1. 1 BIT 8-09-2019
COMPARATOR

2. 1 BIT 8-09-2019
ADDER(HALF
ADDER)
3. 2 BIT ADDER 8-09-2019
(FULL ADDER

4. FULL ADDER 8-09-2019

USING
HALF ADDER
5. 2 x 1 MUX 8-09-2019

6. 4 BIT BINARY 8-09-2019

COUNTER
 Experiment No. 1
AIM : To design one bit comparator using Verilog

SOFTWARE USED : Icarus iverilog , GTKWave,command

prompt for compilation

CODE :
Using gate level modelling:

module b_comp1 (a, b, L, G,E);

input a, b;
output L, E, G;
wire s1, s2;
not X1(s1, a);
not X2 (s2, b);
and X3 (L,s1, b);
and X4 (G,s2, a);
xnor X5 (E, a, b);
endmodule
TESTBENCH:
module try;
reg x,y;
wire l,g,e;
b_comp1 cmp(x,y,l,g,e);
always@(l or g or e)
begin
$monitor("x=%d,y=%d,l=%d,g=%d,e=%d\n",x,y,l,g,e);
end
initial
begin
$dumpfile("exp.vcd");
$dumpvars ;
x=0; y=0;
#4 x=0 ; y=1;
#4 x=1; y=0;
#4 x=1; y=1;
end
endmodule

OUTPUT :
RESULT: thus waveform for 1 bit comparator is verified .
 EXPERIMENT NO 2

AIM : To Design half adder using Verilog.

SOFTWARE USED : Icarus iverilog , GTKWave,command prompt for
compilation
CODE :
module half_adder(a,b,s,c);
input a,b;
output s,c;
xor (s,a,b);
and (c,a,b);
endmodule

TESTBENCH :
module try_half;
reg x,y;
wire c,s;
half_adder hf(x,y,s,c);
always@(s or c)
begin
$monitor("x=%d,y=%d,c=%d,s=%d",x,y,c,s);
end
initial
begin
$dumpfile("exp1.vcd");
$dumpvars;
x=0; y=0;
#4 x=0; y=1;
#4 x=1; y=0;
#4 x=1; y=1;
end
endmodule

OUTPUT:
RESULT: thus waveform for half adder is verified.
 EXPERIMENT 3
AIM: To design full adder using Verilog
SOFTWARE USED : Icarus iverilog , GTKWave,command prompt
for compilation
CODE:
module full_adder(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire s,cout;
assign s = a^b^cin;
assign cout =((a&b)|(b&cin)|(a&cin));
endmodule

TESTBENCH :
module try_full;
reg a,b,c;
wire s,cout;
full_adder fl(a,b,c,s,cout);
always@(s or cout)
begin
$monitor("a=%d,b=%d,c=%d,s=%d,cout=%d",a,b,c,s,cout);
end
initial
begin
$dumpfile("exp3.vcd");
$dumpvars;
a=0; b=0; c=0;
#3 a=0; b=0; c=1;
#3 a=0; b=1; c=0;
#3 a=1; b=0; c=1;
#3 a=1 ;b=1 ; c=1;
end
endmodule

OUTPUT:
RESULT: thus waveform for full adder is verified
 EXPERIMENT 4
AIM: To design full adder using half adder in verilog.
SOFTWARE USED : Icarus iverilog , GTKWave,command prompt for
compilation
CODE :
module full_adder_using_half_adder(input a, input b, input cin, output
sum, output cout);
wire ha1_c , ha1_s , ha2_c , ha2_s, sum , cout;
half_adder ha1 (a, b, ha1_s, ha1_c);
half_adder ha2 (cin, ha1_s,sum, ha2_c);
or(cout, ha2_c, ha1_c);
endmodule
module half_adder(a,b,s,c);
input a,b;
output s,c;
xor (s,a,b);
and (c,a,b);
endmodule

TESTBENCH :
module try4;
reg a, b, c;
wire sum, cout;
full_adder_using_half_adder fuh(a, b, c, sum, cout);
always@(sum or cout)
begin
$monitor("a=%d,b=%d,c=%d,sum=%d,cout=%d\n" , a , b , c , sum ,
cout);
end
initial
begin
$dumpfile("exp4.vcd");
$dumpvars;
a = 0; b = 0; c = 0;
#4 a= 0; b = 0; c = 1;
#4 a= 0; b = 1; c = 0;
#4 a =0; b = 1; c = 1;
#4 a =1; b = 0; c = 0;
#4 a =1; b = 0; c = 1;
#4 a =1; b= 1; c = 0;
#4 a =1; b = 1; c = 1;
end
endmodule
OUTPUT:

RESULT: thus the waveform for full adder using half adder is verified.
 EXPERIMENT 5
AIM : To design 2x1 Multiplexer in Verilog.
SOFTWARE USED : Icarus iverilog , GTKWave,command prompt for
compilation
CODE:
module mux2to1(in_0,in_1,sel,out);
input in_0;
input in_1;
input sel;
output out;
reg out;
always @(in_0,in_1,sel)
begin
if(sel == 0)
out = in_0;
else
out = in_1;
end
endmodule

module try_mux;
reg a,b,s;
TESTBENCH:
wire y;
mux2to1 tm(a, b, s, y);
always@(y)
begin
$monitor("a=%d,b=%d,s=%d,y=%d\n" , a , b , s , y);
end
initial
begin
$dumpfile("exp5.vcd");
$dumpvars;
a = 0; b = 0; s = 0;
#4 a = 0; b = 0; s = 1;
#4 a = 0; b = 1; s = 0;
#4 a = 0; b = 1; s = 1;
#4 a = 1; b = 0; s = 0;
#4 a = 1; b = 0; s = 1;
#4 a = 1; b = 1; s = 0;
#4 a = 1; b = 1; s = 1;
end
endmodule
RESULT: thus the waveform for 2x1 mux is verified.
 EXPERIMENT 6
AIM: To design 4 bit binary counter in Verilog
SOFTWARE USED :Icarus iverilog , GTKWave,command
prompt for compilation
CODE:
module binary_counter(input clk, input rstn, output reg[3:0] out);
always@(posedge(clk)) begin

if(!rstn)
out<= 0;
else
out<= out + 1;
end
endmodule

TESTBENCH:
module try_binary_counter;
reg clk;
reg rstn;
wire [3:0] out;
binary_counter bc(clk, rstn, out);
always #5 clk = ~clk;
initial
begin
$dumpfile("exp6.vcd");
$dumpvars;
clk<= 0;
rstn<= 0;
#10 rstn<= 1;
#20 rstn<= 0;
#40 rstn<= 1;
#60 $finish;
end
endmodule

OUTPUT:
RESULT: thus waveform for 4 bit binary counter is verified.