EXPERIMENT No.

5
2/3 BIT BINARY COMPARATOR

AIM: To design, setup and verify the truth table of 2/3 bit magnitude
comparator.
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7404, 7408, 7486 and 7432) and connecting wires
THEORY: A 2-bit comparator compares two binary numbers, each of two bits
and produces their relation such as one number is equal or greater than or less
than the other. The figure below shows the block diagram of a two-bit
comparator which has four inputs and three outputs. The first number A is
designated as A = A1A0 and the second number is designated as B = B1B0.
This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B)
and L (L = 1 if A<B).

The truth table of this comparator is shown below.

The k-map simplification for the above truth table is as follows.

From the above k-map simplification, each output can be expressed as

LOGIC DIAGRAM

RESULT: Designed, set up and verified the truth tables of 2/3 bit binary
comparator.
 EXPERIMENT No. 6
BINRY TO GRAY AND GRAY TO BINARY CONVERTERS

AIM: To design, setup and verify the truth tables of

a) 4 bit binary to gray converter
b) 4 bit gray to binary converter
c) 3 bit binary to gray/gray to binary converter using mode control
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7486, 7408) and connecting wires
THEORY:

a) 4 bit Binary to Gray Converter

b) 4 bit Gray to Binary Converter
PROCEDURE:
1. The circuit connections are made as shown in fig.
2. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3
are given at respective pins and outputs G0, G1, G2, G3 are taken for all
the 16 combinations of the input.
3. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3
are given at respective pins and outputs B0, B1, B2, and B3 are taken
for all the 16 combinations of the input.
4. In the case of binary to gray/gray to binary conversion, an additional
mode control input is used. When M=0, the circuit behaves as a binary
to gray converter and when M=1, the circuit behaves as a gray to binary
converter.
RESULT: Designed, set up and verified the truth tables of
a) 4 bit binary to gray converter
b) 4 bit gray to binary converter
c) 3 bit binary to gray/gray to binary converter using mode control
 EXPERIMENT No. 7
STUDY OF FLIP-FLOPS

AIM: To design, setup and verify the truth tables of following flip-flops.
a) SR flip-flop
b) JK flip-flop
c) D flip-flop
d) T flip-flop
e) Master Slave JK flip-flop
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7404 and 7400) and connecting wires
THEORY:
a) SR flip-flop

b) JK flip-flop
c) D flip-flop

d) T flip-flop
 e) Master Slave JK flip-flop

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.
RESULT:
Designed, setup and verified the truth tables of SR flip-flop, JK flip-flop, D flip-
flop, T flip-flop and Master Slave JK flip-flop.
 EXPERIMENT No. 8
4 BIT ASYNCHRONOUS COUNTERS

AIM: To design, setup and verify the truth tables of a) 4 bit asynchronous up
counter b) 4 bit asynchronous down counter
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7476) and connecting wires
THEORY:
Asynchronous counters are those whose output is free from the clock signal.
Because the flip flops in asynchronous counters are supplied with different
clock signals, there may be delay in producing output. The required number of
logic gates to design asynchronous counters is very less. So they are simple in
design. Another name for Asynchronous counters is “Ripple counters”. The
number of flip flops used in a ripple counter is depends up on the number of
states of counter (ex: Mod 4, Mod 2 etc). The number of output states of counter
is called “Modulus” or “MOD” of the counter. The maximum number of states
that a counter can have is 2n where n represents the number of flip flops used in
counter.
a) 4 Bit Asynchronous Up Counter
b) 4 Bit Asynchronous Up Counter

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

RESULT:
Designed setup and verified the truth tables 4 bit asynchronous up and down
counters.
 EXPERIMENT No. 9
Mod-N ASYNCHRONOUS COUNTERS

AIM: To design, setup and verify the truth tables of a) Asynchronous decade
counter b) Mod-12 asynchronous counter
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7476 and 7400) and connecting wires
THEORY:
An Asynchronous counter can have 2n-1 possible counting states e.g. MOD-16
for a 4-bit counter, (0-15) making it ideal for use in Frequency Division
applications. But it is also possible to use the basic asynchronous counter
configuration to construct special counters with counting states less than their
maximum output number. For example, modulo or MOD counters.
A decade counter requires resetting to zero when the output count reaches the
decimal value of 10, ie. when DCBA = 1010 and to do this we need to feed this
condition back to the reset input. A counter with a count sequence from binary
“0000” (BCD = “0”) through to “1001” (BCD = “9”) is generally referred to as
a BCD binary-coded-decimal counter because its ten state sequence is that of a
BCD code but binary decade counters are more common.
a) Asynchronous Decade Counter
 b) Mod-12 Asynchronous Counter

RESULT:
Designed, setup and verified the truth tables of asynchronous decade counter
and mod-12 counters.
 EXPERIMENT No. 10
3 BIT UP/DOWN ASYNCHRONOUS COUNTERS

AIM: To design, setup and verify the truth table of 3 bit Asynchronous
up/down counter
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7476, 7408 and 7432) and connecting wires
THEORY:

RESULT:
Designed, setup and verified the truth table of asynchronous up/down counter
using mode control.
 EXPERIMENT No. 11
SYNCHRONOUS COUNTERS

AIM: To design, setup and verify the truth tables of 4 bit synchronous up and
down counters.
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7476 and 7408 ) and connecting wires
THEORY:
With the Synchronous Counter, the external clock signal is connected to the
clock input of EVERY individual flip-flop within the counter so that all of the
flip-flops are clocked together simultaneously (in parallel) at the same time
giving a fixed time relationship. In other words, changes in the output occur in
“synchronisation” with the clock signal. The result of this synchronisation is
that all the individual output bits changing state at exactly the same time in
response to the common clock signal with no ripple effect and therefore, no
propagation delay.
a) 4 Bit Synchronous Up Counter

b) 4 Bit Synchronous Down Counter

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

RESULT:
Designed, setup and verified the truth tables 4 bit synchronous up and down
counters.
 EXPERIMENT No. 12
3 BIT UP/DOWN SYNCHRONOUS COUNTERS

AIM: To design, setup and verify the truth table of 3 bit synchronous up/down
counter.
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7476 and 7400) and connecting wires
THEORY:
The circuit below is of a simple 3-bit Up/Down synchronous counter using JK
flip-flops configured to operate as toggle or T-type flip-flops giving a maximum
count of zero (000) to seven (111) and back to zero again. Then the 3-Bit
counter advances upward in sequence (0,1,2,3,4,5,6,7) or downwards in reverse
sequence (7,6,5,4,3,2,1,0). Generally most bidirectional counter chips can be
made to change their count direction either up or down at any point within their
counting sequence. This is achieved by using an additional input pin which
determines the direction of the count, either Up or Down and the timing
diagram gives an example of the counters operation as this Up/Down input
changes state.
PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

RESULT:
Designed, setup and verified the truth tables 4 bit synchronous up/down
counter.
 EXPERIMENT No. 13
SHIFT REGISTERS
AIM: To construct 4 bit SISO, SIPO, PISO, PIPO shift registers and to verify
their operation.
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7476 and 7400) and connecting wires
THEORY:
Shift register is used to move the data. To move data, it must be stored. So shift
register actually stores data and moves it to left, right as per signal given to it.
Its various types are:
-Serial In Serial Out
-Serial In Parallel Out
-Parallel In Serial Out
-Parallel In Parallel Out
As flip flops are capable to store data (1 bit in a flip flop), they are used to
construct shift registers.
Serial In: Output of one flip flop is input of another. Data is serially given i.e.
only first flip flop receives data; it is shifted to next flip flops.
Serial Out: Data is taken out from last flip flop
Parallel In: All flip flops are loaded simultaneously
Parallel Out: data is taken parallely by taking outputs from all flip flops at same
time.
a) SISO & SIPO

b) PIPO
 c) PISO

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

RESULT:
Constructed 4 bit SISO, SIPO, PISO, PIPO shift registers and verified their
operation.
.
 EXPERIMENT No. 14
RING AND JOHNSON COUNTERS

AIM: To construct 4 bit ring and Johnson counters and to verify their operation.
COMPONENTS AND EQUIPMENTS REQUIRED: Digital IC trainer kit,
ICs (7476 ) and connecting wires
THEORY:
Ring counter is constructed by modifying the Serial In Serial Out shift register.
The basic ring counter can be obtained by connecting the last output to first
input. When clock signal is applied, data is shifted in a circular manner or in a
closed ring, so it is called a ring counter. Johnson Counter. A Johnson counter is
a modified ring counter, where the inverted output from the last flip flop is
connected to the input to the first. The register cycles through a sequence of bit-
patterns. The MOD of the Johnson counter is 2n if n flip-flops are used.

a) 4 Bit Ring Counter

b) 4 Bit Johnson Counter

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

RESULT:
Constructed 4 bit ring and Johnson counters and verified their operation.
.