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08003-001
Single-supply operation: 3 V to 3.6 V GND
Power-down control Figure 1.
Fabricated using the high speed XFCB3 SiGe process
APPLICATIONS
Differential ADC drivers
Single-ended to differential conversion
RF/IF gain blocks
SAW filter interfacing
GENERAL DESCRIPTION
The ADL5562 is a high performance differential amplifier The device is optimized for wideband, low distortion
optimized for RF and IF applications. The amplifier offers low performance. These attributes, together with its adjustable gain
noise of 2.1 nV/√Hz and excellent distortion performance over capability, make this device the amplifier of choice for general-
a wide frequency range, making it an ideal driver for high speed purpose IF and broadband applications where low distortion,
8-bit to 16-bit ADCs. noise, and power are critical. This device is optimized for the
The ADL5562 provides three gain levels of 6 dB, 12 dB, and best combination of slew speed, bandwidth, and broadband
15.5 dB through a pin-strappable configuration. For the single- distortion. These attributes allow it to drive a wide variety of
ended input configuration, the gains are reduced to 5.6 dB, analog-to-digital converters (ADCs) and make it ideally suited
11.1 dB, and 14.1 dB. Using an external series input resistor for driving mixers, pin diode attenuators, SAW filters, and
expands the amplifier gain flexibility and allows for any gain multi-element discrete devices.
selection from 0 dB to 15.5 dB. Fabricated on an Analog Devices, Inc., high speed SiGe process,
The quiescent current of the ADL5562 is typically 80 mA and, the ADL5562 is supplied in a compact 3 mm × 3 mm, 16-lead
when disabled, consumes less than 3 mA, offering excellent LFCSP package and operates over the temperature range of
input-to-output isolation. −40°C to + 85°C.
TABLE OF CONTENTS
Features .............................................................................................. 1 Basic Structure ............................................................................ 13
Applications ....................................................................................... 1 Applications Information .............................................................. 14
Functional Block Diagram .............................................................. 1 Basic Connections ...................................................................... 14
General Description ......................................................................... 1 Input and Output Interfacing ................................................... 15
Revision History ............................................................................... 2 Gain Adjustment and Interfacing ............................................ 16
Specifications..................................................................................... 3 ADC Interfacing ......................................................................... 16
Absolute Maximum Ratings............................................................ 6 Layout Considerations ............................................................... 18
ESD Caution .................................................................................. 6 Soldering Information ............................................................... 19
Pin Configuration and Function Descriptions ............................. 7 Evaluation Board ........................................................................ 19
Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 21
Circuit Description ......................................................................... 13 Ordering Guide .......................................................................... 21
REVISION HISTORY
9/2017—Rev. E to Rev. F 3/2010—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 21 Changes to Figure 43...................................................................... 19
Changes to Ordering Guide .......................................................... 21 Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
1/2014—Rev. D to Rev. E
Changes to ENBL Threshold Parameter, Table 1 ......................... 3 9/2009—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
4/2013—Rev. C to Rev. D Changes to Table 1.............................................................................3
Changes to Table 1 ............................................................................ 3 Changes to Figure 5 ...........................................................................8
Changes to Figure 6 and Figure 7 ................................................... 8 Changes to Figure 9 and Figure 10..................................................9
Changes to Figure 32, Equation 1, and Figure 34 ...................... 15
Changes to Equation 2 ................................................................... 16
7/2011—Rev. B to Rev. C Changes to Figure 38, Figure 39, Figure 40, and Table 9........... 17
Changes to Figure 28 and Figure 29 ............................................. 12 Changes to Figure 43...................................................................... 19
Added Figure 30 and Figure 31; Renumbered Sequentially ..... 12 Moved Table 14 to .......................................................................... 19
Changes to Ordering Guide .......................................................... 21
5/2009—Revision 0: Initial Version
Rev. F | Page 2 of 21
Data Sheet ADL5562
SPECIFICATIONS
VCC = 3.3 V, VCOM = 1.65 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 140 MHz, TA = 25°C.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth AV = 6 dB, VOUT ≤ 1.0 V p-p 3300 MHz
AV = 12 dB, VOUT ≤ 1.0 V p-p 3900 MHz
AV = 15.5 dB, VOUT ≤ 1.0 V p-p 1900 MHz
Bandwidth for 0.1 dB Flatness AV = 6 dB, VOUT ≤ 1.0 V p-p 220 MHz
AV = 12 dB, VOUT ≤ 1.0 V p-p 270 MHz
AV = 15.5 dB, VOUT ≤ 1.0 V p-p 270 MHz
Gain Accuracy AV = 6 dB, RL = open 0.17 dB
AV = 12 dB, RL = open 0.05 dB
AV = 15.5 dB, RL = open 0.06 dB
Gain Supply Sensitivity VCC ± 5% −0.005 dB/V
Gain Temperature Sensitivity −40°C to +85°C, AV = 15.5 dB 0.32 mdB/°C
Slew Rate Rise, AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V step 9.8 V/ns
Fall, AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V step 10.1 V/ns
Settling Time 2 V step to 1% 2 ns
Overdrive Recovery Time VIN = 4 V to 0 V step, VOUT ≤ ±10 mV 3 ns
Reverse Isolation (S12) 60 dB
INPUT/OUTPUT CHARACTERISTICS
Output Common Mode VCC/2 V
Voltage Adjustment Range 1.4 to 1.8 V
Maximum Output Voltage Swing 1 dB compressed 4.9 V p-p
Output Common-Mode Offset Referenced to VCC/2 60 mV
Output Common-Mode Drift −40°C to +85°C 285 µV/°C
Output Differential Offset Voltage 1 mV
CMRR 65 dB
Output Differential Offset Drift −40°C to +85°C 15 µV/°C
Input Bias Current 3 µA
Input Resistance (Differential) AV = 6 dB 400 Ω
AV = 12 dB 200 Ω
AV = 15.5 dB 133 Ω
Input Resistance (Single-Ended) 1 AV = 5.6 dB, RS = 50 Ω 307 Ω
AV = 11.1 dB, RS = 50 Ω 179 Ω
AV = 14.1 dB, RS = 50 Ω 132 Ω
Input Capacitance (Single-Ended) 0.3 pF
Output Resistance (Differential) 12 Ω
POWER INTERFACE
Supply Voltage 3 3.3 3.6 V
ENBL Threshold Device disabled, ENBL low 0.5 V
Device enabled, ENBL high 1.5 V
ENBL Input Bias Current ENBL high −27 µA
ENBL low −300 µA
Quiescent Current ENBL high 75.5 80 84.5 mA
ENBL low 3.5 mA
Rev. F | Page 3 of 21
ADL5562 Data Sheet
Parameter Conditions Min Typ Max Unit
10 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p −91/−98 dBc
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p −95/−98 dBc
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p −96/−92 dBc
Output Third-Order Intercept/Third-Order AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite +42/−97 dBm/dBc
Intermodulation Distortion (2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite +43/−93 dBm/dBc
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite +43/−91 dBm/dBc
(2 MHz spacing)
Noise Spectral Density (RTI) AV = 6 dB 3 nV/√Hz
AV = 12 dB 2.1 nV/√Hz
AV = 15.5 dB 1.6 nV/√Hz
1 dB Compression Point (RTO) AV = 6 dB 13.5 dBm
AV = 12 dB 13.4 dBm
AV = 15.5 dB 13 dBm
70 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p −102/−90 dBc
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p −97/−85 dBc
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p −93/−83 dBc
Output Third-Order Intercept/Third-Order AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite +46/−96 dBm/dBc
Intermodulation Distortion (2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite +44/−93 dBm/dBc
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite +43/−91 dBm/dBc
(2 MHz spacing)
Noise Spectral Density (RTI) AV = 6 dB 3 nV/√Hz
AV = 12 dB 2.1 nV/√Hz
AV = 15.5 dB 1.6 nV/√Hz
1 dB Compression Point (RTO) AV = 6 dB 13.2 dBm
AV = 12 dB 13.2 dBm
AV = 15.5 dB 12.6 dBm
140 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p −104/−87 dBc
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p −82/−81 dBc
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p −80/−80 dBc
Output Third-Order Intercept/Third-Order AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite +47/−100 dBm/dBc
Intermodulation Distortion (2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite +45/−95 dBm/dBc
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite +43/−92 dBm/dBc
(2 MHz spacing)
Noise Spectral Density (RTI) AV = 6 dB 3 nV/√Hz
AV = 12 dB 2.1 nV/√Hz
AV = 15.5 dB 1.6 nV/√Hz
1 dB Compression Point (RTO) AV = 6 dB 13.4 dBm
AV = 12 dB 13.3 dBm
AV = 15.5 dB 12.4 dBm
Rev. F | Page 4 of 21
Data Sheet ADL5562
Parameter Conditions Min Typ Max Unit
250 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p −80/−94 dBc
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p −74/−86 dBc
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p −74/−84 dBc
Output Third-Order Intercept/Third-Order AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite +43/−94 dBm/dBc
Intermodulation Distortion (2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite +41/−87 dBm/dBc
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite +40/−86 dBm/dBc
(2 MHz spacing)
Noise Spectral Density (RTI) AV = 6 dB 3.2 nV/√Hz
AV = 12 dB 2.2 nV/√Hz
AV = 15.5 dB 1.6 nV/√Hz
1 dB Compression Point (RTO) AV = 6 dB 13 dBm
AV = 12 dB 13 dBm
AV = 15.5 dB 12 dBm
500 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion AV = 6 dB, RL = 200 Ω, VOUT = 1 V p-p −75/−69 dBc
AV = 12 dB, RL = 200 Ω, VOUT = 1 V p-p −69/−73 dBc
AV = 15.5 dB, RL = 200 Ω, VOUT = 1 V p-p −72/−75 dBc
Output Third-Order Intercept/Third-Order AV = 6 dB, RL = 200 Ω, VOUT = 1 V p-p composite +40/−98 dBm/dBc
Intermodulation Distortion (2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 1 V p-p composite +39/−97 dBm/dBc
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 1 V p-p composite +38/−93 dBm/dBc
(2 MHz spacing)
Noise Spectral Density (RTI) AV = 6 dB 3.7 nV/√Hz
AV = 12 dB 2.2 nV/√Hz
AV = 15.5 dB 1.6 nV/√Hz
1000 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion AV = 6 dB, RL = 200 Ω, VOUT = 1 V p-p −70/−60 dBc
AV = 12 dB, RL = 200 Ω, VOUT = 1 V p-p −69/−61 dBc
AV = 15.5 dB, RL = 200 Ω, VOUT = 1 V p-p −66/−59 dBc
Output Third-Order Intercept/Third-Order AV = 6 dB, RL = 200 Ω, VOUT = 1 V p-p composite +24/−65 dBm/dBc
Intermodulation Distortion (2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 1 V p-p composite +24/−66 dBm/dBc
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 1 V p-p composite +25/−66 dBm/dBc
(2 MHz spacing)
Noise Spectral Density (RTI) AV = 6 dB 4.7 nV/√Hz
AV = 12 dB 2.2 nV/√Hz
AV = 15.5 dB 1.6 nV/√Hz
1
See the Applications Information section for a discussion of single-ended input, dc-coupled operation.
Rev. F | Page 5 of 21
ADL5562 Data Sheet
Rev. F | Page 6 of 21
Data Sheet ADL5562
16 GND
15 GND
13 GND
14 GND
PIN 1
VIP2 1 INDICATOR 12 ENBL
VIP1 2 11 VOP
ADL5562
VIN1 3 TOP VIEW 10 VON
VIN2 4 (Not to Scale) 9 VCOM
VCC 8
VCC 7
VCC 5
VCC 6
NOTES
08003-031
1. EXPOSED PADDLE. CONNECT TO A LOW
IMPEDANCE THERMAL AND ELECTRICAL
GROUND PLANE.
Rev. F | Page 7 of 21
ADL5562 Data Sheet
OP1dB (dBm)
9
GAIN (dB)
8
10
7
6
MAX GAIN –40°C
8 5 MAX GAIN +25°C
4 MAX GAIN +85°C
MID GAIN –40°C
3 MID GAIN +25°C
6 MINIMUM GAIN MID GAIN +85°C
2 MIN GAIN –40°C
1 MIN GAIN +25°C
MIN GAIN +85°C
4 0
08003-017
08003-002
10M 100M 1G 10G 0 50 100 150 200 250
FREQUENCY (Hz) FREQUENCY (MHz)
Figure 3. Gain vs. Frequency Response for 200 Ω Differential Load, Figure 6. Output P1dB (OP1dB) vs. Frequency at AV = 6 dB, AV = 12 dB, and
AV = 6 dB, AV = 12 dB, and AV = 15.5 dB over Temperature AV = 15.5 dB over Temperature, 200 Ω Differential Load
20 14
–40°C
+25°C
18 +85°C 12
16 MAXIMUM GAIN
10
OP1dB (dBm)
14
GAIN (dB)
8
MID GAIN
12
6
10 MAX GAIN –40°C
MAX GAIN +25°C
4 MAX GAIN +85°C
8 MID GAIN –40°C
MID GAIN +25°C
MINIMUM GAIN MID GAIN +85°C
6 2 MIN GAIN –40°C
MIN GAIN +25°C
MIN GAIN +85°C
4 0
08003-016
08003-003
Figure 4. Gain vs. Frequency Response for 1 kΩ Differential Load, Figure 7. Output P1dB (OP1dB) vs. Frequency at AV = 6 dB, AV = 12 dB, and
AV = 6 dB, AV = 12 dB, and AV = 15.5 dB over Temperature AV = 15.5 dB over Temperature, 1 kΩ Differential Load
16 8
AV MAXIMUM AV MAXIMUM
AV MID AV MID
14 AV MINIMUM 7 AV MINIMUM
NOISE SPECTRAL DENSITY (nV/√Hz)
12 6
NOISE FIGURE (dB)
10 5
8 4
6 3
4 2
2 1
0 0
08003-005
08003-004
Figure 5. Noise Figure vs. Frequency at Figure 8. Noise Spectral Density vs. Frequency
AV = 6 dB, AV = 12 dB, and AV = 15.5 dB at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB
Rev. F | Page 8 of 21
Data Sheet ADL5562
60 –40 0
AV MAXIMUM AV MAXIMUM
55 AV MID AV MID
AV MINIMUM AV MINIMUM
–60 –20
50
35 –100 –60
30
–120 –80
25
20
–140 –100
15
–160 –120
08003-020
10
08003-018
0 50 100 150 200 250 0 50 100 150 200 250
Figure 9. Output Third-Order Intercept at Three Gains, Output Level at 2 V p-p Figure 12. Two-Tone Output IMD vs. Frequency, Output Level
Composite, RL = 200 Ω at 2 V p-p Composite, RL = 200 Ω and RL = 1 kΩ
60 50
+85°C
+25°C
–40°C 45
50
40
35
40
OIP3 (dBm)
30
OIP3 (dBm)
30 25
20
20
15
10 10
5
0 0
08003-019
08003-028
FREQUENCY (MHz) POUT/TONE (dBm)
Figure 10. Output Third-Order Intercept vs. Frequency, Over Temperature, Figure 13. Output Third-Order Intercept (OIP3) vs. Power (POUT),
Output Level at 2 V p-p Composite, RL = 200 Ω Frequency 140 MHz, AV = 15.5 dB
60 –70
AV MAXIMUM AV MAXIMUM
AV MID AV MID
AV MINIMUM –75 AV MINIMUM
55
–80
50
–85
OIP3 (dBm)
IMD (dBc)
45 –90
–95
40
–100
35
–105
30 –110
08003-007
Figure 11. OIP3 vs. Frequency (Single-Ended Input) Figure 14. IMD vs. Frequency (Single-Ended Input)
Rev. F | Page 9 of 21
ADL5562 Data Sheet
–40 0 –40 0
AV MAXIMUM AV MAXIMUM
AV MID AV MID
AV MINIMUM AV MINIMUM
08003-021
0 50 100 150 200 250 0 50 100 150 200 250
08003-024
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 15. Harmonic Distortion (HD2/HD3) vs. Frequency at AV = 6 dB, Figure 18. Harmonic Distortion (HD2/HD3) vs. Frequency at Av = 6 dB,
AV = 12 dB, and AV = 15.5 dB, Output Level at 2 V p-p, RL = 200 Ω Av = 12 dB, and Av = 15.5 dB, Output Level at 2 V p-p, RL = 1 kΩ
–40 0 –20
+85°C
+25°C
–40°C –30
HARMONIC DISTORTION HD3 (dBc)
HARMONIC DISTORTION HD2 (dBc)
–60 –20
–70
–120 –80 HD2
–80
HD3
–140 –100
–90
–160 –120
08003-022
–100
08003-029
0 50 100 150 200 250 –2 –1 0 1 2 3 4 5
FREQUENCY (MHz) POUT (dBm)
Figure 16. Harmonic Distortion (HD2/HD3) vs. Frequency, Figure 19. Harmonic Distortion (HD2/HD3) vs. Power (POUT),
Three Temperatures, Output Level at 2 V p-p, RL = 200 Ω Frequency 140 MHz, AV = 15.5 dB
–40 0 –60 –50
+85°C
+25°C AV MAXIMUM
–40°C –65 AV MID –55
AV MINIMUM
HARMONIC DISTORTION HD3 (dBc)
HARMONIC DISTORTION HD2 (dBc)
–60 –20
HARMONIC DISTORTION HD2 (dBc)
–75 –65
–80 –40
–80 –70
–90 –80
–120 –80
–95 –85
–100 –90
–140 –100
–105 –95
Figure 17. Harmonic Distortion (HD2/HD3) vs. Frequency, Over Temperature, Figure 20. Harmonic Distortion (HD2/HD3) vs. Frequency (Single-Ended Input)
Output Level at 2 V p-p, RL = 1 kΩ
Rev. F | Page 10 of 21
Data Sheet ADL5562
–30 –60 –55 –60
AV MAXIMUM AV MAXIMUM
AV MID –60 AV MID –65
–40 AV MINIMUM –70 AV MINIMUM
–75 –80
–60 –90
–80 –85
–70 –100
–85 –90
–95 –100
–90 –120
–100 –105
08003-010
0 100 200 300 400 500 600 700 800 900 1000
08003-009
RLOAD (Ω) VCOM (V)
Figure 21. Harmonic Distortion (HD2/HD3) vs. RLOAD Figure 24. Harmonic Distortion (HD2/HD3) vs. VCOM
1.0 0
AV MAXIMUM
0.9 AV MID –20
AV MINIMUM
0.8 –40
PHASE (Degrees)
VOLTAGE (V)
0.6 –80
0.5 –100
0.4 –120
0.3 –140
08003-030
0.2 –160
0.1 –180
08003-011
TIME (2.5ns/DIV) 0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
Figure 22. ENBL Time Domain Response Figure 25. Group Delay and Phase vs. Frequency
110 80
AV MAXIMUM
AV MID
100 RL = 1kΩ AV MINIMUM 70
2V p-p OUTPUT
90 60
VOLTAGE (V)
80 50
CMRR (dB)
CMRR (dB)
RL = 200Ω
70 40
60 30
50 20
40 10
08003-036
30 0
08003-012
Figure 23. Large Signal Pulse Response, AV = 15.5 dB Figure 26. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Rev. F | Page 11 of 21
ADL5562 Data Sheet
800 8
0 AV MAXIMUM
AV MID
700 AV MINIMUM 7
–10
600 6
CAPACITANCE (pF)
–20 DISABLED
RESISTANCE (Ω)
500 5
–30
S12 (dB)
400 4
–40 300 3
–50 200 2
100 1
–60 ENABLED
0 0
08003-051
–70 10M 100M 1G
08003-013
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 27. Reverse Isolation (S12) vs. Frequency Figure 30. Input Resistance and Capacitance vs. Frequency
16 10
1000 20 AV MAXIMUM
AV MAXIMUM AV MID
900 AV MID 10 14 AV MINIMUM
AV MINIMUM
8
800 0 12
IMPEDANCE MAGNITUDE (Ω)
INDUCTANCE (nH)
700 –10
RESISTANCE (Ω)
10
PHASE (Degrees)
6
600 –20
8
500 –30
4
400 –40 6
300 –50 4
2
200 –60
2
100 –70
0 0
08003-052
0 –80 10M 100M 1G 2G
08003-014
10M 100M 1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 28. Input Impedance vs. Frequency Figure 31. Output Resistance and Inductance vs. Frequency
16 40
AV MAXIMUM
AV MID
14 AV MINIMUM 35
IMPEDANCE MAGNITUDE (Ω)
12 30
PHASE (Degrees)
10 25
8 20
6 15
4 10
2 5
0 0
08003-015
10M 100M 1G
FREQUENCY (Hz)
Rev. F | Page 12 of 21
Data Sheet ADL5562
CIRCUIT DESCRIPTION
BASIC STRUCTURE The ADL5562 is composed of a fully differential amplifier with
The ADL5562 is a low noise, fully differential amplifier/ADC on-chip feedback and feed-forward resistors. The two feed-forward
driver that uses a 3.3 V supply. It provides three gain options resistors on each input set this pin-strappable amplifier in three
(6 dB, 12 dB, and 15.5 dB) without the need for external resistors different gain configurations of 6 dB, 12 dB, and 15.5 dB. The
and has wide bandwidths of 2.6 GHz for 6 dB, 2.3 GHz for 12 dB, amplifier is designed to provide high differential open-loop gain
and 2.1 GHz for 15.5 dB. Differential input impedance is 400 Ω and an output common-mode circuit that enables the user to
for 6 dB, 200 Ω for 12 dB, and 133 Ω for 15.5 dB. It has a change the common-mode voltage from a VCOM pin. The
differential output impedance of 10 Ω and a common-mode amplifier is designed to provide superior low distortion at
adjust voltage of 1.25 V to 1.85 V. frequencies up to and beyond 300 MHz with low noise and
low power consumption. The low distortion and noise are
0.1µF 400Ω realized with a 3.3 V power supply at 80 mA.
+
1/ R VIP2 100Ω 5Ω The ADL5562 is very flexible in terms of I/O coupling. It can
2 S
VIP1 200Ω be ac-coupled or dc-coupled at the inputs and/or the outputs
AC
VIN1 200Ω RL within the specified input and output common-mode levels.
The input of the device can be configured as single-ended or
1/ R VIN2 100Ω 5Ω
2 S
differential with similar distortion performance. Due to the
400Ω
internal connections between the inputs and outputs, keep the
08003-032
+
Rev. F | Page 13 of 21
ADL5562 Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS Pin 1 to Pin 4, Pin 10, and Pin 11 are biased at 1/2 VCC above
Figure 33 shows the basic connections for operating the ADL5562. ground and can be dc-coupled (if within the specified input or
VCC must be 3.3 V with each supply pin decoupled with at least output common-mode voltage levels) or ac-coupled as shown
one low inductance surface-mount ceramic capacitor of 0.1 μF in Figure 33.
placed as close as possible to the device. The VCOM pin (Pin 9) To enable the ADL5562, the ENBL pin must be pulled high.
must also be decoupled using a 0.1 μF capacitor. Pulling the ENBL pin low puts the ADL5562 in sleep mode,
The gain of the part is determined by the pin-strappable input reducing the current consumption to 3 mA at ambient.
configuration. When Input A is applied to VIP1 and Input B is
applied to VIN1, the gain is 6 dB (minimum gain, see Equation 1
and Equation 2). When Input A is applied to VIP2 and Input B
is applied to VIN2, the gain is 12 dB (middle gain). When
Input A is applied to VIP1 and VIP2 and Input B is applied to
VIN1 and VIN2, the gain is 15.5 dB (maximum gain).
VCC
16 15 14 13
GND GND GND GND
A 1 VIP2 ENBL 12
RS/2
0.1µF
2 VIP1 VOP 11
BALANCED AC BALANCED
SOURCE ADL5562 RL
LOAD
3 VIN1 VON 10
0.1µF B
RS/2
4 VIN2 VCOM 9
0.1µF
VCC VCC VCC VCC
5 6 7 8
VCC
08003-033
10µF 0.1µF
Rev. F | Page 14 of 21
Data Sheet ADL5562
INPUT AND OUTPUT INTERFACING Single-Ended Input to Differential Output
The ADL5562 can be configured as a differential-input to The ADL5562 can also be configured in a single-ended input
differential-output driver, as shown in Figure 34. The differential to differential output driver, as shown in Figure 36. In this
broadband input is provided by the ETC1-1-13 balun transformer, configuration, the gain of the part is reduced due to the application
and the two 34.8 Ω resistors provide a 50 Ω input match for the of the signal to only one side of the amplifier. The strappable
three input impedances that change with the variable gain gain values are listed in Table 6 with the required terminations
strapping. The input and output 0.1 μF capacitors isolate the VCC/2 to match to a 50 Ω source using R1 and R2. Note that R1 must
bias from the source and balanced load. The load must equal 200 Ω equal the parallel value of the source and R2. The input and
to provide the expected ac performance (see the Specifications output 0.1 μF capacitors isolate the VCC/2 bias from the source
section and the Typical Performance Characteristics section). and the balanced load. The performance for this configuration
3.3V is shown in Figure 11, Figure 14, and Figure 20.
3.3V
0.1µF
0.1µF VIP2
ETC1-1-13 A + RL
VIP1 0.1µF
VIP2
+
R2 2 0.1µF
A
+
50Ω VIN1 VIP1 RL
+
0.1µF RL 2
B 0.1µF
VIN2 2 50Ω R2 VIN1
+
AC RL
R1 B
+
VIN2 0.1µF 2
AC
+
+
0.1µF
NOTES R1
1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.
2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.
08003-043
3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2
AND INPUT B TO BOTH VIN1 AND VIN2. NOTES
1. FOR 5.6dB GAIN (AV = 1.9), CONNECT INPUT A TO VIP1
Figure 34. Differential-Input to Differential-Output Configuration AND INPUT B TO VIN1.
2. FOR 11.1dB GAIN (AV = 3.6), CONNECT INPUT A TO VIP2
Table 4. Differential Termination Values for Figure 34 AND INPUT B TO VIN2.
08003-045
3. FOR 14.1dB GAIN (AV = 5.1), CONNECT INPUT A TO BOTH
Gain (dB) R1 (Ω) R2 (Ω) VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
5Ω 0.1µF
1/ R VIP2 100Ω
2 S on the source impedance and load, as shown in Figure 37.
+
VIP1 200Ω RL
2
AC VIN1 200Ω 400Ω
RL
VIN2 100Ω 5Ω 0.1µF 2 5Ω 0.1µF
0.1µF VIP2 100Ω
1/ R
2 S
+
+ RL
0.1µF 400Ω VIP1 200Ω
+
2
RS R2
08003-044
+
VIN1 200Ω
RL
VIN2 100Ω 5Ω 0.1µF 2
Figure 35. Differential Input Loading Circuit AC
+
+
0.1µF 400Ω
The differential gain can be determined using the following R1
08003-046
400 RL
AV (1)
RIN 10 RL
Rev. F | Page 15 of 21
ADL5562 Data Sheet
The single-ended gain can be determined using the following The necessary shunt component, RSHUNT, to match to the source
formula. The values of RIN and RX for each gain configuration impedance, RS, can be expressed as
are shown in Table 7. 1
RSHUNT = (4)
400 R2 R + RS RL 1 1
AV 1 = × × X × (2) −
RS × R2 RS + R2 RX 10 + RL RS RSERIES + RIN
RIN +
RS + R2 The insertion loss and the resultant power gain for multiple
shunt resistor values are summarized in Table 8. The source
Table 7. Values of RIN and RX for Single-Ended Gain resistance and input impedance need careful attention when using
Gain (dB) RIN (Ω) RX (Ω) Equation 3 and Equation 4. The reactance of the input impedance
5.6 200 R2 || 3071 of the ADL5562 and the ac coupling capacitors must be considered
11.1 100 R2 || 1791 before assuming that they make a negligible contribution.
14.1 66.7 R2 || 1321 Table 8. Gain Adjustment Using Series Resistor
1
These values based on a 50 Ω input match. Il (dB) RIN (Ω) RS (Ω) RSERIES (Ω) RSHUNT (Ω)
GAIN ADJUSTMENT AND INTERFACING 2 400 50 105 54.9
The effective gain of the ADL5562 can be reduced using a number 4 400 50 232 54.9
of techniques. A matched attenuator network can reduce the 2 200 50 51.1 61.9
effective gain; however, this requires the addition of a separate 4 200 50 115 59
component that can be prohibitive in size and cost. Instead, a 2 133 50 34.8 71.5
simple voltage divider can be implemented using the combination 2 400 200 102 332
of additional series resistors at the amplifier input and the input 4 400 200 232 294
impedance of the ADL5562, as shown in Figure 38. A shunt 2 200 200 51.1 976
resistor is used to match to the impedance of the previous stage. 4 200 200 115 549
VIN1
2 400 50 105 54.9
0.1µF 1/2 RSERIES
1/ R 4 400 50 232 54.9
2 S VIN2
1/ R
2 SHUNT 2 200 50 51.1 61.9
AC
0.1µF 1/2 RSERIES VIP1 ADL5562
1/ R
2 S
1/ R VIP2 ADC INTERFACING
08003-037
2 SHUNT
VIP2
0.1µF A 0.1µF 33Ω
ETC1-1-13 VOP
50Ω VIP1 VIN+
+
34.8Ω 14
AD9445
AC VIN1 ADL5562 14-BIT ADC
0.1µF B 0.1µF 33Ω
VIN–
VIN2
+
34.8Ω VON
08003-038
Rev. F | Page 16 of 21
Data Sheet ADL5562
This circuit provides variable gain, isolation, and source matching The wideband frequency response is an advantage in broad-
for the AD9445. Using this circuit with the ADL5562 in a gain band applications, such as predistortion receiver designs and
of 6 dB, an SFDR performance of 87 dBc is achieved at 140 MHz, instrumentation applications. However, by designing for a wide
and a −3 dB bandwidth of 760 MHz, as indicated in Figure 40 analog input frequency range, the cascaded SNR performance is
and Figure 41. somewhat degraded due to high frequency noise aliasing into
0 the wanted Nyquist zone.
–10 ADL5562 DRIVING THE AD9445 14-BIT ADC
–20
GAIN = 6dB
INPUT = 140MHz
An alternative narrow-band approach is presented in Figure 42.
–30 SNR = 66.25dBc
SFDR = 87.44dBc
By designing a narrow band-pass antialiasing filter between the
–40 NOISE FLOOR = –109.5dB
FUND = –1.081dBFS
ADL5562 and the target ADC, the output noise of the ADL5562
–50 SECOND = –84.54dBc
THIRD = –84.54dBc
outside of the intended Nyquist zone can be attenuated, helping
–60
to preserve the available SNR of the ADC. In general, the SNR
(dBFS)
–70
–80 improves several decibels when including a reasonable order anti-
–90 aliasing filter. In this example, a low loss 1:1 input transformer is
–100
used to match the ADL5562 balanced input to a 50 Ω unbalanced
–110
–120 source, resulting in minimum insertion loss at the input.
–130
Figure 42 is optimized for driving some of the Analog Devices
–140
–150
popular unbuffered ADCs, such as the AD9246, AD9640,
0 6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25 62.50 and AD6655. Table 9 includes antialiasing filter component
08003-026
FREQUENCY (MHz)
recommendations for popular IF sampling center frequencies.
Figure 40. Measured Single-Tone Performance of the Inductor L5 works in parallel with the on-chip ADC input
Circuit in Figure 39 for a 100 MHz Input Signal capacitance and a portion of the capacitance presented by C4 to
0 form a resonant tank circuit. The resonant tank helps to ensure
–1 that the ADC input looks like a real resistance at the target center
–2 frequency. The L5 inductor shorts the ADC inputs at dc, which
–3
introduces a zero into the transfer function. In addition, the ac
coupling capacitors introduce additional zeros into the transfer
–4
function. The final overall frequency response takes on a band-
(dBFS)
–5
pass characteristic, helping to reject noise outside of the intended
–6 Nyquist zone. Table 9 provides initial suggestions for prototyping
–7 purposes. Some empirical optimization may be needed to help
–8 FIRST POINT = –1.02dBFS compensate for actual PCB parasitics.
END POINT = –5.69dBFS
MID POINT = –1.09dBFS
–9 MIN = –5.69dBFS
MAX = –0.88dBFS
–10
2.00 161.80 321.60 481.40 641.20 801.00
08003-025
1nF 4Ω L1 L3
105Ω AD9246
ADL5562 C2 C4 CML L5 AD9640
08003-039
Rev. F | Page 17 of 21
ADL5562 Data Sheet
LAYOUT CONSIDERATIONS minimized. In many board designs, the signal trace widths must
High-Q inductive drives and loads, as well as stray transmission be minimal where the driver/receiver is more than one-eighth of
line capacitance in combination with package parasitics, can the wavelength from the amplifier. This nontransmission line
potentially form a resonant circuit at high frequencies, resulting configuration requires that underlying and adjacent ground and
in excessive gain peaking or possible oscillation. If RF transmission low impedance planes be dropped from the signal lines.
lines connecting the input or output are used, they must be
designed such that stray capacitance at the input/output pins is
R3
VIP2
R1 R9
0.1µF 0.1µF
R4 R7
ETC1-1-13 VIP1 VOP ETC1-1-13
ADL5562 SPECTRUM
R5 R8 ANALYZER
VIN1 VON
R2 0.1µF 0.1µF R10
R6
VIN2
08003-034
Figure 43. General Purpose Characterization Circuit
Table 10. Gain Setting and Input Termination Components for Figure 43
AV (dB) R1 (Ω) R2 (Ω) R3 (Ω) R4 (Ω) R5 (Ω) R6 (Ω)
6 29 29 Open 0 0 Open
12 33 33 0 Open Open 0
15.5 40.2 40.2 0 0 0 0
R3
VIP2
R1 R9
R4 R7
PORT 1 VIP1 VOP PORT 2
ADL5562
R5 R8
PORT 3 VIN1 VON PORT 4
R2 R6 R10
VIN2
08003-035
Figure 44. Differential Characterization Circuit Using Agilent E8357A 4-Port PNA
Table 12. Gain Setting and Input Termination Components for Figure 44
AV (dB) R1 (Ω) R2 (Ω) R3 (Ω) R4 (Ω) R5 (Ω) R6 (Ω)
6 67 67 Open 0 0 Open
12 100 100 0 Open Open 0
15.5 200 200 0 0 0 0
Rev. F | Page 18 of 21
Data Sheet ADL5562
SOLDERING INFORMATION To realize the minimum gain (6 dB into a 200 Ω load), Input 1
On the underside of the chip scale package, there is an exposed (VIN1 and VIP1) must be used by installing 0 Ω resistors at R3
compressed paddle. This paddle is internally connected to the and R4, leaving R5 and R6 open. R1 and R2 must be 33 Ω for a
ground of the chip. Solder the paddle to the low impedance 50 Ω input impedance.
ground plane on the PCB to ensure the specified electrical Likewise, driving Input 2 (VIN2 and VIP2) realizes the middle
performance and to provide thermal relief. To further reduce gain (12 dB into a 200 Ω load) by installing 0 Ω at R5 and R6
thermal impedance, it is recommended that the ground planes and leaving R3 and R4 open. R1 and R2 must be 29 Ω for a
on all layers under the paddle be stitched together with vias. 50 Ω input impedance.
EVALUATION BOARD For the maximum gain (15.5 dB into a 200 Ω load), both inputs
are driven by installing 0 Ω resistors at R3, R4, R5, and R6. R1
Figure 45 shows the schematic of the ADL5562 evaluation board.
and R2 must be 40.2 Ω for a 50 Ω input impedance.
The board is powered by a single supply in the 3 V to 3.6 V range.
The power supply is decoupled by 10 µF and 0.1 µF capacitors. The balanced input and output interfaces are converted to
single ended with a pair of baluns (M/A-COM ETC1-1-13).
Table 14 details the various configuration options of the evaluation
The balun at the input, T1, provides a 50 Ω single-ended-to-
board. Figure 46 and Figure 47 show the component and circuit
differential transformation. The output balun, T2, and the
layouts of the evaluation board.
matching components are configured to provide a 200 Ω to 50 Ω
impedance transformation with an insertion loss of about 17 dB.
GND ENBL
16 15 14 13 VPOS
GND GND GND GND P1 C8
0.1µF
1 VIP2 ENBL 12 AGND
R5 T2
C1 J3
0.01µF 0Ω
T1 C9 R7 R9 R11
J1 2 VIP1 VOP 11 84.5Ω 34.8Ω OPEN
R1 0.01µF
R3 ADL5562
40.2Ω C2 0Ω
0.01µF 3 VIN1 VON 10 R8 R10 C13
C10 34.8Ω 0.1µF
C12 84.5Ω
R2 R4 0.01µF
0.1µF 40.2Ω 0Ω 4 VIN2 VOCM 9
VCC VCC VCC VCC C11
0.1µF
R6 5 6 7 8
0Ω J2
VPOS
08003-040
C3 C4 C5 C6 C7
10µF 0.1µF 0.1µF 0.1µF 0.1µF
Rev. F | Page 19 of 21
ADL5562 Data Sheet
08003-041
08003-042
Figure 46. Layout of Evaluation Board, Component Side Figure 47. Layout of Evaluation Board, Circuit Side
Rev. F | Page 20 of 21
Data Sheet ADL5562
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10 0.30
3.00 SQ 0.23
PIN 1 2.90 0.18
INDICATOR PIN 1
13 16 INDICATOR AREA OPTIONS
0.50 (SEE DETAIL A)
BSC 12 1
1.75
EXPOSED
PAD 1.60 SQ
1.45
9 4
02-23-2017-E
PKG-005138
ORDERING GUIDE
Temperature Package Ordering
Model 1 Range Package Description Option Branding Quantity
ADL5562ACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel CP-16-22 Q1Q 1,500
ADL5562ACPZ-WP −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP], Waffle Pack CP-16-22 Q1Q 50
ADL5562-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.
Rev. F | Page 21 of 21