Birla Institute of Technology and Science – Pilani

Pilani | K.K. Birla Goa | Hyderabad

First Semester 2018-2019

CS G553-Reconfigurable Computing
Component: Regular (Closed Book)
Duration: 180 min Comprehensive Examination Max. Marks: 35

Instructions: Make suitable assumption and justify if required.

Q1. Table shows the wire capacitance values for a 90 nm process. Find the Elmore delay for a
minimum-width metal1 wire of length 4000µm using 8 sections.
Note: 1 x 10-18 farad = 1 attofarad [02]

Layer Capacitance to ground Coupling capacitance Resistance /length

Metal 1 76 (aF/ µm) 36 (aF/ µm) 0.03 (Ω/ µm)

Q2. Show the hardware implemented by synthesizing the following code: [02]
a. always @(posedge CLK ) b. always @(posedge CLK )
begin begin
a<=b; a=b;
b<=a; b=a;
end end
Q3. Why partitioning and decomposition are the essential pre-processing steps in library based
technology mapping [01]
Q4. What are called communication memory? Where they can be present? [01]
Q5. Compare general high level synthesis with the reconfigurable system synthesis [01]
Q6. Mention the variations in packing problems? Which one is useful for temporal placements? [01]
Q7. What is a block reconfigurable device? [01]

Q8. Use multilevel logic manipulation to reduce the circuit size of the switching function given
below, at the expense of perhaps slower performance. Use this circuit outcome to compare the
tradeoff of the two level and multilevel size-optimized circuits. [03]

Q9. Consider the 2 bit comparator shown in figure-1, Draw OBDD for the variable ordering f(a1; b1;
a2; b2), and also draw the resulting ROBDD. [03]

Figure-1
Q10. Given the circuit and the configurable logic block (CLB) shown in figure-2, partition the circuit
so that it can be implemented with a collection of CLBs. Try to use the least possible number of
CLBs. Indicate your answer by filling in the table: one row per CLB used; for the configuration bit,
s, write in a “0” or “1”, for all other columns write in the name of the signal wire from the logic
circuit that corresponds to the CLB input or output, a “0” or “1”, or “nc” for no connection. You
may leave some rows blank or add rows. [05]

Figure-2
Q11. Consider the following multi-level, multiple input single output (F) logic network,

t1 = d + e;
t2 = b + h;
t3 = at2 + c;
t4 = t1t3 + fgh;
F = t4’;

(a) Develop the subject graph using base functions

(b) Using the dynamic programming approach, map the circuit using the library shown in
figure-3 (cost associated with each cell is also indicated) into the minimum area cost
solution. Present the solution in tabular form as discussed in lecture. [02+04]
 Figure-3: library cells with the area cost

Q12. FlowMap [07]

(a) Name the two phases of the FlowMap LUT-Technology mapping algorithm.

(b)For the graph with the given cut shown in Figure 4, determine the

i. node cut-size, iii. minimum value of the feasible cut

ii. edge cut-size, iv. and height of the cut.

(c) Why N t' ''

is transformed into a new graph N t ? (Give very specific answer), Justify your answer
using figure-4.

(d)Compute the label for the node ”t” in the Boolean network represented by the graph shown in
Figure-5 using FlowMap algorithm.(Assume K = 3)

Figure-4
 Figure-5

Q13. Discuss the advantages and disadvantages of the following temporal placement methods
(i) Keeping All Maximum Empty Rectangles

(ii) Keep only the non-overlapping empty rectangles [02]