NAME: T YOGA UJWALA

REGISTRATION NUMBER: 17BEC0577

SUBTASK -1
NEGATIVE EDGE TRIGGERED D-FLIPFLOP

AIM:
To design the schematic of negative edge triggered D-FF and check the functionality of the
resulting output waveform.
To calculate the average power dissipation and average time delay of the output waveform.

CIRCUIT DESIGN:

1) When load capacitance C = 200 fF

 Output waveform of a D-Flipflop

Plot of Power signal and average power dissipation

2) When load capacitance C = 400 fF

Plot of output waveform and power signal

 Average Power dissipation

Results and Tabulation:

tCQr tCQf Average power

200fF 0.928ns 1.23ns 1.622 e-6 W

400fF 1.0818ns 2.437ns 3.05 e-6 W

INFERENCE:
The schematic of D-Flipflop is designed, the required waveforms are analysed and the average time
delay is calculated.

SUBTASK – 2
CMOS FULL ADDER CIRCUIT
AIM:
To design the schematic of CMOS Full Adder circuit and check the functionality of the
resulting output waveform.
To calculate the average power dissipation and maximum average time delay of the output
waveform.
CIRCUIT DESIGN:

RESULTS:
Plot of sum and carry waveforms
 Plot of power signal

Average Power dissipation

Table for calculating fall time:
a b c tpdf
0 0 1 -> 0 tcs=0.0358ns
1 1 1 -> 0 tcs=0.0384ns
1 -> 0 0 -> 1 0 ->1 tcs=0.0616ns
tbs=0.0616ns
tas=0.0606ns
1 0 1 -> 0 tcs=0.0631ns

Table for calculating rise time:

a b c tpdr
1 0 1 -> 0 tcs=0.0631ns
0 -> 1 0 -> 1 0 ->1 tsc=tsb=tsa=0.0266ns
0 1 1 -> 0 tsc=0.06601ns

Average Power dissipation = 558.1 e-9 W

INFERENCE:
Hence the schematic for CMOS full adder is designed using some created symbols like
inverter and all the required waveforms are plotted and analysed.