MOSFETs and CMOS Gates

1. MOSFET operation
2. Qualitative MOSFET model
3. CMOS Gates

Hey, that’s a
transistor!

Handouts: Lecture Slides

1
 We Want to Build One of These …

Static Voltage Transfer Curve In Out

VOut

Static discipline forbids

VOH curve from passing
through shaded regions
VIH

Need both:
VIL 1. Gain
VOL 2. Non-linearity
VIn
VOL VIL VIH VOH
2
 MOSFET
gate
source
Polysilicon wire

Inter-layer SiO2 insulation

Heavily doped (n-type or p-type) diffusions
W
Very thin (<20Å) high-quality SiO2
insulating layer isolates gate from channel L
region.
drain

Channel region: electric field from charges on

gate locally “inverts” type of substrate to create
a conducting channel between source and drain.
bulk Doped (p-type or n-type) silicon substrate

MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are four-

terminal voltage-controlled switches.

Current flows between the diffusion terminals if the voltage on the gate
terminal is large enough to create a conducting “channel”, otherwise the
diffusion terminals are not connected.
3
FET Under Gate Bias
+ mobile holes
- mobile electrons
G immobile acceptors
S D + immobile donors
+ n+ + + + n+ +
+ + +
Depletion layer
+ + + + + + + +
p substrate VGS < VTH
Cutoff region

G
S D
+ n+ n+ +
VGS ≥ VTH
+ + +
+ + + + + + + +
Inversion layer
p substrate forms
4
“Linear” Operating Region

VGS VDS
G VGS ≥ VTH
S D
VGS – VTH > VDS
+ n+ n+ +

+ + + Current flows from

+ + + + + + + + drain to source
+ +
p substrate
Larger VDS increases IDS
Larger VGS creates deeper channel which increases IDS
IDS proportional to µ0(W/L)
IDS
Increasing
VGS

VDS 5
Saturated Operating Region

VGS VDS VGS ≥ VTH

G VGS – VTH = VDS
S D
+ n+ n+ +

+ + + Why is the depletion layer

+ + + + + + deeper near the drain?
+ +
p substrate Inversion layer is
pinched off near the
drain

Voltage difference across the channel remains VGS – VTH

even with increased VDS

6
Saturated Operating Region - 2

VGS VDS
G
S D
+ n+ n+ +
Inversion layer is
+ + + pinched off at the drain
+ + + + + +
+ + VGS ≥ VTH
p substrate

To the first order, once VDS ≥ VGS – VTH , IDS does not increase

VDS = VGS – VTH

IDS
Increasing VGS

VDS
7
Channel Length Modulation Effect

VGS VDS
G
S D VGS ≥ VTH
+ n+ n+ +
VDS ≥ VGS – VTH
+ + +
+ + + + +
+
δL
L

Increased VDS results in effective channel length decreasing,

i.e., δL getting larger, which increases IDS
VDS = VGS – VTH
IDS
Increasing VGS

VDS 8
 NFET Summary
D D +
G
S D
G G VDS ≥ 0
+ n n
p
S - S -
VGS
0.8V
cut-off:
VGS < VTH S D IDS

linear: linear saturation

VGS ≥ VTH S “ ” D
VDS < VDsat VGS
VGS – VTH
saturation:
VGS ≥ VTH S D
VDS ≥ VDsat VDS

9
 6.002 vs. 6.004

IDS linear saturation VTH = 0.8V L = 5 µ m

VGS = 4V Quadratic dependence
on VGS
VGS = 3V No dependence on VDS
VGS = 2V in saturation region

VGS = 0.5V Low subthreshold

6.002 SCS/SU Models VDS conduction

IDS VTH = 0.8V L < 0.5 µ m

linear saturation Linear dependence on VGS

VGS = 4V
VGS = 3V Linear dependence on VDS
in saturation region
VGS = 2V
VGS = 0.5V Significant subthreshold
VDS conduction 10
 FETs come in two flavors

By embedding p-type source and drain in a n-type substrate, we can fabricate a

complement to the N-FET:
S D G
B S D

n n p p
n
p p

D S

G G

S D

The use of both NFETs and PFETs – complementary transistor types – is a key
to CMOS (complementary MOS) logic families.
11
 PFET Summary

S -S +
VGS B S D
G G VDS ≤ 0 p p
+
n
p
D D -

–0.8V
cut-off:
VGS > VTH S D -VDS

linear: -VGS
VGS ≤ VTH S “ ” D
VDS > VDsat
VGS – VTH saturation linear
saturation:
VGS ≤ VTH S D
-IDS
VDS ≤ VDsat
12
 CMOS Inverter
IPU

power supply VIN = 0v

S VIN = 1v
G VIN = 2v
IPU VIN = 3v
D VIN = 4v
Vin Vout
D IPU vs VOUT for Pullup PFET VOUT
IPD IPD
G
S = 0V
VIN = 5v

VIN = 4v
VIN = 3v
VIN = 2v
VIN = 1v

IPD vs VOUT for Pulldown NFET

VOUT
13
 CMOS Inverter VTC
Ipu Steady state reached
Vin = 0.5V
when Vout reaches value
Ipd
Ipu where Ipu = Ipd.
Ipd
Vout
Vout
VOH Vin = 3.5V

Ipd
Vin = 1.5V Ipu
Vout
Ipu

Ipd
Vout Vin = 4.5V
VOL Ipd
Vin Ipu
Vin = 2.5V VIL VIH
Vout
Ipu Ipd
What produces the “flat” parts of the curve?
Vout What produces the “steep” part of the curve?
14
 Think Switches
VDD
pullup: make this connection
when VIN near 0 so that VOUT = VDD

VIN VOUT

pulldown: make this connection

when VIN near VDD so that VOUT = 0

L H H L

VIN ≤ VIL VOUT ≥ VOH VIN ≥ VIH VOUT ≤ VOL

15
CMOS Complements What a nice
VOH you have...

Thanks. It runs
in the family...
conducts when VGS is high conducts when VGS is low

A
A B
B

conducts when A is high conducts when A is low

and B is high: A.B or B is low: A+B = A.B

A
A B
B

conducts when A is high conducts when A is low

or B is high: A+B and B is low: A.B = A+B 16
Logic Functions

A B F NAND gate
F 0 0 1
A 0 1 1
1 0 1
1 1 0
B

A B F NOR gate
0 0 1
0 1 0
F 1 0 0
A B 1 1 0

17
 Combinational Devices

A combinational device is a circuit element that has

– one or more digital inputs
– one or more digital outputs
– a functional specification that details the value of
Static each output for every possible combination of
discipline valid input values
– a timing specification consisting (at minimum) of
an upper bound tPD on the required time for the
device to compute the specified output values
from an arbitrary set of stable, valid input values

input A If C is 1 then copy A to Y,

otherwise copy B to Y
input B output Y
I will generate a valid
input C output in no more than
2 weeks after
seeing valid inputs

18
Signal Timing: Propagation Delay

Propagation delay tpd is upper bound between

new valid inputs and new valid output
VIn

tpd includes
time required
for transistor
t to turn on/off

VOut ≤ tpd

t
≤ tpd 19
Signal Timing: Contamination Delay

Contamination delay tcd is lower bound

between invalid inputs and invalid output
VIn

≤ tpd ≥ tcd
VOut

t
≥ tcd
20
 Timing Analysis

B
Logically valid A, B Æ Logically valid C (static discipline)

tpd = 5 tcd = 1 for each NAND gate

Over all input combinations, over all input-output paths

What is the propagation delay for the circuit?

What is the contamination delay for circuit?
21
 Combinational Contract Summary

AB tPD propagation delay

A B 01 tCD contamination delay
10

A
B

Must be ≥ tCD

Note: Must be ≤ tPD

1. No Promises during
2. Default (conservative) spec: tCD = 0
22