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Model Examination
Sub. Code & Name : EE8351 / Digital Logic Circuits Date : -10-2018
Class : II Year / III Sem. Time : 03:00 Hours
Max. Marks : 100 Marks
PART - A (10X02=20)
Answer all the Questions
(or)
(b) i) Design half and full subtractor and realize using logic gates. (13)
15 (a) Explain in detail the concept of behavioral, structural modeling in VHDL for full adder. (13)
(or)
(b) Explain in detail the concept of behavioral, structural modeling in VHDL for 8x1 MUX. (13)
PART - C (1X15=15)
16 Design an asynchronous sequential circuit with two inputs X1 and X2 and one output Z.
initially Z=0 both inputs are equal to zero. When X1 or X2 becomes 1 the output Z becomes
1.When second input also one, the output changes to zero. The output say at 0 until the
circuit goes back to the initial state.
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