A High Performance Inverter Technology,
Architecture and Applications
S.D. Finn, Maitec Pty. Ltd.,
Castle Hill, Sydney, Australia. 2154
Abstract - A high performance inverter technobgy with
unusually high flexibility is presented. Cascade control loops
and the application of feedforward compensation provide
capabiities that are exploited successfully in a wide range of
applications. Using an intermediate high voltage DC bus and
transformerless inverter, the architecture provides near ideal
output performancecombining high bandwidth and low output
impedance.
I. Introduction
Traditional inverter architectures are typically
designed and developed to provide a specified level of
performance to a given load. The design process
usually takes advantage of any load characteristicsthat
simplify the design process and reducethe productcost.
The result of this approach is a lower cost product
performing adequately for the target load, but with little
flexibility in application.
The architecture discussed here was developed to
power any given load to an exceptionally high level of
performance. As originally designed, the inverter was
intended to provide a 24OVac sinusoidal output voltage
in a UPS for the commodity market where the load
characteristicsare totally unknown. However, due to the
modular nature of the resulting design, the architecture
has since found application in many other areas.
II. Power Electronic Architecture
The architecture is composed of two power
processing stages (Figure l ) ,a Booster and an Inverter.
Incoming mains is rectified to provide a 340 Vdc nominal
bus, which the Booster converts, through a high
frequency transformer, to provide a tightly regulated
420Vdc bus with 1500Vrm isolation to earth. The
420Vdc bus is used by the transformerless Inverter to
provide a pulse width modulated waveform which is
passedto a symmetricallow pass LC filter to providethe
output.
W V k
Fig. 1 Power Electronic Architecture
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0-7803-0982-0193 $3.00 1993 IEEE
A. Booster Detail
The Booster input DC is processed by a l.lkW
25kHz MOSFETfull bridgeconverter(FigureP),through
a high frequency transformer, to multiple secondary
rectifiers.The secondary rectifiers stacked in series are
fed to a single inductorkapacitor low pass filter. The
input voltage range of this converter is 160Vdc to
400Vdc, permitting operation from a mains supply of
140 Vms to 275 VW. The output voltage is regulated to
420Vdc +-0.5% over the full input voltage and output
current range. Voltage, current and transformer flux
feedback are provided with custom designed
transformer coupled sensors.
Fg. 2 Booster Detail
If required, a 96V& nominal battery can be connected
via a diode to a centre tap on the Booster transformer,
with the battery negative commoned to the rectified
mains supply negative rail. Alternatively, a 192Vdc
nominal battery can be connected via diode directly
across the rectified mains supply. When the rectified
mains voltage decays during a mains failure, the
Booster input voltage falls until the battery diode
becomes forward biased and then the load energy is
drawn from the battery. During battery operation, the
connection of the battery to the transformer centre tap
provides a voltage doubling effect, permitting the
booster to operate as if a battery of twice the voltage is
applied normally to the bridge. The Booster input
voltage minimum is sufficient to allow for the battery
80Vdc or 160Vdc end of discharge voltage without
compromising the Booster performance.
B. lnverter Detail
The Inverter stage (Figure 3) is a 1.5kVA 25kHz
MOSFET full bridge, transformerless converter, which
processes the 420Vdc Booster output voltage using
pulse width modulation techniques to produce a
240Vac output. Since the Inverter is not isolated, the
Booster output 420 Vdcbus has acommon mode voltage
component at the modulation frequency of the Inverter.
The low pass output filter is comprised of two inductors,
one in each Inverter output leg, and a capacitor. By
removing the isolation and voltage transformation from
the inverter, the inverter performance is considerably
enhanced, permitting DC coupling, greater bandwidth
and lower output impedance. One leg of the inverter
output is earth referenced at the capacitor, permitting
the control electronics to be at earth potential, and
permitting current sensing via an earth referenced
resistor.
Fig. 3 Inverter Detail
Ill. Inverter Control Architecture
The control methodology is based upon two cascaded
control loops (Figure 4) feeding a traditional, constant
frequency, ramp comparison, PWM modulation stage.
An inner proportionaVintegral current control loop is
supplied with a current reference voltage and current
feedback voltage to produce a current error signal. This
current error signal is fed directly to the PWM
modulation stage. A feedforward signal from the module
output voltage is added to the current reference signal
to ensure linearity during massive load changes. This
loop therefore functions as a linear transconductance
amplifier.
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I V I I
FQ.4 Cascade Control Loops
The outer proportionaVintegral voltage control loop is
supplied with a voltage reference and voltage feedback
to produce a voltage error signal. The voltage error
signal is limited by diode clamps and fed to the current
control loop as a current reference signal. Current
limiting of the module is controlled by varying the
clamping limits of the current reference signal. The
voltage feedback signal is derived from a resistive
attenuator with DC blocking capacitor, providing no
attenuation at DC with a roll-off at 1Hz.
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A. Current Loop Compensation
With the PWM modulation operating open loop, the
limit of excursion of the modulation ramp is 3Vpp,
providing a useable output voltage excursion of
800Vpp before the filter, giving a voltage gain of 267.
Attempting to use the full rail to rail voltage of 84OVw
results in unacceptable non-linearities which degrade
the performance.
The feedback amplifier is required to be PI in order to
cater for loads sensitive to DC currents (ie.
transformers, etc). Keeping the feedback voltage to the
summing junction at 3V for a 12.5A output (to ensure
low THD in the op-amp stages), the feedback gain is
lout /4.17. The output current is sensed by a 25mR
resistor and conditioned by a differential amplifier, even
though the resistor is earth referenced, to avoid
common mode voltages caused by earth currents.
Z/= 2 m xf x2.2mH (1)
Vprsfilter (3)
lout =-
21
lout
vir=- 4.1 7
- 267x We,,
-
2 m xf x2.2mH x4.17
= 4.64 x~o~~-
h t 7 (4)
f
deriving the required gain:
- 4.64 x l O3 (5)
- f
Assuming that the unity gain frequency is
considerably greater than the filter break point (ie. the
filter is 2.2mH inductive only), the current loop gain is
given by (5). To establish the desired unity gain point of
5.6kHz (derivedfrom the design goal of current amplifier
bandwidth and low enough that modulation effects do
not cause problems), the amplifier forward gain Ai is
0.829. To establish the integral transfer function, a pole
is added at 418Hz, considerably below the filter break
frequency of 1.2kHz. The effects of this compensation
at the unity gain frequency are minimal, justifying their
exclusion from the calculations.

B. Current Amplifier Response
The current amplifier exhibits a flat response to within
3dB from DC to 5kH2, and provides extraordinary
linearity for currents up to the maximum reference
values. The output impedance per 1.5kVA of rating has
a value at 50Hz of 680R,a minimum of 80R at 1Wz,
and approaches 40 KR at DC (Figure 5).
Fig. 5 Current loop output impedance
C. Voltage Amplifier Compensation
Assuming an ideal inner current loop with a small
signal transconductance of 4.17, the output impedance
is primarily capacitive (8pF). NB:The filter inductanceis
controlled by the current stage such that under linear
conditions these elements are absorbed into the current
loop and do not appear as passive components in the
filter. The feedback amplifier is required to be PI in order
to cater for loads sensitive to DC voltages (ie.
transformers, etc). Keeping the peak feedback voltage
to the summing junction at less than 3.8Vp for a 340Vp
output (to ensure low THD in the op-amp stages), the
feedback gain is Vout/90.The output voltage is sensed
by a ground referenced resistive divider.
1
zc =
2m x f x8 xl O4
lout = 4.1 7XVIm,
Vout = lout x z c
Vout
Vvf =-
90
4.1 7 x V ~
- (9)
2 m xf x8 xl 04x90
deriving the required gain:
A"=-
vir
- 9.22xl O2
- f
~
The voltage loop gain is given by (10). To establish a
unity gain frequency equal to the inner current loop unity
gain frequency of 5.6kHz (providing the greatest closed
loop bandwidth with an acceptable phase margin), the
amplifier forward gain AV is 0.165. A transfer function
pole is added at 130Hz in addition to adding a DC
blocking capacitor to the voltage feedback divider with
a roll-off at 1Hz. These two measures reduce op-amp
offset effects, and ensure that the output DC voltage
component does not exceed 1OmV. In order to lower the
output impedance in the power frequency range of
interest (40-70Hz),an additionalpolehero pair is added
at 100Hz/500Hz, providing a 10 times gain boost.
D. Large Signal Instability
In actual usage, a voltage loop instability at the
frequency of lowest phase margin (2kHz) exists when a
short circuit is removed, due to saturation of the current
loop amplifier. Before removal of the short circuit, the
current loop error is small, as the current reference and
current feedback signals are of similar magnitude. After
removal of the short circuit, the stored energy in the
output inductor and the high bandwidth of the voltage
control loop drives the current error signal to the
opposite polarity faster than the output current (and
therefore current feedback signal) can follow, causing a
massive current error signal, saturating the amplifier.
One method of controlling saturation of the amplifier
is to detect when the current error signal exceeds the
bounds of the PWM comparisonramp, and apply a large
negative feedback to the voltage reference input to drive
the current error signal out of saturation. In a multiple
parallel stage system, such instability only occurs if all
current amplifiers are saturated, as any one current
amplifier operating linearly is sufficient to damp all the
others. Therefore, the additional negative feedback
should only be triggered when all amplifiers are
saturated, to prevent output degradation during a
(7) recoverable transient.
( 8 ) E. Feedforward Compensation
An alternative method of providing this protection is
to provide feedback to the current referencesignal from
the output voltage, and change the current loop to a P
only type. The amount of feedback is dimensioned to
ensure that under the worst case conditions of error,
sufficient feedback exists to drive the current error to
within the linear region of the amplifier, so ensuring a
recovery from the transient.
Under linear operating conditions, this feedback is
positive and hence appears as a feedforwardterm in the
system transfer function. However, the magnitude of this
( 1 0) feedforward term is sufficiently small under normal
operating conditions that the voltage control loop can
compensate without compromising system
performance (ie. the feedforward term appears as a
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small disturbance input). In a situation of parallel power
stages, the presence of the feedfoward term can cause
an increased circulating current due to imperfect
matching of the feedfoward terms between individual
current loops.
F. Voltage Amplifier Response
The output voltage loop, cascaded with the inner
current amplifier, exhibits a flat response to within 3dB
from 1OHz to 2kHz. The output impedance per 1SkVA
of rating has a value at 50Hz of 0.38R,a peak of 2R at
2kHz, and approaches lOmR at DC (Figure 6).
io
I
0.01
1 Frrqm-w W1
Fig. 6 Voltage loop output impedance
IV. Paralleling Modules
As can be seen from the voltage loop unity gain
calculations, if the ratio o f current loop
transconductance and output capacitance remains
constant, the voltage loop compensation remains
unchanged for different output ratings (providedthat the
filter break point frequency and current loop gain and
phase profiles are unchanged). Therefore, the product
rating may be scaled by adding parallel current loops
and power stages (Figure 7), each with a rating of
1.5kVA as described above. Further, stages of smaller
or larger rating may be used provided the filter and
current loop transconductance are scaled appropriately.
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I 1
- -1 VIC
By exploiting the cascaded control loops, and placing
an arbitrary number of transconductance amplifiers
under the control of a single voltage loop, a scalar
architecture results. By designing the voltage
compensation to be independent of the number of
current stages and exporting the current reference
~
signal to each module, the architecture allows modular
expansion, on-line module change and the provision of
additional redundant modules.
A. Portable Current Reference.
The voltage errorkurrent reference signal is shared
between modules by bufferingand distributingthe signal
as a balanced pair. As the current reference (voltage
error) signal provides for a bandwidth of 5kHz, and
25kHz phase information is present, the bandwidth
required of the signal distribution network needs to be
greater than 1OOkHz.
Each module then uses a high CMRR instrumentation
amplifier to re-createthe current referencesignal within
each module. System current limiting is performedprior
to distribution of the current reference signal, permitting
each module to be sized differently as the voltage loop
compensation is unitised with respect to the
transconductance of each module. This technique has
ioomo been shown to be robust and works well even in noisy
environments.
B. Inherent Sharing
Since each module is fed the same current reference
signal, each module provides output current in
proportion to its transconductance, and therefore rating.
At no load, a circulating current of approximately 5% of
rating exists between modules due to accumulated
errors in the reference distribution. At percentage
loading greater than 5%, theseerrors are swamped, and
the circulating current becomes negligible.
C. Failure Detection
Modules may also contain additional circuitry which
compares the current reference signal and actual
module output current to determine if the module is
faulty. If the error signal resulting from the comparison
is small, the module is working correctly. Any significant
error is detected and indicates that the module has a
fault. Any faulty modules are automatically shutdown,
and have their Inverter output disconnected via a fast
II acting relay.
D. Voltage Loop Response to Lost Stage
In the event of a module failing, the voltage
errorkurrent reference signal increases to correct the
instantaneous system voltage. However, the energy
storage present in the distributed output filter provides
sufficient buffering for the cascaded control loops to
correct the error within their respective bandwidths,
resulting in an immeasurable transient at the moment of
failure. Figure 8 is an oscilloscope photograph of the
system response to a single module failure in a fully
loaded 4.5kVA UPS with one redundant module.
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 VII. Inverter Specifications

Input voltage 140 Vac to 275Vac

40Hz to 400Hz,
80 Vdc to 390 W ~ C

Output power 1.1kW /1.5kVA modules

Output voltage/current 240 Vnns/6.2Ams,

4-340 V,l3.2Ap,
short circuit proof

Output impedance e 2f2 per module

... ... 0.38R @ 50Hz

Frequency response 1OH2 - 2kHz (-3dB)

arbitrary waveshape
Fa. 8 Voltage (lOOV/div), module current (5Ndiv)
Gain inverting, 100
E. Fault tolerance capability
Since the system providesfor any number of modules Technology 25kHz switchmode,
to be present, the provisionof a minimum of one module Pulse Width Modulation,
more capacity than the load requires permits any single convection cooled
module to fail without compromising the system
Efficiency > 82%
performance. Further, although the likelihood of module
failure is comparatively high due to the high component Switching noise
count, the system availability is greatly enhanced. The on output 1 Vpp @ 25kHZ
provision of a single redundant module in any system
(n>l), assuming a MTTR to one week with on-line Distortion 0.5% THD
maintenance, provides a system MTBF effectively
independent of the module failure rate, and determined
by the MTBF of the system supervisory components.

V. Applications
This architecture has been exploited successfully in
a range of UPS products from 500VA to 12.5kVA,
providing very high performance with the system
availability necessary for mission critical applications.
Since the inverter provides the characteristics of an
almost ideal low frequency power amplifier, it has found
uses as an arbitrary waveshape generator for power
supply testing, and a variable frequency AC supply for
general usage.

Potential applications include usage as a power

amplifier in geophysical surveys, vibration test
equipment, subsonic amplification for structuraltesting,
low frequency audio amplification, and active
waveshape correction of poor power factor industrial
loads.

VI. Acknowledgements
The work detailed in this paper is the result of the
dedication and effort of a large number of people over
several years. In particular, the author wishes to thank
Greg Hunter, Richard Harrowell and Hurriyet Baykan.

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