Analog Electronics Circuits Lab 18ECL37

EXPERIMENT No. 1:

RECTIFIER CIRCUITS

AIM: Conduct an experiment for Half wave rectifier and Full wave rectifier with and without filter
and measure the ripple factor.

COMPONENTS / APPARATUS REQUIRED:

Required material Specification Qty

Bread board 1
CRO 20/30MHz 1
Diodes IN4007 4
Resistors 50/5W 1
Capacitors 100µF 1
Transformer 9V – 0 - 9V 1
DRB 1

1) HALF WAVE RECTIFIER

CIRCUIT DIAGRAM:

Fig 1.Without Filter

Analog Electronics Circuits Lab 18ECL37

Fig 2. With Filter

THEORY:

In Half wave rectifier, rectifying element conducts only during positive half cycle of input
AC supply. During the positive half cycle the diode is forward biased and the current flows in the
circuit in the clockwise direction. During negative half cycle diode becomes reverse biased w.r.t the
input voltage, hence no current flows in circuit .Thus the circuit current, which is also the load
current is in the form of half sinusoidal pulse.

OBSERVATION TABLE:

(V dc) NL= Volts, RF = Ω

RL Vm V dc V rms Ripple % P dc P ac %
Ω Volts Volts Volts Factor Regn Watts Watts η
γ
1K
5K
10K

RL Ω Vshift Vr Vripple Vdc γ prac γ theo

ripple (filter) (filter)
1K

5K

10K

FORMULAE USED:
1) V dc = Vm / π
2) V rms= Vm / √2
3) Ripple Factor γ (without filter) = Vac / Vdc = √[ (V rms/ V dc)2 – 1]
4) % Regn = {(V dc)NL - (V dc)FL / (V dc)NL} X100
5) P dc= V dc2/ RL
6) P ac = V rms2/ (Rf +RL)
7)% η = (P dc / P ac)X 100
8) Ripple Factor (with filter) γ theo= 1/ 2√3 fC RL
Analog Electronics Circuits Lab 18ECL37

9) Vripple= Vr/ 2√2

10) (Vdc) ripple = Vshift + Vr/2
11) Ripple Factor (with filter) γ prac = Vripple/ Vdc

EXPECTED WAVEFORM:

Vi

t sec

Vo

t sec
Fig 3: Input & Output waveforms

PROCEDURE:

1) Check the diode forward resistance (Rf) using a multimeter and note it down. (Default = 30 Ω).
2) Make the connections as per the circuit diagram (Initially do not connect the 50 Ω and DRB).
Analog Electronics Circuits Lab 18ECL37

3) Measure DC voltage at the output terminal using multimeter.This is the (V dc) NL

4) Now connect the RL (50 Ω and DRB).
5) Vary DRB from 1KΩ to 10KΩ in steps of 5K. Note the peak voltage Vm on the CRO for each
step.
6) Calculate the ripple factor, %regulation and % efficiency using the formulae given.
7) Connect the capacitor across the load.
8) Now again for different load, calculate ripple factor.
9) Trace the output waveforms on a graph sheet in both cases.
Analog Electronics Circuits Lab 18ECL37

2) FULL WAVE RECTIFIER

CIRCUIT DIAGRAM:

Fig 4. Full wave rectifier without Filter

Fig 5. Full wave rectifier with Filter

THEORY:

The full wave rectifier conducts during both positive and negative half cycles of the input ac supply.
In order to rectify both the half cycles of ac input, two diodes are used. In the positive half cycle, the
Analog Electronics Circuits Lab 18ECL37

diode D1 will be forward biased and hence will conduct, diode D2 will act as open circuit. In the
negative half cycle, the diode D2 will be forward biased and hence will conduct diode D1 will be
reversed biased & it act as open circuit. Thus the full wave rectifier Circuit essentially consists of
two half wave rectifier circuits working independently of each other but feeding a common load. The
output load current is pulsating DC.

OBSERVATION TABLE:

(V dc) NL= Volts, RF = Ω

RL Vm V dc V rms Ripple P dc P ac %
Ω Volts Volts Volts Factor Watts Watts η
γ
1K
5K
10K

RL Ω Vshift Vr Vripple Vdc γ prac γ theo

ripple (filter) (filter)
1K

5K

10K

FORMULAE USED:

1) V dc = 2Vm / π
2) V rms= Vm /√2
3) Ripple Factor γ (without filter) = Vac / Vdc = √ (V rms/ V dc) 2 – 1
4) % Regn = (V dc)NL - (V dc)FL / (V dc)NL X 100
5) P dc= V dc2/ RL
6) P ac = V rms2/ (Rf +RL)
7)% η = (P dc / P ac)X 100
8) Ripple Factor (with filter) γ theo= 1/ 4√3 fC RL
Analog Electronics Circuits Lab 18ECL37

9) Vripple= Vr/4√2
10) (Vdc) ripple = Vshift + Vr/2
11) Ripple Factor (with filter) γ prac = Vripple/ Vdc

EXPECTED WAVEFORM:

Vi

Vo
Vo Volts

Vi.Volts

Vo 1Vp-p
Vi.1Vp-p
Case 1
Analog Electronics Circuits Lab 18ECL37

Fig 6: input & output waveforms

PROCEDURE:

1. Check the diode forward resistance (Rf) using a multimeter and note it down. (Default = 30 Ω).
2. Make the connections as per the circuit diagram (Initially do not connect the 50 Ω and DRB).
3. Measure dc voltage at the output terminal using multimeter. This is the(Vdc)NL.
4. Now connect the RL (50 Ω and DRB).
5. Vary DRB from 1KΩ to 10KΩ in steps of 5K. Note the peak voltage Vm on the CRO for each
step.
6. Calculate the ripple factor, %regulation and % efficiency using the formulae given.
7. Connect the capacitor across the load &again for different load, calculate ripple factor.
8. Trace the output waveforms on a graph sheet in both cases.

RESULT:
The half wave and full wave and bridge rectifier circuits are verified. Ripple factor, with and without
capacitor filter were measured. Ripple with capacitor filter was found to be less. The output
waveforms with and without filter are plotted on graph.

HWR FWR
Ripple Factor γ

% Efficiency % η

Ripple Factor (filter) γ

VIVA QUESTIONS:
Analog Electronics Circuits Lab 18ECL37

1. What is Rectification? Why it is necessary?

2. What is a Rectifier? How many types of rectifiers are there? Explain the working of each.
3. Differentiate Full wave rectifier & Center tap Transformer rectifier.
4. What is a ripple factor?
5. Define Line and Load regulation?
6. Define efficiency. Write the theoretical efficiencies of half wave and Full wave rectifier.
7. What do you mean by Avg value, RMS value, and peak value?
8. What is a Filter? Why it is required?
9. Explain the working principle of HWR, FWR, and BR with capacitor filter & write the
expressions of ripple factor, dc o/p voltage, diode current.
10. What are the different types of Filters?
11. Define α, β, γ .Explain the different applications of Diode.
12. Give a comparative study of all rectifier circuits.
EXPERIMENT No. 2:
CLIPPER CIRCUITS

AIM: To design and test diode clipping circuits for peak clipping and peak detection (both Single
ended and double ended circuits).

COMPONENTS/APPARTUS REQUIRED:

Required material Specification Qty

Bread board 1
CRO 20/30Mhz 1
Power supply DC +/- 12V/0-30V 2
Function Generator 1MHz 1
Resistors 1K, 470 2
Diodes IN4007 2

i) DIODE SHUNT CLIPPING above reference voltage.

(Positive peak clipping)

CIRCUIT DIAGRAM:
Analog Electronics Circuits Lab 18ECL37

THEORY:

Clipper circuits are used to remove the portion of a time varying input signal without
distorting the remaining part of the input waveform.

The circuit is as shown above. During positive half cycle of the input voltage (Vin) till Vin <Vref the
diode will not conduct. But when Vin =Vref, the diode will conduct & Vo=Vd+Vr. Throughout the
negative half cycle the diode is reversed biased and act an open circuit.Therefore Vo =Vin , thus the
waveform is as shown below in fig2.

DESIGN:

Let the output voltage be clipped to say +2.8V i.e. V0 (max) = 2.8V
But V0 (max) = Vdiode + V ref
Vdiode= Diode forward voltage drop=0.7V
Vref=V0(max)-Vd=2.8-0.7=2.1V.
The value of resistor R is chosen to be R= Vi (max) – V0 (max)/ Id
Choose Diode forward current, Id = 1.5mA (Typically between 1mA to 10 mA)
Then R= (4 - 2.8) / 1.5mA = 800 Ω ≈ 1K Ω

TABULAR COLUMN: Vref = 2.1V

Vi(p-p) V0+(p-p) Volts V0-(p-p) Volts

Volts
 Analog Electronics Circuits Lab 18ECL37

1
:
:
:
8

EXPECTED WAVEFORM:

Vo (v) Vin
V0
Vref(v) t
sec
sec
sec
sec

Fig 2: output waveform

Fig 3: Transfer characteristics

i) DIODE SHUNT CLIPPINGbelow reference voltage.

(Negative peak clipping)

CIRCUIT DIAGRAM:
Analog Electronics Circuits Lab 18ECL37

THEORY:

The circuit is as shown above. During positive half cycle the diode will be reversed biased, hence Vo
=Vin. Thus entire positive half cycle is reproduced as it is, when Vin<Vref, the diode becomes
forward biased & hence Vo=-(Vr+Vd).

DESIGN:

Let the output voltage be clipped to say -2.8V i.e V0(min) = -2.8V
But V0 (min) = -(Vdiode + V ref )
Vdiode= Diode forward voltage drop=0.7V
-Vref=V0(min) + Vd = -2.8 + 0.7= -2.1V.
The value of resistor R is chosen to be R= Vi (max) – V0 (min)/Id Choose Diode forward
current, Id = 1.5mA (Typically between 1mA to 10 mA)
Then R= (-4 + 2.8) / -1.5mA = 800 Ω ≈ 1K Ω

TABULAR COLUMN:Vref = - 2.1V

Vi(p-p) Volts V0+(p-p) Volts V0-(p-p) Volts

1
::
:
8

EXPECTED WAVEFORM:
▲
Vo(v)

VV

O
Vin
Analog Electronics Circuits Lab 18ECL37

Vref Vout
-2.8V

Fig 5: output waveform

Fig 6: Transfer characteristics

ii) DIODE SERIES CLIPPING above reference voltage
(Positive peak clipping)
CIRCUIT DIAGRAM:

DESIGN:

Let the output voltage be clipped to say +2.0V i.e. V0 (max) = V ref = +2.0V
The value of resistor R is chosen to be R= Vi (max) – V0 (max)/Id
Choose Diode forward current, Id = 2mA (typically between 1mA to 10 mA)
Then R= (4 - 2) / 2mA = 1K Ω

TABULAR COLUMN: Vref = 2V

Analog Electronics Circuits Lab 18ECL37

Vi(p-p) V0+(p-p) Volts V0-(p-p) Volts

Volts
1
:
:
:
8

EXPECTED WAVEFORM:

Vi
Vo(v)
2V
Vo
t sec

Fig 8: Output waveform

Fig 9: Transfer characteristics

iii) DIODE SERIES CLIPPING below reference voltage

(Negative peak clipping)

CIRCUIT DIAGRAM:
Analog Electronics Circuits Lab 18ECL37

DESIGN:

Let the output voltage be clipped to say -2.0V i.e V0(min) = V ref = -2.0V
The value of resistor R is chosen to be R= (Vi (max) + V0 (min)) / Id
Choose Diode forward current, Id = 6mA (Typically between 1mA to 10 mA)
Then R= (4 + 2) / 6mA = 1K Ω

TABULAR COLUMN:Vref = -2V

Vi(p-p) V0+(p-p) Volts V0-(p-p) Volts

Volts
1
:
:
:
8

EXPECTED WAVEFORM:

Vo (v)
▲

►t sec

-2V
Analog Electronics Circuits Lab 18ECL37

Fig 11: Output waveform

Vo(v)▲

-2V Vi(v)
►

2V

Clipping Transmission

Fig 12: Transfer characteristics

NOTE:

By changing the polarities of Vref in each of the above circuits, we obtain peak detection circuits
instead of peak clipping. i.e.Positive peak clipper becomes negative peak detection circuit also
and Negative peak clipper becomes positive peak detection circuit.
iv) CLIPPING AT TWO INDEPENDENT LEVELS

CIRCUIT DIAGRAM:

DESIGN:

To obtain a slice of input voltage between 1V and 3.5V

Let Vref1 > Vref2
Analog Electronics Circuits Lab 18ECL37

Since V0(max) = 3.5V

But V0 (max) = Vdiode + V ref1
Vdiode= Diode forward voltage drop=0.7V
Vref1=V0(max)-Vd=3.5-0.7=2.8V.
Since V0(min) = 1V
But V0 (min) = Vref2 - V diode
Vdiode= Diode forward voltage drop=0.7V
Vref2=V0(min)+Vd=1 .0 +0.7=1.7V.
The value of resistor R is chosen to be R= (Vi (max) – V0 (max)) / Id
Choose Diode forward current, Id = 1mA (Typically between 1mA to 10 mA)
Then R= (4 – 3.5) / 1mA = 500 Ω ≈ 470Ω.

EXPECTED WAVEFORM:

Vo(v) ▲

Vi
3.5V Vo
1V ►t sec

Fig 14:Output waveform

Vo

3.5V

1V
Vi

Transmission
Clipping Clipping

Fig 15: Transfer characteristics

Analog Electronics Circuits Lab 18ECL37

v) DOUBLE ENDED CLIPPER (Symmetrical square wave generator)

CIRCUIT DIAGRAM:

DESIGN:

To generate a symmetrical square wave of ±3V

i.e. V0 (max) = +3V and V0 (min) = -3V

But V0 (max) = Vdiode + V ref1

Vdiode= Diode forward voltage drop=0.7V
Vref1=V0(max)-Vd=3.0 – 0.7=2.3V.

But V0 (min) = Vdiode + V ref2

Vdiode= Diode forward voltage drop=0.7V
Vref2=V0(min)-Vd=3.0 – 0.7=2.3V.

The value of resistor R is chosen to be R= (Vi (max) – V0 (max)) / Id

Choose Diode forward current, Id = 1mA (Typically between 1mA to 10 mA)
Then R= (4 - 3) / 1mA = 1K Ω.

EXPECTED WAVEFORM:

Vo(v)
Vi
3V
Vo

t sec
Analog Electronics Circuits Lab 18ECL37

-3V

Fig 17: Output waveform

Vo

-3 Vi
3

-3

Fig 18: Transfer characteristics

PROCEDURE: (Same for all the clipper circuits)

1).Rig up the circuit as shown in the circuit diagrams.

2).Apply a sinusoidal signal of 1KHz and amplitude of 8Vp-p ( Peak amplitude should be greater than
clipping level) at input Vi.
3).Observe output signal on the CRO and verify it with the given waveform.
4).Apply Vi and Vo to the X and Y channel of the CRO respectively and transfer characteristics are
obtained using X-Y mode on the CRO.
RESULT: The clipping circuits are designed and output waveforms are verified.

ASSIGNMENT :

1. You are given Sine signal of 1 KHz, 2V. Transmit only the +ve half cycle/Transmit only –ve half
cycle. Now change the Ckt to give output of 1V both at +ve& -ve Cycles.
2. Design and Test suitable Clipper Ckts. To get the following outputs using Sine wave of 5V p-p, 2
KHz Signal.
a) To transmit up to 1.5V in the +ve half cycle, suppressing the –Ve half
To transmit up to 1.5V in the -ve half cycle, suppressing the +Ve half
b) To transmit 1.5V on the top and 3V at the bottom.
VIVA QUESTIONS:
 Analog Electronics Circuits Lab 18ECL37

1. What is a Clipper?

2. List the types of clippers?

3. With a neat circuit and waveforms, Explain the working of various clipping
circuits?

4. What do you mean by double ended clipper?

5. What is biased clipper?

CLAMPER CIRCUITS

AIM:

To Design and test the Clamping circuits for specific needs Positive Clamping / Negative Clamping.

COMPONENTS / APPARTUS REQUIRED:

Required material Specification Qty

Bread board 1
CRO 20/30Mhz 1
Power supply DC +/- 12V/0-30V 1
Function Generator 1MHz 1
Resistors 10K 1
Capacitors 1µF 1
Diodes IN4007 1

i) NEGATIVE CLAMPER

CIRCUIT DIAGRAM:
Analog Electronics Circuits Lab 18ECL37

THEORY:

CLAMPER:The circuits which add a dc voltage to the ac input signal are called clamper circuits.
The clamper circuits are also called as DC restorer or DC inserter circuits.Clampers are classified
into two types:Negative clamper and positive clamper.

DESIGN:

To design a Clamper circuit to clamp negative peak of the output voltage at 3V,
We have Vo (max) = Vref + Vd = 3V
Vref = Vo (max) - Vd
To Clamp Positive peak at +3V, Vref = 3 - 0.7 = 2.3V
Given Frequency = 1 KHz, T = 1 / f = 1ms.
Choose RC >> T (so that tilt in the waveform is negligible, ie, C does not discharge)
Let RC = 10T = 10 X 1ms = 10ms
Choose C = 1µF, R = 10ms/1µ = 10KΩ

TABULAR COLUMN:Vref= 2.3V

Vi(P-P)Volts Vo+(P-P) Volts Vo-(P-P) Volts

6
7
8
9
10
Analog Electronics Circuits Lab 18ECL37

EXPECTED WAVEFORM:

▲
VO▲
4V Vi 4V
Vi

t sec t sec
Vo

3V ---------- Vo

Fig 2: Input & output waveforms

i) POSITIVE CLAMPING

CIRUIT DIAGRAM:

DESIGN: To design a clamper circuit to clamp positive peak at 3V.

We have Vo (min) = - (Vref + Vd)
Vref = -Vo(min) + Vd
Analog Electronics Circuits Lab 18ECL37

Vref = -3 + 0.7 = -2.3V

Given Frequency = 1 KHz, T = 1ms.
Choose RC >> T (so that C does not discharge during positive half cycle )
Let RC = 10T = 10ms
Let C = 1 µF, R = 10ms/1 µ = 10KΩ

TABULAR COLUMN:Vref = -2.3V

Vi(P-P)Volts Vo+(P-P) Volts Vo-(P-P) Volts

6
7
8
9
10

EXPECTED WAVEFORM:

▲
Vo▲ Vo

Vi
Vo

Vi t sec t sec

-3V ---------------

Fig 4: Input & output waveform

PROCEDURE: (Same for both Circuits)

1) Rig up the circuit as shown in the circuit diagram.

2) Input sinusoidal signal of 1 KHz Frequency and amplitude of 8VP-P is applied (Peak amplitude
of input must be greater than clamping level).
3) Display the output on CRO & Compare it with the given waveform.
4) Increase the input further and note that the output peak is clamped to the desired level.
5) For the same circuit, give a square wave input & compare it with the given waveforms.
Analog Electronics Circuits Lab 18ECL37

6) Make Vref = 0V and observe that the corresponding peak is clamped to ±0.7V.
RESULT:
Clamped waveform at desired level is obtained and clamping circuits are studied.

VIVA QUESTIONS:

1. What is a Clamper?
2. List the types of clampers?
3. With a neat circuit and waveforms, explain the working of positive clamper & negative
clamper.

EXPERIMENT No. 3:
ZENER DIODE CIRCUITS
Aim: Characteristics of Zener diode and design a Simple Zener voltage regulator determine line and
load regulation.

Objective:
1. To plot characteristics of Zener Diode in forward and reverse bias
2. To design a simple Zener voltage regulator and to determine line and load regulation.

Apparatus required:

A Zener diode
A DC voltage supplier
Bread board
100Ω resistor
Multimeter for measuring voltage
A DC Ammeter of 0-200mA range
Connecting wires

Theory of experiment:

Zener diode is a heavily doped PN junction diode. Due to heavily doped, its depletion layer is very
thin and is order of micrometer. The forward bias characteristic of Zener diode is same as the normal
PN junction diode but in reverse bias it has different characteristic. Initially, a negligible constant
current flow through the zener diode in its reverse bias but at certain voltage, the current becomes
Analog Electronics Circuits Lab 18ECL37

abruptly large. This voltage is called as zener voltage. This sudden and sharp increase in zener
current is called as zener breakdown.

Circuit Diagram:

Fig 3.1: Zener diode

Procedure (Reverse Bias):

1. Connect the circuit as per the diagram

2. Vary the applied voltage in steps of 1.0 volt.
3. Note down the corresponding Ammeter readings.
4. Plot a graph between output voltage Vz & I

Tabular Column:
Sl. No Voltage Vz in Volts Current I in mA

Expected Waveform:
Analog Electronics Circuits Lab 18ECL37

Fig 3.2: V-I Characteristic Curve for Zener Diode

Procedure (Forward Bias)

1. Connect the Zener diode in forward bias in Figure 3.1

2. Vary the applied voltage in steps of 0.1 volt.
3. Note down the corresponding Ammeter readings.
4. Plot a graph between output voltage Vz & I

Tabular Column:

Sl. No Voltage Vz in Volts Current I in mA

Analog Electronics Circuits Lab 18ECL37

Regulation with a varying input voltage (line regulation): It is defined as the change in regulated
voltage with respect to variation in line voltage. It is denoted by ‘LR’.

Regulation with the varying load (load regulation): It is defined as change in load voltage with
respect to variations in load current. To calculate this regulation, input voltage is constant and output
voltage varies due to change in the load resistance value.

Procedure (Line Regulation):

1. Connect the circuit as per the diagram

2. Vary the applied voltage Vi in steps of 1.0 volt.
3. Note down the corresponding Zener Voltage Vz
4. Plot a graph between output voltage Vi and Vz

Tabular Column:

Sl. No Voltage Vi in Volts Zener Voltage Vz in Volts

Procedure (Load Regulation):

1. Connect the circuit as per the diagram.

2. Connect a load resistance RL (Decade resistance box) in parallel to Zener diode.
3. Set the input voltage Vi at 15 V.
4. Vary the load resistance RL.
5. Note down the corresponding Zener Voltage Vz.
6. Plot a graph between load voltage RL and output voltage Vz .

Tabular Column:

Sl. No Load resistance RL in kΩ Zener Voltage Vz in Volts

Analog Electronics Circuits Lab 18ECL37

Expected Waveform:

Fig 3.3: Line and load regulation waveform

Result:
1. The zener diode characteristics have been studied.
2. The zener breakdown voltage was found to be = ………

Outcome:
Understood the characteristics of Zener diode in forward and reverse bias. A simple Zener regulator
was designed and load and line regulation were determined.

Viva Questions:
1. What is Zener diode?
2. What is Zener current?
3. Give applications of Zener diode?
4. Give advantages of Zener diode regulator over other regulators?
5. Give the voltage range availability of Zener diodes?
6. What is Zener voltage?
7. What is the basic principle of Zener diode?
8. What is Zener break down?
Analog Electronics Circuits Lab 18ECL37

EXPERIMENT No. 4:
STATIC CHARACTERISTICS OF SCR
Aim: To conduct an experiment to plot the static characteristics of an SCR and to find the Latching
current, holding current.

Objective:
1. To plot static characteristics of SCR
2. To find latching current and holding current

Apparatus required:

Sl.
Particulars Range Quantity
No
1 SCR P104X - 1
2 Resistors As per design 2
3 Milliammeter 0-20/200mA 2
Analog Electronics Circuits Lab 18ECL37

4 Multimeter - 1
5 Regulated power Supply (RPS) 0-30V 2

Theory of experiment:

Introduction:
A thyristor is a four layer semiconductor device of PNPN structure with three PN junctions. It has
three terminal anode, cathode and gate. When the anode voltage is made positive with respect to
cathode, the junctions J1 and J3 are forward biased. The junction J2 is reversed biased and, only
small leakage current flows from anode to cathode. The thyristor is then said to be in the OFF mode.
If a Anode to Cathode voltage is increased to a sufficiently large value, the reversed biased junction
J2 will break. This is known as avalanche breakdown and the corresponding voltage is called
forward breakdown voltage VBO. Since junctions J1 and J3 are already forward biased, there will be
free movement of carriers across all three junctions, resulting in a large forward anode current. The
device will then be in a conducting state or on state. The voltage drop would be due to the ohmic
drop in the four layers and it is small, typically, 1V. In the on state, the anode current is limited by an
external impedance or resistance.

Latching current is the minimum anode current required to maintain the thyristor in the on state
immediately after the thyristor has been turned on and the gate signal has been removed. Once the
thyristor is turned on, it behaves like a conducting diode and there is no control over the device. The
device will continue to conduct because there is no depletion layer on the junction J2 due to the free
movements of the carriers. However if the forward anode current is reduced below a level known as
the holding current, a depletion layer will develop around the junction J2, due to reduced number of
carriers and the thyristor will be in the blocking state. Holding current is the minimum anode current
required to maintain the thyristor in the ON state. Holding current is less than latching current. A
thyristor can be turned on by increasing the forward voltage V AK beyond VBO, but such a turn on
could be destructive. In practice, the forward voltage is maintained below VBO and the thyristor is
turned on by applying a positive voltage between its gate and cathode. Once a thyristor is turned on
by a gating signal and its anode current is greater than holding current, the device continues to
conduct due to positive feedback, even if the gating signal is removed.

Circuit Diagram:
Analog Electronics Circuits Lab 18ECL37

Fig 4.1: V-I characteristics of SCR

Procedure:
For V-I Characteristics:

1. Check the components/equipment of their correctness

2. Connection are made as shown in fig. 4.1

3. Both RPS-1 and RPS-2 should be in zero position and the supply switch is ON

4. To find Gate current require to trigger the SCR:

5. Fix the anode voltage VAK around 20V (by using the RPS-2). Increase the gate current
gradually by using RPS-1 until the SCR turn on (VAK meter becomes approximately 0.7V).
Note down the break over voltage of SCR and the gate current required to turn on the SCR.

6. Switch OFF RPS-1 & RPS-2 (Don’t vary RPS-1 and bring RPS-2 to zero).

7. Increase the RPS-2 gradually until VAK jumps to 0.7, note down RPS-2 reading i.e., VBO
8. Now gradually vary the RPS-2 and note down the corresponding readings of VAK and IA.

9. Repeat the steps 6 and 7 for some other gate current value

10. Graph between VAK and IA is plotted.

Tabular Column:
Analog Electronics Circuits Lab 18ECL37

Sl. No VAK in Volts IA in mA

Expected Waveform:

Fig 4.2: Static Characteristics of SCR

Result:
The holding current IH = ________________ mA
The latching current IL = ________________ mA
At gate current IG = _________ mA, the break over voltage VBO = ________ V

Outcome:
Analog Electronics Circuits Lab 18ECL37

Understood the static characteristics of an SCR and Latching current and holding currents were
measured using the graph.

Viva Questions:

1. What is SCR?
2. What are various turn on method for thyristor?
3. What is fullform of SCR
4. How many terminals of SCR and their names
5. Why is it called Silicon controlled rectifier
6. What is rectification?
7. How can SCR control the rectification?
8. How to trigger SCR
9. What are operating modes or operating regions of SCR
10. What is forward blocking mode. Explain?
11. What is forward conduction mode. Explain?
12. What is reverse blocking mode. Explain?
13. How many junctions in SCR?
14. Explain holding current?
15. Explain latching current?
16. Difference between SCR and TRIAC