EECS 141 – S02

Lecture 7
Inverter Sizing

Digital Integrated Circuits Inverter © Prentice Hall 1999

Last Lecture
l The CMOS Inverter: Dynamic Behavior
» Capacitors in MOS transistors
l Summary:
» Gate Capacitances (Thin Oxide)
– Channel - voltage-dependent
– Overlap - constant
» Drain- and Source Junction (Depletion)
– Bottom - CJ, MJ
– Side-wall - CJSW, MJSW
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 Today

l Propagation Delay
l CMOS Inverter sizing for optimum delay

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Propagation Delay

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 CMOS Inverter Propagation Delay
Approach 1
VDD

tpHL = CL Vswing/2
Iav

Vout CL
~
Iav CL kn VDD

Vin = V DD

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CMOS Inverter Propagation Delay

Approach 2
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL

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 CMOS Inverters
VDD

PMOS

1.2µm
=2λλ
Out
In
Metal1

Polysilicon

NMOS
GND

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Transient Response
3

2.5
?
2

tp = 0.69 CL (Reqn+Reqp)/2
1.5
(V)

tpHL
out

tpLH
V

0.5

-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10

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 Design for Performance

l Keep capacitances small

l Increase transistor sizes
» watch out for self-loading!
l Increase VDD (????)

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Delay as a function of VDD

5.5

4.5

4
t (normalized)

3.5

3
p

2.5

1.5

1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
V (V)
DD

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 Device Sizing
-11
x 10
3.8

3.6 (for fixed load)

3.4

3.2

3
t (sec)
p

2.8
Self-loading effect:
2.6 Intrinsic capacitances
dominate
2.4

2.2

2
2 4 6 8 10 12 14
S
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NMOS/PMOS ratio
-11
x 10
5

tpLH tpHL
4.5

tp β = Wp/Wn
t (sec)

4
p

3.5

3
1 1.5 2 2.5 3 3.5 4 4.5 5
b

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 Impact of Rise Time on Delay
0.35

0.3
tpH L (nsec)

0.25

0.2

0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

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Inverter Sizing

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 Inverter Chain
In Out

CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

May need some additional constraints.

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Inverter Delay
• Minimum length devices, L=0.25µm
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
W
• Analyze as an RC network
−1 −1
 W   W 
RP = Runit  P  ≈ Runit  N  = RN = RW
 Wunit   Wunit 
Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL
W
Load for the next stage: C gin = 3 Cunit
Wunit
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 Inverter with Load
Delay

RW

CL
RW Load (CL)
tp = k RWCL

k is a constant, equal to 0.69

Assumptions: no load -> zero delay
Wunit = 1
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Inverter with Load

CP = 2Cunit Delay

2W

W
Cint CL

Load
CN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

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 Delay Formula

Delay ~ RW (C int + C L )

t p = kR W C int (1 + C L / C int ) = t p 0 (1 + f / γ )

Cint = γCgin with γ ≈ 1

f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit

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Apply to Inverter Chain

In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

 C 
t pj ~ Runit Cunit 1 + gin, j +1 
 γC gin, j 
 
N N  C 
t p = ∑ t p , j = t p 0 ∑ 1 + gin, j +1 , C gin, N +1 = C L
 γC
i =1 

j =1 gin , j 

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 Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

C gin, j = C gin , j −1C gin, j +1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay

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Optimum Delay and Number

of Stages
When each stage is sized by f and has same eff. fanout f:
f N
= F = C L / C gin ,1

Effective fanout of each stage:

f =NF
Minimum path delay

(
t p = Nt p 0 1 + N F / γ )
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 Example
In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f =38=2

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Optimum Number of Stages

For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
C L = F ⋅ Cin = f N Cin with N =
ln f
t p 0 ln F  f γ 
( )
t p = Nt p 0 F 1/ N / γ + 1 =
γ
 + 
 ln f ln f 
∂t p t p 0 ln F ln f − 1 − γ f
= ⋅ =0
∂f γ ln 2 f
For γ = 0, f = e, N = lnF f = exp(1 + γ f )
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 Optimum Effective Fanout f
Optimum f for given process defined by γ
f = exp(1 + γ f )
fopt = 3.6
for γ=1

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Impact of Self-Loading on tp

No Self-Loading, γ=0 With Self-Loading γ=1

60.0

40.0
u/ln(u)

x=10,000

x=1000

20.0 x=100

x=10

0.0
1.0 3.0 5.0 7.0
u

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 Normalized delay function of F

(
t p = Nt p 0 1 + N F / γ )

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Buffer Design
N f tp
1 64 1 64 65

1 8 64
2 8 18

1 4 16 64 3 4 15

1 64 4 2.8 15.3
2.8 8 22.6

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