Voltus-Fi Custom Power Integrity Solution: Electromigration and IR Drop at the Transistor Level

Power signoff isn't just about digital logic—analog and custom digital blocks in SoCs need power integrity analysis as well. That's why Cadence today (Aug. 4, 2014) is introducing the
Voltus-Fi Custom Power Integrity Solution, which provides transistor-level electromigration (EM) and voltage drop (IR drop) analysis with foundry-certified SPICE accuracy.

The Voltus-Fi solution complements the Cadence Voltus IC Power Integrity Solution, a full-chip, cell-level power signoff solution announced in November 2013. The Voltus-Fi solution
thus "completes the Voltus platform," said Jerry Zhao, director of product marketing at Cadence. Key Voltus-Fi features include full integration into the Cadence Virtuoso analog design
flow, visualization and analysis with real physical layouts, and SPICE level accuracy. The Voltus-Fi solution runs with the Cadence Spectre APS (Accelerated Parallel Simulator), which now
offers a patented voltage-based iteration method for solving the power network.

EM and IR drop are becoming more serious problems at advanced process nodes, and foundry rules are extremely complex at 28nm and below. EM is the unwanted transport of material
due to movement of ions in a conductor, caused by a transfer of momentum from electrons to these ions. One result is that high-density current in a narrow metal wire may destroy the
wire. EM is thus a reliability problem that could occur after years of deployment in the field. An EM analysis solution calculates the current on each wire and compares it to foundry EM
rules. The Voltus-Fi solution analyzes EM on both signal and power nets.

IR drop is an unwanted drop in voltage caused by current through a metal wire. It is so named because voltage (V) = current (I) * resistance (R). An unexpected voltage drop on an
instance or a device can cause a functional failure because the lowered voltage supply may not be strong enough to switch the instance, or may switch it too slowly. An IR analysis
solution calculates the IR drop and shows real voltage values on devices. While most other solutions consider power nets only, the Voltus-Fi solution analyzes IR drop on both signal and
power nets.

A Broader Solution

Voltus-Fi is not an isolated point tool—it is part of a much broader power integrity signoff solution. From a transistor-level point of view, that solution includes:

Layout (Virtuoso flow) and RC parasitic extraction (Quantus QRC Extraction Solution): The Quantus QRC solution performs an "EM aware" extraction. It understands EM rules
that foundries dictate on various layout patterns. Its use is strongly recommended for the Voltus-Fi solution.
Transistor-level EM and IR simulation: The Voltus-Fi solution runs with the Spectre APS to accomplish this task. The Spectre APS solves the matrix for the RC power network, and
the Voltus-Fi solution then runs EM and IR drop simulations based on foundry rules.
EM and IR drop visualization, analysis, debug, and fixing: This takes place in the Virtuoso flow, where layout designers can re-examine and repair problematic layout structures.
The Spectre APS provides a signoff-quality, foundry-certified matrix solver, Zhao noted. It can do some EM and IR drop analysis on its own, but without the Voltus-Fi solution, designers will
not be able to look at layouts and back-annotate to the Virtuoso flow for analysis and fixing. The Spectre APS solves the currents, Zhao said, and then the Voltus-Fi solution takes that
current information and uses its knowledge of the layout to evaluate compliance with EM and IR drop rules.

As shown below, the Voltus-Fi solution generates a "power grid view" (PGV) after the EM and IR drop checks are completed. This model includes physical layout information and also
captures electrical information. It can be passed to the full-chip Voltus power analysis tool for use in an SoC signoff power analysis. Further, the voltage drop results from Voltus power
analysis can be used by the Cadence Tempus Timing Signoff Solution for timing analysis.

As Zhao noted, the Tempus and Voltus solutions are actually provided in a single installation and they share an executable for some cross-functions. For example, the Voltus solution can
call the Tempus engine for TWF (Timing-Window-File) generation, while the Tempus engine can report leakage power numbers calculated by the Voltus engine.

The previous Cadence transistor-level EM and IR drop solution was the Virtuoso Power System, which the Voltus-Fi solution will replace, Zhao said. He noted that the Voltus-Fi solution has
increased accuracy, better integration with the Virtuoso flow (including the front-end Analog Design Environment (ADE)) and new analysis features.

Solving the Power Network

For signoff level accuracy, the Voltus-Fi solution is run when the layout is completed. Inputs include the extraction netlist, DSPF (Detailed Standard Parasitic Format) file, and layout
database. Since the Voltus-Fi solution runs dynamic verification in most cases, test vectors are required. Finally, the Voltus-Fi solution needs the technology files that define foundry rules for
EM and IR drop.

So why run IR drop analysis on the signal nets? "People usually don't care about IR drop in signal nets," Zhao said. "But in analog design, sometimes there are very long wires, or you
have strong current flowing along a wire. If you have an IR drop issue, the effect on signal current can be significant."

The Voltus-Fi solution has been used to solve embedded memories with millions of transistors. One reason it can handle relatively big circuits is an innovative matrix solution provided by
the Spectre APS.
 There are two methods for solving a large RC matrix: direct and iterated. The direct approach solves the RC network and the circuit devices all at once. This approach is very accurate, but
poses performance and capacity limitations. The iterated approach, in contrast, uses a two-staged methodology. First, it runs an RC-reduced simulation to collect voltage or current profiles
at tap device points. Secondly, it applies the collected profiles to the entire RC network, runs simulation, and generates EM and IR drop reports.

Cadence is not the only provider of an iterated approach. However, other providers use a current-based iterated method, in which current is probed in the first stage and is decoupled from
the RC nets. The new Spectre APS methodology, however, uses a voltage-based iterated method. Here, voltage (not current) is profiled in the first stage. This approach, Zhao said, can
handle much larger circuits than the current-based method. It also promises better accuracy and performance, with no need to save an intermediate current waveform file in the first stage.

For results analysis, users can launch the Voltus-Fi solution from the Virtuoso Layout view. A Violations Browser can display EM and IR drop violations. Users can cross-prove between a
graphical display and a simulation text report. The bottom line? "It's all about ease of use and productivity if the EM and IR drop engine is accurate," Zhao said.

Further information is available at this landing page.

Richard Goering

Related Blog Posts

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