Analog & Digital VLSI

Design
EEE/ INSTR F313
BITS Pilani ANU GUPTA
EEE
Pilani Campus
 BITS Pilani
Pilani Campus

Digital design
Concepts

• Boolean Algebra, and minimization

• Gates, Combinational networks
• Logic design with PLD
• FLIP FLOPS, counters
• Synchronous sequential networks-mealy , moore
machine, state table and its reduction
• ASM- design using ASM chart, state assignment, ASM
tables, ASM realizations
• Asynchronous sequential network-analysis, primitive flow
table and its reduction, races, hazards

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Digital VLSI Design

• Digital VLSI Design

Full Automation
Maximum benefit of scaling
High speed
low power
Robustness

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Design metrics
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Pilani Campus

Design of CMOS inverter

for long channel MOSFET s
 INVERTER

STATIC CHARACTERISTICS
 VTC DESIGN ISSUES
• STATIC POWER CONSUMPTION
• FULL LOGIC LEVELS
• SHARP TRANSITION
• SWITCHING THRESHOLD→ NOISE
MARGINS
PRACTICAL VTC
FIVE CRITICAL VOLTAGES

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 SWITCHING THRESHOLD
• Vth
• Output changes its state
Noise Margins
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Possible Noise immunity/
noise margin
Binary signaling----

Required swing

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Noise immunity - Signal
magnitude/ swing with noise
Binary signaling----

Required swing

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Noise components-example

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Implementation
Resistive load
Design for Vol
VIH
SAT. ENHANCEMENT LOAD INV.
LIN. ENHANCEMENT LOAD INV.
Static characteristics
Operating regions
VOH
VOL
VIL
VIH
V inv=V th -switching threshold
Long channel MOSFET-- VM
Long channel VM
Symmetric CMOS inverter
 Critical voltage
• Nothing
• We can design for wide noise margins
• Set Vth= ½Vdd
Why design for Vth≠ ½Vdd?
Choose appropriate VM
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Design of CMOS inverter in sub-

threshold region
Subthreshold region operated
MOS

Io represents the drain current when Vgs = Vt,

Sub-threshold current
 Subthreshold region threshold voltage
Vtsub

• Sub threshold region threshold voltage Vtsub

can be defined as the voltage Vgs at which the
drain current is equal to 0.01Io,

• n= η= subthreshold slope factor

• parameter n is process dependent. typical range

of values for n is 1 to 1.5.
characteristics
Subthreshold region VM
Noise margins
Gain of CMOS inverter
saturation region operation

ΦT
 Subthreshold swing S
The transition from the ON state to the OFF state is gradual. This is more clearly
when ID is plotted on a logarithmic scale

log
scale
 Sub-threshold swing S

Required----

A device characterized by steep subthreshold slope (1/S) exhibits a faster

transition between off (low current) and on (high current) states.
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Design of CMOS inverter

for short channel MOSFET s
THE SHORT CHANNEL
MOSFET

L> xd1+xd2

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Short channel MOSFET- DIBL

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 Punch through
• This continue until the VDS reaches value that deplete the
whole remaining neutral substrate region where the two space
charge region almost touch each other.
• As the voltage is increased further the drain space charge
region expands while the space charge region of the source
junction contracts
• This means that its internal electric field decreases which
means that the source junction becomes appreciable forward
biased
• So, the net barrier height at the source is appreciably
decrease which enables electrons to flow with large number
from source to drain.
• This is the punch through current signifying the onset of punch
through breakdown.
• Long-channel MOSFET is defined as devices with width and
length long enough so that edge effects from the four sides
can be neglected
• Short channel MOSFET is defined as devices with width and
length short enough such that the edge effects can not be
neglected.
• Channel length L is comparable to the depletion widths
associated with the drain and source, or , channel depletion
width in channel region before inversion layer appears..
• Channel length L must be much greater than the sum of the
drain and source depletion widths

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Velocity saturated device
 Short channel MOS

CONSTANT 105 m/s for silicon

Short channel MOS current
equation

This model is first order and empirical

Long Channel Vs. Short Channel
SAME
Long Channel Vs. Short Channel
Id vs Vgs
 Switching threshold—short channel CMOS Inv.

  pVDS ATp 
 p co x 
w
  VDS ATp W p ox 
c  

 l p  l p W p co xvS AT
r   
 V
 n co x 
w  Wn co xvS AT
  VDS ATn Wn co x  n DS ATn 
 l n  l n
 NMOS

PMOS

vsat= 105 m/sec, VDSATn= 0.63V, VDSATp= -1 V

VM--For velocity saturated device-
inverter
Long channel VM
Finding VIL, VIH
Using Piece wise linear approx.
Gain of CMOS inverter
Inverter gain
 Gain of CMOS inverter
Alternative way

Drift velocity, Vde= µVdsat/ L = 105 m/sec

gds (in saturation) is dominated by channel length

modulation. Va is early voltage

1 I D sat
 g ds  Early Voltage, Va = 7 V / um
ro LVa
Noise margins
Short channel MOSFET--Estimation of NM
USING Piecewise lin. approx.
Determine g at Vin~Vm
Variation in VM by (w/L)
Impact Of Device Variations on Vm
Effect on kR= unCox[W/L]n / upCox[W/L]p
 Critical voltage
• Nothing
• We can design for wide noise margins
• Set Vth= ½Vdd
Why design for Vth≠ ½Vdd?
Choose appropriate VM
Effect on kR
Reducing supply voltage
 Hysteresis behavior
• If the power supply voltage is reduced below the
sum of the two threshold –

• The VTC will contain a region in which none of

the transistors is conducting

• The output voltage level is determine by

previous state of the output

• The VTC exhibits a hysteresis behavior

Hysteresis behavior
Use of hysteresis VTC
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End