Vidyalankar

S.E. Sem. III [BIOM]

Electronic Circuits and Design- I
Prelim Question Paper Solution

1. (a) Comparision between D-MOSFET and E-MOSFET

D-MOSFET E-MOSFET
i) A depletion mode mosfet normally An enhancement mode mosfet is
conducts but becomes more and normally non-conducting but

r
more non-conducting as carriers are conducts when the channel is
depleted or pulled out of the channel
enhanced by applying a voltage to

ka
by applying a voltage. the gate and pulling carriers into the
channel.
ii) D-MOSFET has a conducting E-MOSFET has no conducting
channel between the source terminal channel between two terminal source
and gate terminal. terminal and gate terminal.
iii) D-MOSFET can be worked in both E-MOSFET can work only in

depletion mode
iv) Symbol
D
an
enhancement mode as well as

D
enhancement mode

Symbol
D D

G G G G
Substrate Substrate
al
S S S S

v) Transfer characteristics Transfer characteristics

ID ID
dy

(mA) (mA) VDS = 10V

constant
Depletion 6 Enhancement
mode 5 mode
4
3
IDSS
2 IDS
1
Vi

VG 2 1 1 VT 2 3 4 VDS (V)
VGS -4 -3 -2 -1 0 1 2 3 4 5 6
off Transfer characteristic Transfer characteristics

1. (b) Darlington pair

If we cascade two CC  CC stages then configuration known as Darlington pair.

This configuration has high current gain, large bandwidth, unit voltage gain and it
is used as a buffer stage or impedance matching.

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Vidyalankar : S.E. – ECD
C
Darlington pair is also
reffered to as super 
transistor if 1 is a current
gain of transistor T1 and 2 C
is a current gain of T1, 1 T2, 2
transistor T2. When we B
connected T1 and T2 to form E E

Darlington pair current gain of Darlington pair is given as;

 T = 1   2

r
If T1 and T2 are identical then;
T = (1)2 or (2)2

ka
Baising of Darlington Pair :
VCC

RB
IB an T1
Vi +
Cin VBE1

T2
+
VBE2 IE
 Vo
Applying KVL to Base loop; Co
al
VCC  IBRB  VBE1 VBE2 IERE = 0 RE
 IE = (1 + T) IB

Where T = 1.2
dy

 VCC  IBRB  VBE1  VBE2  (1 + T) IB RE = 0

 VCC  VBE1  VBE2 = IBRB (1 T )I BRE
= IB RB 1T  RE 
Vi

VCC  VBE1  VBE2

 IB =
RB 1  T  RE

Apply KVL to collector loop;

VCC  VCE  IERE = 0
VCE = V CC IERE .

For ac equivalent circuit darlington pair can be replaced by single transistor

having T = 12 & VBE = VBE1 VBE2 .

2 1113/Engg/SE/Pre Pap/2013/BIOM/ECD_Soln
 Prelim Question Paper Solution
VCC

RB

Vi T
+
Cin
VBE
 Vo
RE Co

r
Darlington pair as CC

ka
amplifier.
1. (c) Clamping Circuit
A clamping circuit works based on nonlinear property of a diode (unidirectional). It is
used to introduce a dc level to an input signal. If the dc introduced equals dc lost by
the signal during processing, then clamping circuit is called "dc restorer". If the dc
inserted is of any other value, then clamping circuit is called as "dc inserter".
an
Basic Clamping circuit
It mainly consist of a capacitor and diode as shown :

C
al
Vi D V0
i
dy

When an ac sinusoidal waveform is impressed on the diode circuit, during the 1st
quarter half of the cycle, input voltage rises from V to Vm. Assuming the diode as
an ideal device, D is forward biased, hence V0 = 0. Therefore the total resistance
associated with capacitor charging is zero, the capacitor voltage follows input
voltage i.e. V0 = Vi.
Vi

At the end of the first quarter cycle, vc = Vm with polarity as shown. After the first
quarter cycle, input voltage starts decrease from Vm. The capacitor is unable to
discharge, since the diode is reverse biased. Assuming the capacitor as an ideal
element, vc remains equal to Vm.

Therefore v0 = vi  vC i.e. v0 = vi  Vm.

When vi = Vm, v0 = 0
vi = 0, v0 = Vm
vi = Vm, v0 = 2Vm

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Vidyalankar : S.E. – ECD

The output waveform is as shown :

Vi
Vm

r
Vm

ka
t

Vm
an
2Vm
al
From the output waveform, it is seen that the positive peak of input waveform
gets clamped to zero level, hence the name "negative clamper". It introduces
average value to input waveform (Vm).
dy

1. (d) BJT has a positive temperature coefficient i.e., with the increase in temperature,
value of IC increases and hence power dissipation PD increase and the
temperature increases. Thus due to thermal regeneration IC increases to a very
high value causing damage to transistor. This is thermal runaway.

FET on the other hand have negative temperature coefficient since the mobility
Vi

decreases with increasing temperature. Since majority carrier current decreases

with temperature, thermal runaway is not encountered in FET.

2. (a) hfe = 300; hie = 2.2 k;

|Av|  200 ; SICO  10; V0  5 Vrms ; Vcc  20V; fL  30Hz

Step 1 : Selection of transistor

Select transistor BC147A.

Step 2 : Selection of biasing network

Select voltage divider bias network for better stability.

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 Prelim Question Paper Solution

Step 3 : Selection of Rc
h .R
|Av| = fe L
hie VCC
Let Av = 225 where RL = Rc
300
 225 = .Rc R1
2.2k Rc CC 2
 Rc = 1650  Vo
CC1
select Rc = 1800
Vi
Step 4 : Selection of ICQ

r
V peak
I0 peak = 0 R2
Rc CE
RE

ka
5
= = 2.78 mA
1800
1
Let ICQ = I0 peak
2
Ic = 1.39 mA
Step 5 :
VCEQ

VCEQ
an
Selection of VCEQ
= 1.5(VCE sat  V0 peak )
= 1.5 (0.25 + 5)
= 7.875 V
Step 6 : Selection of RE
VRE = VCC  VCEQ  ICQ (RC  RE )
al
= 20  7.875  1.39 (1800 + RE)
VRE = 9.623  1.39 RE
9.623  1.39RE
RE =
1.39
dy

 2  1.39 RE = 9.623
 RE = 3.46 k
Select RE = 3300 
Step 7 : Selection of R1 and R2
1  hfe
S1 =
 RE 
Vi

1  hfe  
 RB  RE 
Let S1 = 8; hfe = 300
1  300
8 =
3300
1  300 .
(3300  RB )
300  3300
1 = 37.625
(3300  RB )
RB + 3300 = 27030 
RB = 23730 

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Vidyalankar : S.E. – ECD

ICQ 1.39m
Now IBQ = = = 4.63A
hfe 300
IBQ = 4.63 A
VB = IBQRB  VBE  (IBQ  ICQ )RE
= 5.31
V R 20  R2
VB = CC 2 =
(R1  R2 ) (R1  R2 )
20R2 R2
 = 5.31  = 0.2655
(R1  R2 ) (R1  R2 )

r
R1R2

ka
Now RB = = 23730 
R1  R2
R1(0.2655) = 23730 
R1 = 89.378 k
Select R1 = 91 k
 R2 = 0.2655R2 + 0.2655 R1


Select
anR2

R2
= 0.3614R1
= 32893
= 33k

Step 9 : Selection of CC1 , CC2 , CE

(a) To find CC1
al
fL 30
Let fLCC = = =3
1 10 10
Ri = RB = R1 || R2 = 24.02 k
1
dy

fLCC =
1 2RiCC1
 CC1 = 2.20 F
Select CC1 = 2.2 F

(b) To find CE
Vi

fLCE = fL = 30 Hz
1 hfe
R = || RE gm =
gm hie
= 7.33 || 3300
1
 fLCE =
2RCE
R = 7.31
 CE = 725F
Select CE = 1000 F

6 1113/Engg/SE/Pre Pap/2013/BIOM/ECD_Soln
 Prelim Question Paper Solution

fL
(a) Let fL CC2 = =3
10
R = RC + R L = R C = 1800
1
 fLCC2 =
2RCCC2
 CCC2 = 29.47F
Select CCC2 = 33F

The final circuit is as shown :

r
VCC = 20V

ka
R1 = 91k Rc = 1.8k CC2  33F
V0
CC1  2.2F
BC147A
Vi an
R2 = 33k
RE = 3.3k

CE  1000F
al
2. (b) Comparision between Series and Shunt Clippers
Series Clippers Shunt Clippers
i) When a series diode conducts, series When a shunt diode conducts shunt
dy

branch resistance decreases, slope branch resistance decreases, slope

of transfer characteristics increases
i.e. output voltage increases.
ii) With diode as series element
reference voltage source VR can
have any value of RS because it is in
series with high value of R.
Vi
of the transfer characteristics
decreases output voltage decreases.
With diode is shunt element,
reference VR should have low value
of RS because it is in series with
diode.

iii) Whenever it is intended that there is It is intended that there is transmission,

no transmission, a fast changing
signal at input side gets transmitted to
output due to internal capacitance of
diode
whenever a fast changing signal comes
at input, the change is not transmitted
to output due to finite rise time
associated with charging of total
shunting capacitance at output (output
gets rounded off at the edges).

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Vidyalankar : S.E. – ECD

iv) Series Positive Clipper Shunt Positive Clipper

R
D
D
R V0
Vi V0

VR VR

3. (a)

r
D1 2V
+ 

ka
D2 2.5V
18V  +
V0
2.5V 2k
18V
an
The given circuit is of twoway series clipper. Assuming the diodes to be ideal.
During positive half cycle of the input, we observe that D1 gets forward biased
and D2 gets reverse biased.

 D1 acts as a short circuit where as D2 act as a open circuit. The equivalent

circuit is as shown.
al
2V
+ 

+
dy

 +
Vi 2k

As out can be observed from the above figure the output voltage = 0V as long as
Vi  2V;
Vi

 it reverse biases the diode more than the input voltage.

 When Vi > 2V the output becomes a function of i/p voltage.
 18  2  2kI = 0
 ID = 8 mA
 V0 = ID  2k = 16 V
 V0 = 16 V

8 1113/Engg/SE/Pre Pap/2013/BIOM/ECD_Soln
 Prelim Question Paper Solution

 The output voltage can be drawn as shown.

Vi
18V

2V

16V

r
ka
Similarly, during ve half cycle of
input, D2 gets forward biased and D1
gets reverse biased. The circuit Vi 
diagram is as shown. 2.5 2k

Hence V0 = 0V.
an
However, the 2.5 V bias keep the diode reverse biased unless | Vi |  2.5 V.

When Vi < 2.5 V, the output voltage V0 voltage V0 becomes a function of input
voltage Vi.
 Maximum output voltage = 18 + 2.5 = 15.5 V
al
The waveform can be drawn as shown
Vi

18V
dy

2V
t
2.5V

18V
Vi

V0 D1 ON
D2 OFF
16V

D1 off
D2 off t

D1D2 off

15.5V
D1 OFF
D2 ON
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Vidyalankar : S.E. – ECD

The transfer characteristics +Vm = 16 V

are as shown.
DIODE ON
(D1)
18V 2.5V 2
Vi
DIODE OFF
DIODE ON D 1 & D2
(D2)

Vm = 15.5 V

r
3. (b) Here RE is split into RE1 and RE2, RE2 is bypassed by a large value CE

ka
i) Circuit diagram +VCC

RC
RB
an V0

Vi Q

RE1
ii) ac Equivalent circuit
Short VCC and short all the capacitors
al
RE2
CE

Q
V0
RC
dy

Vi RB RE1

iii) Replace transistor by its h parameter model

Vi

Ii Ib I0
hie hfe Ib

Vi RB RC V0
(1 + hfe )Ib
RE1

Ri Vi Ib .hie + (1+ hfe )IbRE1 R0

=
Ib Ib
=hie + (1+ hfe )RE1
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 Prelim Question Paper Solution

iv) To find input resistance Ri = Vi/Ii

V V I I .h  (1  hfe )IbRE1 RB
Ri = i  i . b  b ie .
Ii Ib Ii Ib RB  hie  (1  hfe )RE1

=
hie  (1 hfe )RE1.RB = RB || hie  (1 hfe )RE1
RB  hie  (1  hfe )RE1

v) To find output resistance R0

R0 = R C

vi) To find voltage gain Av = V0 / Vi

r
Output Voltage (V0 ) I0 .RC
Av = =
Input Voltage (Vi ) Ib .hie  (1  hfe )RE1

ka
hfe Ib RC hfe RC
=  = 
Ib hie  (1  hfe )RE  hie  (1  hfe )RE1

The ve sign indicates that input and output voltages are 180 out of phase.

Ai =
output current
input current
hfe Ib
an
vii) To find current gain AI = I0 / Ii

RB
I
= 0
Ii
=
I0 Ib
.
Ib Ii

=  .
Ib RB  hie  (1  hfe )RE1
hfe .RB
al
= 
RB  hie  (1  hfe )RE1

viii) Results
dy

Without RL With RL
1) hfe RC hfe RC RL
AV = AV = .
hie  (1  hfe )RE hie  (1  hfe )RE RC  RL
2) RB RB
AI =  hfe . AI =  hfe . .
RB  hie  (1  hfe )RE RB  hie  (1  hfe )RE
Vi

RC
RC  RL
3) Ri = RB || [ hie + (1  hfe )RE ] Ri = RB || [ hie + (1  hfe )RE ]
4) R o = RC R o = RC
Ro ’ = RC || RL

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Vidyalankar : S.E. – ECD

4. (a) VCC = 20V

2.2 K

dc = 75
470 K
1.1 K RC = 2.2 K
RE = 1.1 K
RB = 470 K

r
(a) Base Current (IB)
VCC  VBE
IB =

ka
RB + 1    RC  RE 
20  0.6
=
 470 ´10   1 75   2.2  1.1 ´103
3

= 0.0269 mA

(b) Collector Current an

IC =  I = 75 (0.0269 × 103)
= 0.002018 A
= 2.018 mA

(c) Collector Emitter Voltage

VCE = VCC  (IB + IC) (RC + RE)
al
= VCC  (IB +  IB) (RC + RE)
= VCC  I (1 + ) (RC + RE)
= 20  (0.0269 × 103) (76) (2.2 + 1.1) × 103
= 13.25 V
dy

(d) BJT power consumption

P = VCE IC = (13.25) (2.018 × 103)
= 26.7385 mW

20V
R1 = 8.2 K
R2 = 2.2 K
Vi

RC = 2.7 K
2.7 K RE = 1.8 K
8.2 K

dc = 120

2.2 K
1.8 K

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 Prelim Question Paper Solution

20 ´ 2.2
VB = VCC  R1 R2  =
 R  R   8.2  2.2 
 1 2
= 4.2307 V
R1 R2
RB = R1 || R2 =
R1  R2
= 1.7346 K

(a) Base Current

VB  VBE 4.2307  0.6
IB = =
RB  1    RE 103 ´1.7346   121 1.8 ´103 

r
= 0.01653 mA

ka
(b) Collector Current
IC independent of 
V
IC = B = 0.0023503 A = 2.3503 mA
RE
an
(c) Collector Emitter Voltage
VCC = IC RC + (IC + IB) RE + VCE
VCE = VCC  ICRC + (IC + IB) RE
= 20  (2.3503) (2.7) + (2.3503 + 0.01653) (1.8)
= 17.9144 V

(d) BJT Power Consumption

al
P≈VCE IC
= (17.914) (2.3503) = 42.1032 mW

4. (b) (i) Comparison between CE, CB, CC amplifiers

dy

Parameter CE amplifier CB amplifier CC amplifier

i) Voltage gain high high low ( 1)
ii) Current gain high low ( 1) high
iii) Power gain high low low
Vi

iv) Input resistance medium low high

Output
v) high high low
resistance
vi) Q point stability good good poor
output is out of output is in output is in
vii) Phase shift
phase with input phase with input phase with input
Low frequency
High frequency
amp. Buffer
viii) Applications amp.
Current source Isolator
Current source
Switch

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Vidyalankar : S.E. – ECD

(ii) Transfer characteristics of JFET ID (mA)

A graph drawn with ID VS VGS for a
constant value of VDS is as shown. IDSS
The graph is parabolic in nature.

The graph can be represented

mathematically by the equation
2
 V 
ID = IDS  1  GS  VGS (V) VGS OFF (Vp) 0
 Vp 


r
The above equation shows that JFET is a square law device.

ka
JFET Parameters
1. IDSS : Drain source saturation current : IDSS is defined as the
maximum value of drain current when VGS = 0V. It is a constant for a
JFET. For JFET BFW  11, IDSS typical = 7 mA.

2.
an
VGSOFF : Pinch off voltage : It is defined as the maximum value of VGS
at which the drain current becomes zero. It is also called as pinch off
voltage. For a JFET, VGSOFF is a constant. For JFET BFW11, VGSOFF
typical = 2.5 V.

3. rd : drain resistance : It is defined as the ratio of the change in drain

al
source voltage to the change in the drain current for a constant value of
VGS .
VDS ID (mA)
rd = VGS constant
ID VGS constant
dy

= 1/slope of output  ID
 VDS
characteristics in
pinch off region VDS (V)
For FET BFW  11, rd = 50 k.
Vi

4. gm : Transconductance : It is defined as the ratio of the change in

drain current to the change in the gate source voltage for a constant
value of VDS .
ID
gm = V constant
VGS DS
= slope of transfer characteristics

14 1113/Engg/SE/Pre Pap/2013/BIOM/ECD_Soln
 Prelim Question Paper Solution

5. (a) The DC equivalent circuit is as shown

1M  24M VDD = 24V
Here VG = = 3V
[1M  7M]
RG = (7MM || 1M) = 875 k

Now VGS = VG  IsRs 7M RD = 4.7k

VGS = 3  2.5 Is (Is in mA)
2
 V  VG
Now ID = IDSS  1  GS 
 VP 
2 1M
 3  2.5Is  RS = 2.5k

r
= 8  1 
 4 

ka
8
= (7  2.5ID )2  Is = ID
16
2 ID = 49  35ID  6.25ID2
6.25ID2  37ID  49 = 0
ID2  5.92ID  7.84 = 0

ID

=
=
an
5.92  3.6864
2
5.92  1.92
2
= 3.92 mA or 2 mA
 ID = 2 mA or 3.92 mA
al
For ID = 3.92 mA For ID = 2 mA
VGS = 6.8 V VGS = 2V
But VP = 4V  VGS  6.8 V
 VGS = 2V  ID = 2mA
dy

2IDSS 2  8mA
Now gmo = = = 4 mS
| VP | | 4 |
 V 
gm = gmo  1 GS 
 VP 
 2
= 4mS  1   = 2 mS
Vi

 4
gm = 2mS

Now neglecting the value of rd

Av = gm RD
= 2  4.7
Av = 9.4  Av = 9.4
Ri = RG = 875 k Ri = 875 k
R0 = RD = 4.7k R0 = 4.7 k

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Vidyalankar : S.E. – ECD

5. (b) DC analysis :

VB1 =
RB2  RB3  Vcc =9
RB1  RB2  RB3
RB3 VCC
VB2 = = 3.
RB1 RB2 RB3

KVL to loop :
VB VBE
IE2 = 2 = 2.3 m Amp
RE

r
26mV
re1 = re2 = = 11.30
IE2

ka
VC1 = VCC  IC1 RC1 = 12.94

For transistor Q1;

VCB1 = VC1 VB1 = 12.94  9 = 3.94 V
 Qpoint of Q1 = (3.94, 2.3 mA)
an
For transistor Q2;
VCE2 = VC2 VE2
VC2 = VE1

To find VE1 ,
al
VBE1 = VB1 VE1
0.7 = 9  VE1
VE1 = 8.3 V
dy

 VE1 = VC2 = 8.3 V

VCE2 = VC2 VE2
VCE2 = 8.3  IE2 RE 
VCE = 6V
 QPoint of Q2 (6, 2.3 mA)
Vi

AC analysis :
c Vo
Vi b c e

RB3 2re2 re1 

RB2  Vo Ie1
2 IB RC1
2 b
e

16 1113/Engg/SE/Pre Pap/2013/BIOM/ECD_Soln
 Prelim Question Paper Solution

Vo = Ie1re1 = 0.025

Vin = Ib2 2 Ve2 = 3.1188
r
Av1 = e1 = 1
re2
RC
Av2 =
re
26mV
re =
ICQ
2.2K
Av2 =

r
11.30
Av2 = 194.69

ka
20 = RC1 = 2.2 K
 B2 ||2 re2
2in = RB3 ||R = 1.12 K
zi
Ai = A V  = 99.114
z0
an
6. (a) Depletion  MOSFET : (N channel)

Source (S) Gate (G) Drain (D)

Metal (Al) VGS VDS

SiO2 S G D
n + n n +
+++++++
al
n+ + + + + + n+
diffused channel
Depletion
p  type substrate region
ptype substrate
dy

nchannel D  E MOSFET
Fig. 1(a) Fig. 1(b)

Figure 1(a) shows the construction features of depletion enhancement MOSFET.

The construction is the same as that for the enhancement mode MOSFET,
except that a lightly doped nchannel has been introduced between the two
heavily doped source and drain blocks.
Vi

Starting with a high resistive ptype substrate, two blocks of heavily doped
ntype material are diffused into the substrate, and then the surface is coated
with a layer of silicon dioxide. Holes are cut through the SiO2 to make contact
with the ntype blocks. Metal is deposited through the holes to form drain and
source, a metal plate is deposited which functions as a gate. The metal area of
the gate, in conjunction with the insulating dielectric oxide layer and the
semiconductor channel, forms a parallel plate capacitor.
The insulating layer of SiO2 is the reason why this device is called the insulating
gate FET. This layer results in an extremely high input resistance 1010 to 1015 
for the MOSFET.

1113/Engg/SE/Pre Pap/2013/BIOM/ECD_Soln 17
Vidyalankar : S.E. – ECD

Characteristics of D-MOSFET
When the drain is made positive with respect to the source, appreciable drain
current IDSS flows, even with zero gate to source voltage (VGS = 0), because
electrons can flow from source to drain through ntype channel existing between
them. If the gate is made negative with respect to the source, some of the
negative charge carriers are repelled from the gate and driven out of the ntype
channel, and cause the channel resistance to increase. Drain current drops as
VGS is made more negative. This effect is similar to that in the nchannel JFET.
Since the action of negative voltage on gate is to deplete the channel of free
ntype charge carriers (which are majority charge carriers), the device operating
with negative VGS is referred to as depletion mode MOSFET, note [fig.(b)],

r
because of the voltage drop due to the drain current, the channel region nearest
the drain is more depleted than is the region near the source. This phenomenon

ka
is similar to that of Pinchoff occurring in a JFET at the drain end of the channel,
drain characteristic of depletion mode MOSFET and the JFET are quite similar.

ID
(mA) +2 V

6 VGS = +1V Enhancement

5
4
3
an VGS = 0V

1 V
mode

Depletion
mode
2
2 V
1
al
1 2 3 4 5 6 VDS (V)
Drain characteristic
dy

ID
(mA)

6
Depletion mode Enhancement mode
5
Vi

4
3
2 IDSS
1

-4 -3 -2 -1 0 1 2 3 4 5 6 VGS
VGS off
Transfer characteristic

18 1113/Engg/SE/Pre Pap/2013/BIOM/ECD_Soln
 Prelim Question Paper Solution

6. (b) Comparison between BJT and JFET

BJT JFET
i) BJT is a bipolar device, both majority JFET is an unipolar device, electron
and minority carriers take place in current in Nchannel and hole
electrical conduction. current in Pchannel.
ii) BJT is current operated device, it is JFET is voltage operated device, it is
a current controlled current source. a voltage controlled current source.
iii) BJT has high gm and hence JFET has low gm and hence
provides large gain provides low gain.
iv) BJT has low input resistance (  k) JFET has high input resistance (M)

r
 input junction is forward biased.  input junction is reverse biased.
v) Thermal runaway is possible in BJT. Thermal runaway is not possible in

ka
 IC increases when temperature JFET.
increases.  ID decreases when temperature
increases.
vi) BJT can be operated with low values JFET requires large supply voltage
of supply voltage (3  10) V (> 10) V
vii) BJT is noisy in operation.
an JFET is less noisy in operation.
viii) Requires large area while fabrication Requires less area while fabrication
of IC's. of IC's.
ix) Less susceptible to damage while More susceptible to damage while
handling. handling.
x) Very complex biasing circuits Biasing circuits are less complex
required to provide stability. when compared to that of BJT.
xi) Cannot be used as a voltage It can be used as a voltage variable
al
variable resistance resistance


dy
Vi

1113/Engg/SE/Pre Pap/2013/BIOM/ECD_Soln 19