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• Flip-Flops (edge-triggered)
– edge sensitive circuits that sample the inputs on a clock
transition
• Positive edge-triggered: 0 1
• Negative edge-triggered: 1 0
– Built using latches (e.g., master-slave flip-flops)
Synopsys University Courseware
Copyright © 2012 Synopsys, Inc. All rights reserved.
Sequential Elements
Developed By: Jorge Ramirez
Latches and Flip-flops
Output exposed
tDQ=tDC+tCQ
Minimum tDQ
tsetup tCQ
tpcq
tccq
tDC
Synopsys University Courseware
Copyright © 2012 Synopsys, Inc. All rights reserved.
Sequential Elements
Developed By: Jorge Ramirez
Characterizing sequential element
Hold time
Hold time: Minimum delay from clock
to D changing such that
tCQ ≤tpcq
Delay
tDQ
Minimum tDQ
Slope = -1
tpcq
tCQ tCQ
thold tsetup
tpcq
tCD tDC
Synopsys University Courseware
Copyright © 2012 Synopsys, Inc. All rights reserved.
Sequential Elements
Developed By: Jorge Ramirez
tCQ vs tDC
• Longer tsetup and shorter
propagation delay for
low input than high
• The quoted delay for flip-
flop timing parameters,
it is customarily the
worst go the 0 and 1
delay
• Aperture width
tar = tsetup1 + thold0
taf = tsetup0 + thold1
Synopsys University Courseware
Copyright © 2012 Synopsys, Inc. All rights reserved.
Sequential Elements
Developed By: Jorge Ramirez
tCQ vs tDC
Aperture width
tar = tsetup1 + thold0 The quoted delay for flip-
taf = tsetup0 + thold1 flop timing parameters, it
is customarily the worst
(bigger) value
in out
CL CL CL
Sn Sn+1
Clock
DCQ DCQ
U U
Y= Sn-1 Sn Sn+1
Synopsys University Courseware
Copyright © 2012 Synopsys, Inc. All rights reserved.Time
Sequential Elements
Developed By: Jorge Ramirez
Sequencing Static Circuits
tskew tskew
– Characteristic of clock distribution t jit
system t jit
Received Clock
Note: T