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Sequential Circuit Design

Jorge Ramírez Bravo


Corp Application Engineer

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Sequential Elements
Developed By: Jorge Ramirez
Agenda
• Circuit design of latches and flip-flops
• Sequential element characterization
• Sequencing Static Circuits

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Sequential Elements
Developed By: Jorge Ramirez
CIRCUIT DESIGN OF LATCHES AND
FLIP-FLOPS
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Sequential Elements
Developed By: Jorge Ramirez
Latches and Flip-flops
• Latches
– Level sensitive circuit that passes inputs to Q when the
clock is high (or low) - transparent mode
– Input sampled on the falling edge of the clock is held
stable when clock is low (or high) - hold mode

• Flip-Flops (edge-triggered)
– edge sensitive circuits that sample the inputs on a clock
transition
• Positive edge-triggered: 0  1
• Negative edge-triggered: 1  0
– Built using latches (e.g., master-slave flip-flops)
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Sequential Elements
Developed By: Jorge Ramirez
Latches and Flip-flops

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Sequential Elements
Developed By: Jorge Ramirez
CMOS Latches
Pass Transistor Latch
Small
Fast
Vt drop
Dynamic output
Diffusion input Used in 1970’s

Output exposed

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Sequential Elements
Developed By: Jorge Ramirez
CMOS Latches
Transmission Gate Latch
No Vt drop
Requires inverted clock

Inverting Buffer Latch


Fixes noise problems
Inverter output

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Sequential Elements
Developed By: Jorge Ramirez
CMOS Latches
Latch with Tristate Feedback
Static latch

Latch with Buffered Input


Non-inverting

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Sequential Elements
Developed By: Jorge Ramirez
CMOS Latches
Robust transparent latch
Latch is static
Nodes swing rail-to-rail
State is isolate from noise
Input buffered

Widely used in standard cells

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Sequential Elements
Developed By: Jorge Ramirez
CMOS Flip-Flops
Dynamic inverting Flip-Flop

Non-Inverting Static Flip-Flop

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Sequential Elements
Developed By: Jorge Ramirez
Latches and Flip-Flop with Reset

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Sequential Elements
Developed By: Jorge Ramirez
Flip-flop with asynchronous set and
reset

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Sequential Elements
Developed By: Jorge Ramirez
Latches and Flip-Flop with Enable
• Enable: ignore clock when en is zero

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Sequential Elements
Developed By: Jorge Ramirez
SEQUENTIAL ELEMENT
CHARACTERIZATION
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Sequential Elements
Developed By: Jorge Ramirez
Timing parameters
• Setup Time (tsetup)
Minimum time before the clocking event by which the input
must be stable
• Hold Time (thold)
Minimum time after the clocking event during which the
input must remain stable
• Propagation Delay (tpd, tpcq, tpdq)
Minimum time after the input change to the output to
settle completely
• Contamination Delay (tcd, tccq, tcdq)
Maximum time after the input change to the output start to
change
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Sequential Elements
Developed By: Jorge Ramirez
Timing parameters

tpd Logic Propagation Delay


tcd Logic Contamination Delay
tpcq Latch/Flop Clk-Q Prop. Delay
tccq Latch/Flop Clk-Q Cont. Delay
tpdq Latch D-Q Prop. Delay
tcdq Latch D-Q Cont. Delay
tsetup Latch/Flop Setup Time
thold Latch/Flop Hold Time Synopsys University Courseware
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Sequential Elements
Developed By: Jorge Ramirez
Characterizing sequential element
Setup time
Fail region Variable tCQ Constant tCQ
Delay

tDQ=tDC+tCQ

Minimum tDQ

Setup time: tDC value at


– min tDQ
Slope = -1 – tCQ= tpcq

tsetup tCQ
tpcq
tccq

tDC
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Sequential Elements
Developed By: Jorge Ramirez
Characterizing sequential element
Hold time
Hold time: Minimum delay from clock
to D changing such that
tCQ ≤tpcq

Delay
tDQ
Minimum tDQ

Slope = -1
tpcq
tCQ tCQ
thold tsetup
tpcq

tCD tDC
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Sequential Elements
Developed By: Jorge Ramirez
tCQ vs tDC
• Longer tsetup and shorter
propagation delay for
low input than high
• The quoted delay for flip-
flop timing parameters,
it is customarily the
worst go the 0 and 1
delay
• Aperture width
tar = tsetup1 + thold0
taf = tsetup0 + thold1
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Sequential Elements
Developed By: Jorge Ramirez
tCQ vs tDC

Longer tsetup and shorter


propagation delay for low
input than high

Aperture width
tar = tsetup1 + thold0 The quoted delay for flip-
taf = tsetup0 + thold1 flop timing parameters, it
is customarily the worst
(bigger) value

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Sequential Elements
Developed By: Jorge Ramirez
Delay trace-offs

Adding delay to the input or output easy min-delay at the


expense of sequencing overhead
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Sequential Elements
Developed By: Jorge Ramirez
Delay trace-offs
• Delays vary with input slope, voltage and
temperature
– Contamination delay should be measure in
environment where it is shortest
– Setup and hold time and propagation delays
should be measure in environment where they are
longest
• Design can trade-off setup time, hold time and
propagation delay, adding a buffer (tbuff)
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Sequential Elements
Developed By: Jorge Ramirez
SEQUENCING STATIC CIRCUITS

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Sequential Elements
Developed By: Jorge Ramirez
Sequencing
• Combinational logic
– Output depends on current inputs
• Sequential logic
– Output depends on current and previous inputs
– Requires separating previous, current, future
– Examples:
clk clk clk clk

in out
CL CL CL

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Sequential Elements
Developed By: Jorge Ramirez
Timing – System that use sequential
elements
• Events need to prevent:
1. Data arrive to late to be capture reliably in the
next cycle
2. The data arrive too early (during the same cycle)
• Analyze time situation on a pipeline system
Xt Combinational Yt Xt+1 Combinational Yt+1
Logic Logic

Sn Sn+1

Clock
DCQ DCQ

U U

Y= Sn-1 Sn Sn+1
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Sequential Elements
Developed By: Jorge Ramirez
Sequencing Static Circuits

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Sequential Elements
Developed By: Jorge Ramirez
Sequencing Static Circuits
• Setup-time or max-delay violations
– Data arrives too late
• Sequencing overhead added by flip-flop and latches
• Combinational logic is too great
• Hold-time or min-delay violations
– Data arrives too early (during the same cycle)
• Data propagates thought 2 successive elements

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Sequential Elements
Developed By: Jorge Ramirez
Flip-Flop max delay constraints

TC ≥ tpcq + tpd + tsetup


tpd ≤ TC – (tsetup + tpcq)
Sequencing overhead
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Sequential Elements
Developed By: Jorge Ramirez
Two-phase latch max delay constraints

TC ≥ tpdq1 + tpd1 + tpdq2 + tpd2

tpd = tpd1 +tpd2 ≤ TC – (2tpdq)

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Sequential Elements
Developed By: Jorge Ramirez
Pulse latch max delay constraints

TC ≥ max {tpdq + tpd , tpcq + tpd +tsetup –tpw}


tpd ≤ TC – max {tpdq, tpdq +tsetup–tpw}
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Sequential Elements
Developed By: Jorge Ramirez
Flip-Flop min delay Constrains

tccq + tcd ≥ thold


tcd ≥ thold – tccq

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Sequential Elements
Developed By: Jorge Ramirez
Two-phase latch min delay Constrains

tnonoverlap+ tccq+ tcd1,2 ≥ thold


tcd1 ,tcd2 ≥ thold – tccq – tnonoverlap

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Sequential Elements
Developed By: Jorge Ramirez
Pulse latch min delay Constrains

tccq+ tcd ≥ thold + tpw


tcd ≥ thold – tccq + tpw

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Sequential Elements
Developed By: Jorge Ramirez
Clock Uncertainties
Data may arrive early or later because of the uncertainties
• Clock jitter
– Temporal variation of the clock signal manifested as uncertainty
of consecutive edges of a periodic clock signal.
– It is caused by temporal noise events
– Mainly characteristic of clock generation system
• Clock skew tDRVCLK

– Time difference between concurrent


edges of two periodic signals
– Caused by spatial variations in signal
Ref_Clock

tskew tskew
– Characteristic of clock distribution t jit
system t jit
Received Clock

Note: T

Will use tskew to represent all the uncertainties tRCVCLK

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Sequential Elements
Developed By: Jorge Ramirez
Flip-Flop system clock skew
Max delay worst case
tpd ≤ TC – (tsetup + tpcq + tskew)

Min delay worst case


tcd ≥thold + tskew – tccq

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Sequential Elements
Developed By: Jorge Ramirez
Latch base system clock skew
• Latch transparent systems
– Clock skew doesn’t degrade performance, if runs
slowly enough with sufficient nonoverlap time
tpd ≤ TC – (2tpdq)

– Skew increase the hold time in each half cycle


tcd1 ,tcd2 ≥ thold – tccq – tnonoverlap+ tskew

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Sequential Elements
Developed By: Jorge Ramirez
Latch base system clock skew
• Pulsed latch systems
– Can tolerate an amount of skew proportional to
the pulse width
tpd ≤ TC – max {tpdq, tpdq + tsetup– tpw + tskew}

– Skew increase the hold time


tcd ≥ thold – t ccq + tpw + tskew

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Sequential Elements
Developed By: Jorge Ramirez
References
• CMOS VLSI Design: A Circuits and
Systems Perspective. Neil Weste, David
Harris
• Digital System Clocking: High-
Performance and Low-Power Aspects.
Vojin G. Oklobdzija, Vladimir M.
Stojanovic
• Clocking Schemes for High-Speed
Digital Systems. Stephen h. Unger,
Chung-jen Tan
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Sequential Elements
Developed By: Jorge Ramirez

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