INTEL CORE 2 DUO

PROCESSOR

BY VAMSI KRISHNA (611738)

INTEL CORE 2 DUO PROCESSOR
This Processor consists of two cores hence known as core 2
duo. It has the two cores working in parallel at the same
frequency in the same processor.
It is a 16-bit processor.
The core 2 duo was introduced on July 27,2006 as the successor
of core duo processor.. It was a 65nm technology with Pentium
M micro architecture as the internal core architecture.
INTEL CORE 2 DUO

Name of the processor Intel core 2 duo E440

Code name Conroe

Package Socket 775LGA

Technology 65nm
ARCHITECTURE OF
CORE 2 DUO
PROCESSOR

 General overview of Core 2

Duo Architecture
ASSOCIATIVITY OF CORE 2 DUO

The core 2 duo processor follows 8 way set associativity in L1

cache And 16 way set associativity in L2 cache. The associativity is
must between the two
 CORE SPECIFICATIONS

Number of Cores - 2

Number of Threads – 8

Pentium M microarchitecture
Pentium M microarchitecture
The Pentium M is a family of mobile 32-bit single-
core x86 microprocessors (with the modified
Intel P6 microarchitecture) introduced in March
2003 and forming a part of the Intel Carmel
notebook platform under the then new Centrino SOMEONE@EXAMPLE.COM
brand. Arch
CPU
Type
Designer Intel
Manufact
Intel
urer
Introducti
2003
on
Phase-out 2005
Process 130 nm, 90 nm
 CORE PERFORMANCE

Number of cores 2

Number of threads 6

Core 1 operating frequency 1.6Ghz

Core 2 operating frequency 1.6Ghz

INTEL CORE 2
DUO INTERNAL
STRUCTURE
CACHE MEMORY

The processor consists of

512kb of smart L1 cache memory
2 to 4 MB L2 cache memory

The L2 cache memory can be extended to a maximum of 6MB as

shared L2 cache memory.
ARCHITECTURE OF
INTEL CORE 2 DUO
PROCESSOR

 General surface architecture of

Core 2 Duo processor
ASSOCIATIVITY IN CORE 2 DUO

 Associativity is crucial in the implementation of high performance computing

architectures for applications that require intensive data management or are
cognitive in nature. The basic architecture of associative memories can be based
on either the exact match or neural network models. This paper focuses on exact
match associative memories.
 Core 2 duo has
 8-way set associativity in L1 cache
 16-way set associativity in L2 cache
SPECIFICATIONS

 Data Cache : 32kb Dual port data cache

 Instruction cache : 32kb of Instruction cache
 Size of Fetch Buffer : 32kb pre-Decoded cache
 Instruction Queue : 18 entry instruction queue
PARALLEL
PROCESSING
 TLB IN CORE 2 DUO
 A translation lookaside buffer (TLB) is a memory cache that stores recent translations of virtual memory to
physical address for faster retrieval.
 When a virtual memory address is referenced by a program, the search starts in the CPU. First, instruction caches
are checked. If the required memory is not in these very fast caches, the system has to look up the memory’s
physical address.At this point,TLB is checked for a quick reference to the location in physical memory.
 When an address is searched in the TLB and not found, the physical memory must be searched with a memory
page crawl operation.As virtual memory addresses are translated, values referenced are added to TLB. When a
value can be retrieved from TLB, speed is enhanced because the memory address is stored in the TLB on
processor. Most processors include TLBs to increase the speed of virtual memory operations through the inherent
latency-reducing proximity as well as the high-running frequencies of current CPU’s.

 Size of TLB : 256 entry L1 DTLB

128 entry ITLB
256 entry L2 DTLB and 16 entry Data cache DTLB
DECODERS IN CORE 2 DUO

Core 2 duo has a total

number of 5 decoders
One for decoding code and
the remaining are for
decoding the other
instructions
RESERVATION STATION

 Unified Reservation station, also known as unified scheduler, is a decentralized feature of

the microarchitecture of a CPU that allows for register renaming, and is used by the Tomasulo algorithm for
dynamic instruction scheduling.
 Reservation stations permit the CPU to fetch and re-use a data value as soon as it has been computed, rather
than waiting for it to be stored in a register and re-read. When instructions are issued, they can designate the
reservation station from which they want their input to read. When multiple instructions need to write to the
same register, all can proceed and only the (logically) last one need actually be written. It checks if the operands
are available (RAW) and if execution unit is free (Structural hazard) before starting execution.
 Reservation Station in core 2 duo : 32 entry reservation station
LOAD AND STORE QUEUE

 In computer engineering, a load–store architecture is an instruction set architecture that divides instructions
into two categories: memory access (load and store between memory and registers), and ALU operations (which
only occur between registers).
 RISC instruction set architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.
 For instance, in a load–store approach both operands and destination for an ADD operation must be in registers.
This differs from a register–memory architecture (for example, a CISC instruction set architecture such as x86)
in which one of the operands for the ADD operation may be in memory, while the other is in a register.
 The earliest example of a load–store architecture was the CDC 6600 Almost all vector processors (including
many GPUs) use the load–store approach.

 Load and store queue in core 2 duo : 128 bit load and store queue
INSTRUCTION QUEUE

 Fetching the instruction opcodes from program memory well in advance is known as prefetching and it is served
by using prefetch input queue (PIQ).The pre-fetched instructions are stored in data structure - namely
a queue. The fetching of opcodes well in advance, prior to their need for execution increases the overall efficiency
of the processor boosting its speed. The processor no longer has to wait for the memory access operations for
the subsequent instruction opcode to complete. This architecture was prominently used in the Intel
8086microprocessor.

 Instruction Queue in core 2 duo : 18 entry instruction queue

SPECIAL FEATURES

Advanced Smart Cache (ASC) :

• Intel says: "Smart Cache provides a higher- Digital Media Boost :
performance, more efficient cache sub-system
• Intel says: "Accelerates a broad range of
that's optimized for multi-core and dual-core
applications, including video, speech and image,
processors."
photo processing, encryption, financial,
• We say: All processors have their own memory engineering and scientific applications."
- the cache - to record frequently used data so
• We say: Core 2 Duo increases the rate at which
the information can be grabbed more quickly.
SSE, SSE 2 and SSE 3 128-bit SIMD instructions
Add a second core to the CPU and you need to
can be processed so that each takes a single
add more cache. Each core can have its own
clock tick to execute rather than the two or
cache, but ASC allows them to share all the
available cache memory in whatever way that more clock cycles they've taken in the past.
makes most sense for each core's workload. Media processing code, security, engineering
and scientific applications all stand to benefit, as
That allows the two core to operate more
will games.
efficiently, which means faster processing for
you.
SPECIAL FEATURES

Enhanced SpeedStep (EIST) :

• Intel says: "Enhanced Intel Speedstep Technology allows the system to dynamically
adjust processor voltage and core frequency, which results in decreased power
consumption."
• We say: EIST allows your processor to slow down to a speed that's appropriate for
the task you're performing, and to speed up again when it needs that extra welly.
You always get the processing power you need but without using excess electrical
power - for which read 'battery life', if you're a notebook user. It also means your
machine doesn't run hot, allowing its cooling fans to run more quietly.
SPECIAL FEATURES
Smart Memory Access (SMA) :
• Intel says: "SMA improves system performance by
optimizing the use of the available data bandwidth."
• We say: Core 2 Duo chips are better at getting the right
information from the right chunk of memory at the right
time. That allows the chip to continue processing your
data without having to wait while the wrong information
is ditched and the correct stuff retrieved and used in its
place. Again, that makes for faster-running apps.
Execute Disable Bit :
• Intel says: "A malicious worm can create a flood
of code that overwhelms the processor. Execute
Disable Bit allows the processor to classify
areas in memory where application code can
execute and where it cannot. When a malicious
worm attempts to insert code in the buffer, the
processor disables code execution, preventing
damage and worm propagation."
• We say: Execute Disable Bit is a hardware
feature within the processor that acts as a
safety catch to prevent a virus sneaking in nasty
software code. It requires OS support which
was added in Windows XP Service Pack 2 and
of course you still need anti-virus, firewall,
spyware removal and e-mail filtering software to
keep all the other nasties at bay.