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DATA SHEET

MOS FIELD EFFECT TRANSISTOR


2SK3116
SWITCHING
N-CHANNEL POWER MOS FET

DESCRIPTION ORDERING INFORMATION


The 2SK3116 is N-channel DMOS FET device that features a PART NUMBER PACKAGE
low gate charge and excellent switching characteristics, and
2SK3116 TO-220AB
designed for high voltage applications such as switching power
supply, AC adapter. 2SK3116-S TO-262

2SK3116-ZJ TO-263

FEATURES
•Low gate charge
QG = 26 nC TYP. (ID = 7.5 A, VDD = 450 V, VGS = 10 V)
•Gate voltage rating ±30 V
•Low on-state resistance
RDS(on) = 1.2 Ω MAX. (VGS = 10 V, ID = 3.75 A)
•Avalanche capability ratings

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)


Drain to Source Voltage (VGS = 0 V) VDSS 600 V
Gate to Source Voltage (VDS = 0 V) VGSS ±30 V
Drain Current (DC) ID(DC) ±7.5 A
Note1
Drain Current (pulse) ID(pulse) ±30 A
Total Power Dissipation (TA = 25°C) PT1 1.5 W
Total Power Dissipation (TC = 25°C) PT2 70 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg −55 to +150 °C
Note2
Single Avalanche Current IAS 7.5 A
Note2
Single Avalanche Energy EAS 37.5 mJ
Note3
Diode Recovery dv/dt dv/dt 3.5 V/ns

Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%

2. Starting Tch = 25°C, VDD = 150 V, RG = 25 Ω , VGS = 20 → 0 V


3. IF ≤ 3.0 A, Vclamp = 600 V, di/dt ≤ 100 A/ µs, TA = 25°C

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. D13339EJ2V0DS00 (2nd edition) The mark ★ shows major revised points. © 1998
Date Published May 2002 NS CP (K)
Printed in Japan
2SK3116

ELECTRICAL CHARACTERISTICS (TA = 25°C)


CHRACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Zero Gate Voltage Drain Current IDSS VDS = 600 V, VGS = 0 V 100 µA
Gate Leakage Current IGSS VGS = ±30 V, VDS = 0 V ±100 nA

Gate Cut-off Voltage VGS(off) VDS = 10 V, ID = 1 mA 2.5 3.5 V


Forward Transfer Admittance | yfs | VDS = 10 V, ID = 3.75 A 2.0 S
Drain to Source On-state Resistance RDS(on) VGS = 10 V, ID = 3.75 A 0.9 1.2 Ω
Input Capacitance Ciss VDS = 10 V 1100 pF
Output Capacitance Coss VGS = 0 V 200 pF
Reverse Transfer Capacitance Crss f = 1 MHz 20 pF
Turn-on Delay Time td(on) VDD = 150 V, ID = 3.75 A 18 ns
Rise Time tr VGS = 10 V 15 ns
Turn-off Delay Time td(off) RG = 10 Ω 50 ns

Fall Time tf RL = 50 Ω 15 ns

Total Gate Charge QG VDD = 450 V 26 nC


Gate to Source Charge QGS VGS = 10 V 6 nC
Gate to Drain Charge QGD ID = 7.5 A 10 nC
Body Diode Forward Voltage VF(S-D) IF = 7.5 A, VGS = 0 V 1.0 V
Reverse Recovery Time Trr IF = 7.5 A, VGS = 0 V 1.6 µs
Reverse Recovery Charge Qrr di/dt = 50 A/ µs 7.6 µC

TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME

D.U.T. D.U.T. VGS


RG = 25 Ω L RL 90%
VGS VGS
Wave Form 10%
RG 0
PG. 50 Ω VDD PG. RG = 10 Ω VDD
VGS = 20 → 0 V ID 90%
90%
VGS ID
BVDSS 10% 10%
0 ID 0
IAS Wave Form

ID VDS τ td(on) tr td(off) tf


VDD
τ = 1 µs ton toff
Duty Cycle ≤ 1%
Starting Tch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.
IG = 2 mA RL

PG. 50 Ω VDD

2 Data Sheet D13339EJ2V0DS


2SK3116

TYPICAL CHARACTERISTICS (TA = 25°C)

DRAIN CURRENT vs. FORWARD TRANSFER CHARACTERISTICS


DRAIN TO SOURCE VOLTAGE

Pulsed
25
100
Tch = 125˚C
VGS = 10 V

ID - Drain Current - A
20 75˚C
ID - Drain Current - A

8V 10
15
1.0 Tch = 25˚C
6V −25˚C
10

0.1
5
VDS = 10 V
Pulsed
0 10 20 30 40 0 5 10 15
VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V

GATE CUT-OFF VOLTAGE vs. FORWARD TRANSFER ADMITTANCE vs.


CHANNEL TEMPERATURE DRAIN CURRENT
5.0 10
| yfs | - Forward Transfer Admittance - S
VGS(off) - Gate Cut-off Voltage - V

Tch = −25˚C
4.0 25˚C
75˚C
125˚C
3.0
1.0
2.0

1.0
VDS = 10 V
VDS = 10 V
ID = 1 mA Pulsed
0 0.1
−50 0 50 100 150 0.1 1.0 10
Tch - Channel Temperature - ˚C ID - Drain Current - A

DRAIN TO SOURCE ON-STATE RESISTANCE vs.


DRAIN TO SOURCE ON-STATE
RDS (on) - Drain to Source On-State Resistance - Ω

GATE TO SOURCE VOLTAGE


RESISTANCE vs. DRAIN CURRENT
RDS(on) - Drain to Source On-State Resistance - Ω

3.0
Pulsed 3.0 Pulsed

2.0
2.0
ID = 4.0 A
7.5 A
VGS = 10 V
20 V
1.0
1.0

0
0 5 10 15 0 1.0 10 100
VGS - Gate to Source Voltage - V ID - Drain Current - A

Data Sheet D13339EJ2V0DS 3


2SK3116

DRAIN TO SOURCE ON-STATE RESISTANCE vs. SOURCE TO DRAIN DIODE


RDS (on) - Drain to Source On-State Resistance - Ω
CHANNEL TEMPERATURE FORWARD VOLTAGE

4.0

ISD - Diode Forward Current - A


100

3.0
10

ID = 7.5 A
2.0 4.0 A
1.0

VGS = 10 V 0V
1.0 0.1
VGS = 10 V
Pulsed Pulsed
0
−50 0 50 100 150 0 0.5 1.0 1.5
Tch - Channel Temperature - ˚C VSD - Source to Drain Voltage - V

CAPACITANCE vs. DRAIN TO


SOURCE VOLTAGE SWITCHING CHARACTERISTICS
100
td(off)
td(on), tr, td(off), tf - Switching Time - ns
Ciss, Coss, Crss - Capacitance - pF

10000
tf

Ciss 10 td(on)
1000

100 Coss tr
1

10
VDD = 150 V
VGS = 0 V Crss VGS = 10 V
f = 1 MHz RG = 10 Ω
1 0.1
1.0 10 100 1000 0.1 1 10
VDS - Drain to Source Voltage - V ID - Drain Current - A

REVERSE RECOVERY TIME vs.


DRAIN CURRENT DYNAMIC INPUT/OUTPUT CHARACTERISTICS
10000 16
di/dt = 50 A/ µs
ID = 7.5 A
VGS = 0 V
VDS - Drain to Source Voltage - V

VGS - Gate to Source Voltage - V


trr - Reverse Recovery Time - ns

14
VDD = 450 V
600 12
300 V
1000 150 V
VGS 10

400 8

6
100
200 4
VDS
2

10 0
0.1 1.0 10 100 0 8 12 20 32
ID - Drain Current - A QG - Gate Charge - nC

4 Data Sheet D13339EJ2V0DS


2SK3116

★ DERATING FACTOR OF FORWARD BIAS ★ TOTAL POWER DISSIPATION vs.


SAFE OPERATING AREA CASE TEMPERATURE
100 80
dT - Percentage of Rated Power - %

PT - Total Power Dissipation - W


70
80
60

60 50

40
40 30

20
20
10

0
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160
TC - Case Temperature - ˚C TC - Case Temperature - ˚C

FORWARD BIAS SAFE OPERATING AREA

100

ID(pulse)
PW
=
10
ID - Drain Current - A

d µs
ite 10
10 Lim
0
ID(DC) µs
)
on 1
S( m
RD s

Po 3
we 10 ms
3 m
r Di 10 0 m s
0 s
ss DC ms
ipa
1 tio
n
Lim
ite
d

TC = 25˚C
Single Pulse
0.1
1 10 100 1000
VDS - Drain to Source Voltage - V

★ TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH


rth(t) - Transient Thermal Resistance - ˚C/W

100 Rth(ch-A) = 83.3˚C/W

10

Rth(ch-C) = 1.79˚C/W
1

0.1

0.01
10 µ 100 µ 1m 10 m 100 m 1 10 100 1000
PW - Pulse Width - s

Data Sheet D13339EJ2V0DS 5


2SK3116

SINGLE AVALANCHE CURRENT vs. SINGLE AVALANCHE ENERGY


INDUCTIVE LOAD DERATING FACTOR
100 120
VDD = 150 V
IAS - Single Avalanche Current - A

RG = 25 Ω
100 VGS = 20 → 0 V

Energy Derating Factor - %


IAS ≤ 7.5 A
10 IAS = 7.5 A 80
EAS
=3
7.5
mJ
60

1.0 40
RG = 25 Ω
VDD = 150 V 20
VGS = 20 → 0 V
Starting Tch = 25˚C
0.1 0
10 µ 100 µ 1m 10 m 25 50 75 100 125 150
L - Inductive Load - H Starting Tch - Starting Channel Temperature - ˚C

6 Data Sheet D13339EJ2V0DS


2SK3116

★ PACKAGE DRAWINGS (Unit: mm)

1) TO-220AB (MP-25) 2) TO-262 (MP-25 Fin Cut)

4.8 MAX.

1.0±0.5
10.6 MAX. 4.8 MAX.
3.0±0.3

φ 3.6±0.2 10 TYP. 1.3±0.2


1.3±0.2
10.0 TYP.

8.5±0.2
5.9 MIN.

15.5 MAX.
4
1 2 3
4

12.7 MIN.
1 2 3
1.3±0.2
6.0 MAX.

12.7 MIN.

1.3±0.2
0.75±0.3 0.5±0.2 2.8±0.2
2.54 TYP. 2.54 TYP.
0.75±0.1 0.5±0.2 2.8±0.2
1.Gate
2.54 TYP. 2.54 TYP. 2.Drain
1.Gate 3.Source
2.Drain 4.Fin (Drain)
3.Source
4.Fin (Drain)

3) TO-263 (MP-25ZJ)

10 TYP. 4.8 MAX.


1.3±0.2
4 EQUIVALENT CIRCUIT
1.0±0.5

8.5±0.2

Drain (D)
1 2 3
5.7±0.4

1.4±0.2 P.
TY Body
R P.
0.7±0.2 0.5 TY 0.5±0.2 Gate (G) Diode
R
2.54 TYP. 2.54 TYP. 0.8

1.Gate
2.Drain Source (S)
3.Source
2.8±0.2

4.Fin (Drain)

Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade
the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.

Data Sheet D13339EJ2V0DS 7


2SK3116

• The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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M8E 00. 4

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