Types of degradation modes of AIGaN/GaN high
electron mobility transistors (HEMTs) in dependence
on epitaxial design and buffer quality
Abstract- DC-Step-Stress tests have been applied on wafers
as a fast AIGaN/GaN HEMTs robustness screening method with
different epitaxial designs. The results showed three types of
early degradation which are permanent and are dependent on
epitaxial design and GaN buffer quality. The criterion of critical
voltage is defined for the onset of degradation
subthreshold drain current and/or gate leakage current increase
significantly in a step source-drain voltage during stress test. It
has been found that AIGaN/GaN HEMT devices with GaN cap
show higher critical source-drain voltages as compared to non­
capped devices. Devices with low AI concentration in the AIGaN
barrier layer also show higher critical source-drain voltages.
Superior stability and robustness performance have
achieved from devices with AIGaN backbarrier epitaxial design
grown on n-type silicon carbide substrate. It is found that high
electric field under the gate at the drain side is the main cause of
degradation. Consequently careful epitaxial design to reduce
high electric field is required. It is also shown that epitaxial
buffer quality and growth process have a great impact on device
robustness.
Keywords- GaN device; reliability; degradation
I. INTRODUCTION
AIGaN/GaN high electron mobility transistors (HEMTs)
are promlSlng candidates for microwave and power
applications with high breakdown field �3MVIcm, high
electron mobility �1200cm21V.s, and saturation velocity about
3xl07cmls. However, they have problems concerning device
degradation which is not fully understood and needs further
investigation [1-2]. So far, two degradation mechanisms are
explained by inverse piezoelectric effect [3] and hot electron
[4-5]. In this paper, a study of varied epitaxial design of
AIGaN/GaN HEMTs is shown in order to understand the
degradation mechanism. High electric field under the gate at
the drain side is known as the main cause of degradation. The
electric field distribution in AIGaN/GaN HEMTs has been
studied by electroluminescence [6-7] and in this paper is also
performed and supported by electric field simulations.
II. EXPERIMENT
AIGaN/GaN HEMTs with varied epitaxial design have been
fabricated in Ferdinand-Braun-Institut, Leibniz-Institut flir
Hoschstfrequenztechnik Berlin (FBH), Germany by metal
organic vapor phase epitaxy (MOVPE) in crystal direction
978-1-4799-6551-9115/$31.00 ©2015 IEEE
Ponky Ivo
Indonesia
ponky.ivo@gmail.com
(0001) with gallium face surface. GaN layer has been grown
on SiC substrate and on top of it, a thin AIGaN layer is
deposited. The total polarizations of spontaneous and
piezoelectric fields induce charges at the interface between
AIGaN and GaN layers which form two dimensional electron
when a
gas (2DEG) channel. Source and drain ohmic contacts are
TilAl/TilAu with low resistance to n-GaN and the Schottky
contacts use Pt/TiI Au stack metallization.
Wafer epitaxial design variation list is shown in Table 1.
Device under test (DUT) is 2x125/lm with 0.5/lm gate length;
been l/lm Source-Gate and 6/lm Gate-Drain spacing with SiN
passivation (see Fig. 1). Breakdown is defined when drain
current reach 1 rnA/mm at VGS -7V. Wafer "A" is considered
=
as a reference which is deposited on semi insulating (SI) SiC
substrate. Wafer "B" has relatively a thick AIGaN layer of
35nm and wafer "c" has a relatively less Al concentration of
18%. Wafer "D" has a 5nm-GaN cap with Si-doped of
7x1018/cm3 on top of AIGaN layer. Wafer "E", "F" and "G" are
deposited on n-type (n) SiC substrate with wafer "F" has
AIGaN buffer with 5% AI with GaN channel of 15nm, and "G"
has relatively thin GaN buffer. Breakdown VBR is � 30V for
wafer "A", "B", "E". Wafer "C", "D" and "G" have VBR is �
60V and wafer "F" has the highest VBR is � 150V. Threshold
voltage VTH of all devices is � -2V.
� Gate I SL'i �
�I��G�
��----�--------�I
2DEG
Gal"
SiC substrate
Fig. 1. Schematic basic diagram of A1GaN/GaN HEMTs (not in a right scale).
DC-Step-Stress tests have been performed on wafer at
room temperature at VGS -7V with a ramp 5V VDS every two
=
hours. During the stress, gate leakage IG and subthrehold drain
current ID were observed. Before, during and after stress, IV­
characteristics were performed. Optical characterization with
electroluminescence (EL) using PHEMOS 1000 photo
emiSSIOn microscopy (PEM) from Hamamatsu with
34 2015 International Conference on Quality in Research
wavelength range 450-lO50 run was carried out at Technische thin GaN buffer layer "G" has a dramatic increase of ID and
Universitat Berlin. the meantime IIGI is very small < lllA/mm (see Fig. 3 (b)).

120
TABLE I. LIST OF WAFER EPITAXIAL OESIGN PARAMETER
100
AL,GaJ.xN dbuffa(/lm) SiC
Wafer
�ed
x(%) d(8nm) GaN type
0.4 80
�
'E trap
A 23 25 2.33 ST charging �
0.8 6O�
E
B 23 35 2.31 Sl ::>
1i
� 1. 2 40
C 18 25 2.43 ST

D' 24 25 2.52 ST 1.6 20

E 23 30 2.4 n 0
36
F 23 30 1.84b n (a)

G 25 25 1.75 n 120
a. Wafer "D" has a 5nm-GaN cap
100
b. Wafer "F" has AJGaN buffer with 5% AI and GaN channel of 1 Snm.
0.4 80
III. RESULT AND DISCUSSION f
�
�
0.8 60 �
Typical results of DC-Step-Stress tests on wafer are shown ::,;
in Fig. 2 and 3. Point of degradation is defined when gate
leakage IG and/or subthreshold drain current ID increase over
�
(5
1.2 40

20% within one step (see Fig 2). In Fig. 2 (a), the third until 1.6 20
the fifth step shows charge trapping within one step of Vos.
The charges flowing to gate and to drain are captured by the 20 0
o 4 8 12 16 20 24 28 32 36 40 44 48
trapping centers i.e. defects or surface states. At Vos of 30V, Time (h) (b)
absolute gate leakage IIGI and subthreshold drain current 10 Fig. 2. OC-Step-Stress test results from device of wafer (a) "A" with VCR of30V
increase which is defined as point of degradation VCR. The and To > 1101, and (b) "0" with VCR of 60V. Note: 10 and 1101 are on top of each
VCR of wafer "B" with 35run AIGaN barrier layer is 30V � other.
which its thickness is far beyond the critical thickness about -OA 120

70 run for relaxation of tensile strained AIGaN with 23% AI 100

[8]. The gate leakage increase which is associated with drain
and source resistance increase and drain output current E OA
Point of so

decrease have been observed by Ref. [3]. This is due to �

E
0.8
degradation
6O�
-;:.'8
inverse piezoelectric effect as a result of applied high electric
::0 1.2 40
field which adds tensile strain in AIGaN barrier layer. The
�
total strain can exceed beyond crystal elasticity, and - 1.6
r-- 20

consequently crystallographic defects can be created which -� \

2.0 0
-2 6 8 10 12 14
can be a pathway for the charges from gate electrode to Time (h)
penetrate into AIGaN barrier layer via hopping mechanism. (a)
.0.4 l
POint � E'j 120
Wafer "C" and wafer "D" with less AI concentration of
18% and a GaN cap respectively have similar results of
0.0 f.1 degadation
100
"':\ \
1
relatively high point of degradation at about 60V. Both IIGI and 0.4
10 IG III

�
�t\
10 increase simultaneously. It is shown that if AI concentration 0.8 oo�
��
in AIGaN layer is less than 20%, the epilayer is smooth without
:91.2
� 1.6
crack and less threading dislocation density [9], therefore VCR
_--e--- .
is higher than that of reference. 20
\
In buffer comparison, wafer "E" vs. wafer "F" have been 20 0

grown on n-type SiC substrate. Device "E" has similar 30V -2 0 2 4 6 8 10 12 14 16 18 20 22 2A 26

lime (h) (b)
VCR as the reference regardless the type of SiC substrate with
simultaneously increase of IIGI and ID (see Fig. 3 (a)). Device Fig. 3. OC-Step-Stress test results from device of wafer (a) "E" with VCR ofJOV,
"F" with AIGaN backbarrier shows no degradation up to and (b) "G" with VCR of 50V, low ITol «I/lAlmm) and very abrupt increase of
10. ELI and EL2 indicate the electroluminescence measurements before and
l20V, the limit of stress test setup (not shown). Device with after stress respectively.

35
 1.2 .----.-�___,_�____,r_�_,_�_:_r:_�---,---r- --, ,....,
- virgin
-after35V
1.0 - rf!£C:Nf!rY after 1 week
2V
0.8

J�
� 0.6

0.4

0.2

0.0

0 5 10 15 20 25 30 (a)

Vos(V) (a)
1.2

1.0
- vi rgi n
-after40V
0.8

ICi: 0.6

0.4
_!!3
0.2

0.0 (b)

0 5 10 15 20 25 30 Fig. 5. Normalized EL intensity vs. IV-output at VDS = IOV of (a) wafer "E"
and (b) wafer "G" before (black) and after stress (red) as marked by ELI and
VooM (b) EL2 in Fig. 3.
Fig. 4. TV static characteristics of device before and after stress at each V a
To Source To Drain To Source To Drain
with 1V V as step from (a) wafer "E" shows knee walk-out and (b) wafer "G"
is broken. The degradation is permanent after one week as shown in (a) with
green lines.

Optical characterization with EL measurements have been

carried out at VDS lOV, -7V<VGs<2V (see Fig 5). Virgin
=

devices show a bell-shaped curved along the IV-output with

its peak at 1;' of linear regime. After stress, the EL peak drops
and shifts to more positive VGS. It is believed that after stress,
there is irreversibly degradation occurrence which is
associated with crystallographic defects after stress. A broken
device "G" is not dimmed out at VGS>OV. There is additional
emission which is associated with a severe degradation with a
significant drop of output current. From XRD "rocking curve"
(a)
during GaN epitaxial growth, wafer "G" has relatively high
edge dislocation density � 1.4x109 cm-2 which is almost
double as wafer "E" of 8xl08 cm-2• Hence, wafer "G" is more
prone to degrade. Further investigation of this severe
degradation mechanism showed that devices of wafer "G"
have void at the gate walls and nm scale unpassivated surface
at the gate foot [10].

Electric field simulations between device "A" without GaN

cap and "D" with GaN cap shows electric field distribution
under the gate area (see Fig. 6). Device "A" has relatively high
electric fields �107 V/cm at the comer under the gate at the
drain side meanwhile device "D" with GaN cap has less than a
half of it �3xl06 V/cm. Clearly, GaN cap in device "D" blocks (b)
the high electric field under the gate comer at the drain side
Fig. 6. (a) Electric field simulation under the gate device between device "A"
which has less additional strain in AIGaN layer and explains without GaN cap and device "D" with GaN cap (b) The electric field
the 60V VCR of device "D" [11]. magnitude under the gate marked by a black line in (a).

36
 Band energy simulation comparison between device "E"
with GaN buffer and device "F" with AIGaN buffer show that
device "F" has higher conductive band energy (see Fig. 7).
This prevents the electrons to AIGaN buffer layer, thus no
leakage occurrence during stressing which explain no
degradation. Electric field simulation under the gate corner at
the drain side cross) of device "E" and "F" are 6.5MVfcm �
and 2MVfcm respectively (marked with a red cross in Fig. 7
�
(b) and (c)).
, � To Source To Or.1O 7
. �l
E(MV/cm)
, prevents the leakage. Severe degradation occurred is from
,
r
AIoooGaa.,.N buIfer
-GaNbuffer
(b)
� To Source To 011110 7
I
\J
x coordinate (..,,)
(a) (c)
Fig. 7. (a) Band energy simulation of device "E" with GaN buffer (black line)
and "F" with AIGaN buffer (red line). Electric field simulation of device of
device (b) "E" and (c) "F" at V DS = 45V and V as = -6V.
Three types of degradation modes have been observed for
this study on eight wafers with varied epitaxial design.
1) 10 IIGI
= discussions at Ferdinand-Braun-Institut, Leibniz-Institut fUr
Wafers "C", "D", and "E" with 18% AI, GaN cap and n­
type SiC substrate respectively have symmetric increase
of subthreshold drain current and absolute leakage
current. It is believed in this case that charges from the
gate penetrate through the AIGaN barrier layer via
hopping mechanism and flowing along the interface
between AIGaN and GaN layers (as 2DEG is not depleted
outside the area under the gate) and go to drain electrode.
2) 10 > IIGI
Wafer "A" is a reference and wafer "B" with 35 urn
AIGaN layer have asymmetric increase. At VCR the
subthreshold drain current increase more than gate
leakage because there is additional charges flow from the
source bypassing the high electric field under the gate
diving into the buffer known as punchthrough [12]. It is
likely that these charges altogether with charges from the
gate (gate leakage) flow together in the interface of
AIGaN and GaN and end at the drain contact.
3) IIGI -7 0 and 10 increases dramatically
Wafer "G" with a thin GaN buffer of 1.7/lm (double of
edge dislocation density as the reference on n-type SiC
substrate) with void at gate wall and /lm unpassivated
surface is much more prone to degrade. The charges from
37
the gate are accumulated into the unpassivated surface
(positive charges) which might explains a severe drop of
drain current output in Fig. 4 (b).
IV. CONCLUSION
DC-Step-Stress tests have been performed as a fast
robustness tests on wafer with varied epitaxial designs. It has
shown that device with GaN cap and low Al concentration are
robust due to the cap which "blocks" electric field under the
gate at the drain side and less strain in AIGaN layer
respectively. The most robust device is from wafer "F" with
AIGaN buffer which has high conductive band energy thus
wafer "G" which has void at the gate wall and unpassivated
surface in the gate periphery. Moreover, it has more dislocation
density due to relatively thin GaN buffer of 1.7/lm. Altogether,
device from wafer "G" is more prone to degradation. Three
modes of degradation have been observed which strongly
depend on the epitaxial design, process technology and buffer
quality. It is very important to reduce electric field under the
gate at the drain side by field plate, slanted gate and GaN cap
as well as to improve epitaxial buffer quality and process
technology.
ACKNOWLEDGMENT
This research has been funded by Deutsche Akademische
Austauch Dienst (DAAD) and performed at Ferdinand-Braun­
Institut, Leibniz Institut fUr H6schstfrequenztechnik Berlin
(FBH), Germany. The author thanks to Dr. Eldad Bahat­
Treidel for electric field simulation and samples, Dr. Joachim
WUrfl and Prof. GUnther Trankle for their guidance and fruitful
H6schstfrequenztechnik Berlin (FBH), Dr. Arkadius Glowacki
and Prof. Christian Boit at Technische Universitat Berlin for
their assistance of optical characterization with PEM.
REFERENCES
[I] G. Meneghesso, M. Meneghini, A. Tazzoli, N. Ronchi, A. Stocco, A.
Chini and E. Zanoni, "Reliability issues of Gallium Nitride High
Electron Mobility Transistors", International Journal of Microwave and
Wireless Technologies, 2 (1), pp. 39-50, 2010.
[2] J. Wuertl, E. Bahat-Treidel, F. Brunner, E. Cho, O. Hilt, P. T vo, A.
Knauer, P. Kurpas, R. Lossy, M. Schulz, S. Singwald, M. Weyers, R.
Zhytnytska, "Reliability issues of GaN based high voltage power
devices", Microelectronics Reliability 51, pp. 1710-1716,2011.
[3] Joh, L. Xia, and 1. A. del Alamo, "Gate Current Degradation
Mechanisms of GaN High Electron Mobility Transistors", IEDM, IEEE,
pp. 385-388,2007.
[4] D. K. Sahoo, R. K. Lal, H. Kim, V. Tilak, and L. F. Eastman, "High­
Field Effects in Silicon Nitride Passivated GaN MODFETs", IEEE
Trans. El. Dev., vol. 50, no. 5, pp. 1163-1170,2003.
[5] G. Meneghesso,G. Verzellesi, F. Danesin, F. Rampazzo, F. Zanon, A.
Tazzoli, M. Meneghini, and E. Zanoni, "Reliability of GaN High­
Electron-Mobility Transistors: State of the Art and Perspectives", IEEE
Trans. Dev. Mat. Reliability, vol. 8, no. 2, pp. 332-343,2008.
[6] N. Shigekawa, K. Shiojima, and T. Suemitsu, "Electroluminescence
characterization of AIGaNOGaN high-electron-mobility Transistors",
Appl. Phys. Lett. 79, (8), 2001, ibid N. Shigekawa, K. Shiojima, and T.
Suemitsu, "Optical study of high biased AIGaN/GaN high-electron­
mobility transistors", 1. Appl. Phys., 92 (1), pp. 531-535,2002.
[7] R. J. T. Simms, F. Gao, Y. Pei, T. Palacios, U. K. Mishra, and M. 100nm scale unpassivated regions around the gate
Kuball, "Electric field distribution in AIGaN/GaN high electron mobility periphery",Microelectronics Reliability 54, pp. 1288-12 92 ,2014.
transistors investigated by electroluminescence", Appl. Phys. Lett. 97, [11] P. Ivo, A. Glowacki, R. Pazirandeh, E. Bahat-Treidel, R. Lossy, 1. WUrl,
033502,2010. C. Boit, G. Triinkle, "lnfuence of GaN cap on robustness of AIGaN/GaN
[8] S. R. Lee, D. D. Koleske, K. C. Cross, 1. A. Floro, K. E. Waldrip, A. T. HEMTs", IEEE International Reliability Physics Symposium (IRPS),
Wise and S. Mahajan, In situ measurements of the critical thickness for pp. 71-75,2009.
strain relaxation in A1GaN/GaN heterostructures, Appl. Phys. L ett.85 [12] E. Bahat-Treidel, O. Hilt, F. Brunner, J. WUrl, and G. Triinkle,
(25 ), pp. 6164-6166,2004. "Punchthrough-Voltage Enhancement of AIGaN/GaN HEMTs Using
[9] R. Loganathan, M. Jayasakthi, K. Prabakaran, R. Ramesh, P. AIGaN Double-Heterojunction Confinement", IEEE Transactions on
Arivazhagan, K. Baskar, "Studies on dislocation and surface Electron Devices 55 (12), pp. 3354-3359,2008.
morphology of AlxGal-xN/GaN heterostructures grown by MOCVD",
Journal of Alloys and Compounds 616, pp. 363-371,2014.
[10] P. Ivo, E. M. Cho, P. Kotara, L. Schellhase, R. Lossy, U. Zeimer, A.
Mogilatenko, 1. WUrfl, G. Triinkle, A. Glowacki, C. Boit, "New
degradation mechanism observec for AIGaN/GaN HEMTs with sub

38