Irradiation System

Preset number of ions irradiation system Acknoledgement
ACKNOWLEDGEMENT
This work has been supported from contract HPRN-CT-2000-00047,

European Network on Ion Track Technology and from contract CNCSIS
586/2005 Sistem automat de iradiere a filmelor polimerice su br prestabilit
de ioni.
Preset number of ions irradiation system Contents
Contents
Preface
1. General description 1
2. Operating 2
1.1. Adjusting the preamplifier gain 4
1.2. Irradiation process 6
3. Ion detector 7
4. Preamplifier 8
5. Pulse shaper 9
6. Negative pulse suppressor 22
7. Analog to digital converter 11
8. Digital processor FPGA 12
9.1. 8 bit Computer interface 13
9.2. Clock divider 15
9.3. Instruction decoder 16
9.4. Registers 20
9.5. Irradiation machine 23
9.6. Peak detector 25
9.7. FIFO memory and interface 28
9.8. Acquire state machine 30
9.9. Printer state machine 31
9.10. Encoder reader 31

9.11. PWM generators 33
9.12. Motor control block 34
9.13. Ion flux measurement 36
9.14. Driving flipping magnets 38
9.15. Digital circuit schematic 39
9. Communication interface 41
9.16. Data acquisition board 42
9.17. Communication protocol 43
10. Power circuits 43
10.1. Motors drivers 44
10.2. Printer head drivers 45
10.3. Driving TV cameras 46
10.4. Interfacing the beam shutter 47
11. LabView program 48
11.1. Main control program 48
11.2. Beam diagnostic VI 50
11.3. Acquire VI 50
11.4. Irradiation VI 52
12. Mechanics 54
12.1. Beam diagnostics 55

12.2. Tape roller 56
Appendix 1 66
Appendix 2 79
Appendix 3 84
Appendix 4 102
Appendix 5 119
Appendix 6 120
Bibliography
Acknowledgement
Preset number of ions irradiation system
PRESET NUMBER OF IONS IRRADIATION SYSTEM
1. General description
The system is aimed to irradiate long polymer films (polycarbonate,
polyimmide, PET, etc), 35mm wide, with or without perforations, with
preset number of ions coming from an ion accelerator. Other goals to
be achieved by the present system are:
• to mark on the tape good and bad frames,
• to be mobile (light weight and small dimensions),
• to be easy to install and to operate,
• to perform ion counting and energy analysis,
• to enable irradiation under different angles,
• to be remote via Ethernet network.
The system has three parts: a beam diagnostic system, a tape
roller, and an electronic system.
The beam diagnostic system is aimed for trimming the beam
before the irradiation is started, down to 10÷100 ions per second, in
order to reduce the probability of double pulses at the detector level.
This part works in vacuum. It has three main parts: the Faraday cup
for measuring the beam current, the fluorescent screen to see the
beam shape and roughly estimating the flux, and the TV camera to
observe the fluorescent screen. The fluorescent screen and the
Faraday cup can be flipped in or out using to bi-stable magnets. On
the flange of the beam diagnostic system there are 4 double BNC
connectors: Fluorescent screen magnet, Faraday cup magnet, TV
camera and Faraday cup repeller. First three are signals coming from
the digital part of the electronic system and the repeller should be
connected to a picoamperemeter.
The tape roller consists of three DC motors and a printer head
mounted on a metal plate. Two motors are attached on the two tape
roles and the third one is driving a pressure rubber role. The motors
attached on the roles serve as breaks during irradiation or as traction
motors for FF or REW the tape. The third motor has an angular
encoder for measuring the tape displacement (the distance between
frames).
1
Fluorescent Faraday Ion Detector REW Motor Electronics Power Configuration

screen cup
memory
supply
Beam EPC2
line Preamplifier
Memory
Beam
diagnostic Shaping
ADC
Filter
EPF10k10LC84
Printing FPGA FIFO
head
Digital
Power processor
Angular circuits
Video encoder
camera
Pressure Driving Motor

role
Communication
interface
pA FF Motor
Tape roller DAQ card
DAQ6062
LAN
Figure 1 Detailed block diagram of the irradiation system

The hardware can be divided in three parts: the analog signal
processing part (silicon detector, amplifier and shaping filters), the
digital part (digital signal processor, microinstruction executor and
FIFO memory) and the power electronics (motors and magnets
drivers).
The electronic system is controlled by a LabView program, running
on a portable computer, via an 8 bits data bus (digital I/O of DAQ –
NI DAQ6062). See Figure 1.
2. Operating
The irradiation system is a complex machine which has to fulfill many
tasks. These should be scheduled in a proper order: beam trimming,
gain and sampling frequency adjustment and irradiation itself, in
order to obtain the expected results.
2.1. Beam trimming
The beam trimming is achieved using the beam diagnostic system. It

can be controlled by three bits in the control register (address 1h) in
the digital processor: D5 – TV camera switch, D6 – fluorescent screen
flipping magnet, D7 – Faraday cup flipping magnet. Also the ion flux
can be measured with frequency-meter available in the digital
processor. The result is available in register located at the address
2h on 8 bits. An overflow is signaled by the 8th bit in the status
2
register (address 0h). This process can be controlled with the VI

BeamDiagControl (Figure 53).
There are three possibilities to adjust the beam, or even
combination of them. The first one (using the Faraday cup) starts
with flipping-in the Faraday cup (I, II, II, IV) and measuring the
current (V, VI). See Figure 3 a. The beam must be defocused, by the
operator, until the current is under a certain limit (between 1pA and
10pA for Xe 27+ beam). Also, this can be completed with the
fluorescent screen together with the TV camera (for experienced
operator). First the fluorescent screen must be flipped in (I, II, II, IV),
and then, using Netmeeting, to look to the image captured with the
TV camera. The operator must decrease the beam, until a pale light
spot is visible on the screen. See Figure 3 b. Another alternative,
more precise, is offered by the frequency-meter. It can be used from
the beginning or after trimming with the previous one, for fine
adjustment. First the threshold for the trigger must be set-up and the
beam line should be switched on (I). The signal coming from the
detector (II), amplified (III), shaped (IV), digitized (V), is triggered by a
digital comparator and the pulses are counted along one second,
every two seconds, by the frequency-meter (VI). The beam flux must
be reduced until the desired number of ions per second is measured.
See Figure 3 c. The number displayed will be not constant but the
dispersion should not be more than 10 to 20 %. This is the most
precise adjustment.
screen cup
memory
supply
Beam EPC2
line Preamplifier
Memory
Beam
diagnostic Shaping
ADC
Filter
EPF10k10LC84
IV
Printing FPGA FIFO
head
Digital
Power II processor
Angular circuits
Video encoder
V
camera
Pressure Driving Motor III

role
Communication BeamDiagControl.vi
interface
pA FF Motor
Tape roller DAQ card I
DAQ6062
VI LAN
a) Trimming the beam with the Faraday cup
Figure 2.a Trimming the ion beam
3

screen cup
memory
supply
Beam EPC2
line Preamplifier
Memory
Beam
diagnostic Shaping
ADC
Filter
EPF10k10LC84
Printing FPGA FIFO
head
IV
Digital
Power II processor
Angular circuits
encoder
Video
camera
Pressure Driving Motor

role
Communication BeamDiagControl.vi
V interface
pA FF Motor
Tape roller DAQ card I
DAQ6062
III
LAN
b) Trimming the beam with the fluorescent screen NetMeeting

screen cup
memory
supply
Beam EPC2
line Preamplifier
Memory
II
Beam
diagnostic Shaping
ADC Frequency
Filter
III IV V meter
Printing FIFO
head VI
Power
EPF10k10LC84
Angular circuits
encoder FPGA
Video
camera
Digital
Pressure Driving Motor processor
role
Communication I VII BeamDiagControl.vi
interface
pA FF Motor
DAQ6062
LAN
b) Trimming the beam measuring the ion flux
Figure 3.b Trimming the ion beam
2.2. Adjusting the preamplifier gain
In order to achieve this, a special block (Acquire) has been included

4
in the digital processor. It takes 256 samples of the signal, starting

when the signal exceeds the threshold value, stored in the Threshold
register, and stores them into the FIFO memory. Afterwards they can
be downloaded into computer byte by byte. For accomplishing this,
Acquire.vi has been developed. The ion beam is switched on (I) and
the gain of the preamplifier set-up (II), the signal generated by the
detector (III) is amplified (IV), shaped (V), digitized (VI), and then the
samples are stored into FIFO (VII). For collecting the bytes from
FIFO (VIII), every byte should be transferred into the digital
processor (readmemmachine) and then read via the communication
interface from register MEM (IX). The data transferred into the
computer are displayed on a graph (Acquire.vi) and saved on the
disk into a file starting with “Acq” followed by the date and the hour,
with the extension “txt”. The operation should be repeated few times
to ensure that there are no limitations due to high gain, or, if there
are, the gain should be reduced until the pulse look like in Figure 5.
The program can save also a note at the beginning of the file. The
process is described by the following picture (Figure 4).
screen cup
memory
supply
Beam EPC2
line Preamplifier
Memory
Beam III
diagnostic IV Shaping V VI
ADC Acquire
Filter
VII
Printing
head II VIII FIFO
Readmem
machine
Power
Angular circuits EPF10k10LC84
encoder
Video FPGA
camera
Digital
role
Communication I IX Acquire.vi
interface
pA FF Motor
DAQ6062
LAN
Figure 4 Acquiring pulses for gain adjustment
NOTE: the gain adjustment should be performed with the same tape
that will be irradiated in front of the detector in order to get proper
results.
5
Figure 5 Pulse
2.3. Irradiation process
After the calibration is done, one can start the irradiation process. For
this Main.vi is available. The gain value, determined in the previous
step, must be used. According to the pulse shape, and noise
recorded, the thresholds for good pulse must be chosen too. The
virtual instrument is performing the irradiation automatically, saving
the peaks recorded in the log file (Irr + date and hour.txt) together
with some explaining note. The instrument is described in chapter 0.
The irradiation process is thought as a sequential one, different tasks
to be accomplished successively: switching-on the ion beam (I, II),
waiting for receiving the desired number of ions (III, IV, V, VI, VII),
reading the number of peaks and the peaks values (IX, X), deciding if
screen cup
memory
supply
Beam EPC2
line Preamplifier
Memory
Beam III
diagnostic IV Shaping V VI
ADC Peak det
Filter
VII
Printing
head IX FIFO
XIII
Readmem
machine
XVI Power XII
Angular circuits EPF10k10LC84
encoder XV
Video FPGA
camera
Digital
VIII II
role
Communication X Acquire.vi
I
Beam interface
Control
pA FF Motor
Tape roller DAQ card XI, XIV
DAQ6062
LAN
Figure 6 Irradiation process

6
the irradiation is good, saving data to file, printing on tape (XI, XII,
XIII), advancing the tape for next frame (XIV, XV, XVI). After the
desired number of samples is recorded, the beam is switched off
automatically (VII). This process is presented in Figure 6.
3. Ion detector
The ion detector is a PIN diode (S1223). It is dedicated for
optical measurements. In order to be used for ion detection, the
quartz window has been removed.
100nF 100pF
10µF
1M 100K -5V
Det-
Det+
1M 100K +5V
10µF
100nF 100pF
Figure 8 PIN diode capacitance versus
Figure 7 Biasing the PIN the reverse voltage
diode
Warning: removing the window will expose the diode to air.

There is a very thin wire connecting the anode of the diode to the
external pin. When manipulating, try not to touch the active area or
the gold bonding wire.
At zero voltage the maximum capacitance of the diode is
about 100pF (Figure 8), which will give a slow response (long tail of
the pulse) and a low sensitivity. In order to reach the maximum
performance, the diode should be reverse polarized (up to 20V)
through 1Mohm resistor. The reverse voltage will reduce the stray
capacitance: the result is increasing the sensitivity (U=Q/C and for
constant Q and smaller C the peak will be higher) and reducing the
pulse tail (t=RinCdet – faster discharge). The schematic is presented
in Figure 7. The DC voltage, at the detector level, must be very
7
smooth and without noise, otherwise these will add to the useful
signal.
4. Preamplifier
The preamplifier consists of two stages. The first one is an

instrumentation amplifier (Figure 9), capacitively coupled with the
detector. This is programmable gain stage with the gains 2, 4, 8, 16.
Its role is to reject the common mode signals and to provide the fine
adjustment of the overall gain. OP27 was used, because it is fast,
has low noise and low offset. The gain can be calculated with the
following equation:
3 k
R4 + ∑ 2 ⋅ Rk − ∑ 2 ⋅ Rk
Gk = 1 + 2 ⋅ i =0
k
i =3
∑2⋅ R
i =3
k
(1)
Choosing R4=10k we obtain for the other resistors the
following values: R0 = 5k, R1=2.5K, R2=1.25K, R3=2.5K. For R0 will
be used 4.7K in series with 300, for R1 and R3 2.2K plus 300 will be
used and for R2 1.1K plus 150. The feedback resistors have a 3p
1n
Det- Op27 15p

1M
R4 10k 20k
-5V +5V R0 5k 20k

15p
R1 2k5
VEE VDD
X0
Xcom X1 R2 1k25
G0 A X2 Out
G1 B X3 Op27
R3 2k5
4052 Y3 To
Ycom
Y2 shaper
Y1 R2 1k25
Y0
VSS INH
R1 2k5
15p
R0 5k 20k 20k
R4 10k
1M
Det+ Op27
1n
Figure 9 The first stage of the detector preamplifier

8
capacitance in parallel for compensating the frequency response and

avoiding the oscillation of the amplifier. The 1M resistances on each
input allow biasing the positive inputs of the opamp.
The second stage is a simple inverter stage, also with
programmable gain in two steps 1 and 16. Its schematic is presented
in Figure 10. The total gain was divided in two stages to keep a high
bandwidth for the preamplifier.
-5V +5V 15p 15p
VEE VDD
X0
In Xcom X1 16k 16k
G3 A X2
B X3 1k
4052 Y3
Y2
Ycom Out
Y1
Y0
47p OP27
VSS INH
Figure 10 The second stage of the preamplifier
5. Pulse shaper
In order to avoid multiple pulses, rising on the previous tail, the
pulse tail must be shortened. This is usually achieved using a pulse
shaper. The pulse shaper consists of two cascaded filters: a high
pass filter followed by a low pass filter. Both are MFB 2 pole Bessel
filters, in inverting configuration. Because the high pass filter will
strongly reduce the amplitude of the pulses, and to distribute the
necessary gain on both stages, the high pass has been used before
the low pass filter.
The high pass filter is F1 in Figure 11 and the low pass filter is
F2 in Figure 11.
9
15p
4.7k
6.8p
320k
22p 22p
InF2 22p
InF1 OP27
OutF1 4.7k 12k OP27
120k OutF2
33p
F1 F2
Figure 11 Shaping filter: F1 - High pass filter, F2 - Low pass filter
The high pass filter has the cutting frequency at 50KHz and the gain
of about 1.5. The low pass filter has the cutting frequency at 1MHz
and the gain of about 1. After filtering the pulses, length decreases
from about 150µs down to 3.5µs, the amplitude remaining almost
constant. The measured 3dB bandwidth of the whole shaper is from
42KHz to 310KHz with a maximum around 87KHz. The maximum
measured gain using sine wave is about 2.64 and using pulses from
the fission source (similar to ion pulses) the gain is around 2.
6. Negative pulse suppressor

Because signal shaping with high pass filter produces an undergoing
of the signal under the zero axis after the pulse, and because the A/D
converter has the input range from 0 to 2.5V a negative pulse
suppressor must be introduced on the signal path. It is shown in
10k
3p
From
shaper BAT85
BAT85 Out
In 10k OP37
To
ADC
Figure 12 The negative pulse suppressor

10
Figure 12.
The circuit is a fast half wave precision rectifier. The diodes are fast
Schottky diodes in order to have an accurate response. The
compensation capacitor can miss from the circuit. This circuit will
give negative output voltages for positive inputs. This has to be
considered in the following stage (see Figure 13).
7. Analog to digital converter

This stage performs the fast conversion (10Ms/s) of the shaped and
rectified signal into digital data, in order to be processed by the DSP.
The circuit consists of a level shifter, a voltage reference and the
ADC itself. The entire block is presented in Figure 13.
VC ADCClk
VC VC
13 12
10 DGND 100nF DVDD CLK 100nF
14 11 DGND
VC AVDD DVDD
15 10
AVDD D7
1 8 10 16 9
2 NC SEL 7 100nF VRTS D6
3 +Vin NC 6 2.5V 17 8
4 TEMP Vout 5 VRT D5
GND TRIM 18 7
1uF 100nF AD780 AVDD D4
To digital processor
100nF 19 6
100uF 100nF VIN D3
+5Vaf 100nF 20 5
-5Vaf +5Vaf AVSS D2
1k
21 4
AVSS D1
510 22 3
10k 10k VRBS D0
7 1
100nF 23 2
3 VRB DVSS
+
6 24 1
2 DVSS NOE
-
AD817 51
1k
From suppressor DGND AD775 DGND
4 8 10pF
-5Vaf
1k
3pF
Figure 13 The analog to digital converter
The level adapter is built around AD817, which is a fast

settling time, low offset operational amplifier, suitable for acting as a
buffer in front of a fast ADC. It acts as an inverter with unity gain. The
potentiometer in the noninverting input allows adjusting the DC level
of the signal at the ADC input for compensating its offset.
The AD775 is a CMOS, low power, 8-bit, 20 MSPS sampling analog-
to-digital converter (ADC). The AD775 features a built-in sampling
function and on-chip reference bias resistors to pro-vide a complete
8-bit ADC solution. The AD775 utilizes a pipelined/ping pong two-
step flash architecture to provide high sampling rates (up to 35 MHz)
11
while maintaining very low power consumption (60 mW). In order to

ensure the whole accuracy, an external reference voltage must be
used. We choose AD780 which deliver 2.5V at more than sufficient
precision for 8 bits of resolution.
Analog ground
LM7805
AD775
Digital ground
Figure 14 Layout for ADC

Regarding the layout (Figure 14), very important is the way to route
the ground. It is obligatory to have a ground plane and a digital
ground plane. Both must rest under the package and must meet
each other at the power supply. The power supply must be separated
from the analog power supply and from the digital power supply. For
the analog and the digital power supply of the ADC, the same source
can be used, but separated with a simple RC filter. The decoupling
capacitors must be placed as close as possible to the supply pins.
8. Digital processor FPGA

The digital processor is located in a FPGA (Flex10k10) from Altera.
The processor must perform the following jobs:
• to enable communication with computer or another
processor via bi-directional interface
• to allow the control of different parameters and output
signals: preamplifier gain (3 bits), sampling frequency (1
bit), accelerator line, TV camera switch signal, Faraday cup
switch signal and Fluorescent screen switch signal.
• to process the signal coming from the detector and to
provide a peak detection and counting
• to switch on the ion beam at the beginning of the irradiation
process, to switch it off after counting the preset number of
ions and to continue performing the signal analysis for an
extra time necessary for the accelerator to switch off the ion
12
beam (around 250us)

• to allow the acquisition of the signal for gain adjustment
• to drive the motors of the tape roller
• to drive the printer head
The processor has been developed in MaxPlusII, at graphic level,
all the schematics being available in Appendix 2 and along this
chapter.
This is a combination between a simple microprocessor (registers
and instruction decoder), a hardware digital signal processor (peak
detector) and some dedicated logic blocks (printing, tape advance,
acquire). It was developed to fulfill the specifications above with
minimum resources.
8.1. 8 bit Computer interface
The interface with a host computer or other processor is a bi-

directional one, the data flow being managed by a Strobe signal
DFF
DIO0 PRN Q0
D Q
INPUT OUTPUT
7 DIO[7..0] VCC 3 Q[7..0]
CLRN
11
DFF
DIO1 PRN Q1
D Q
CLRN
12
DFF
NOT AND2 DIO2 PRN Q2
D Q
INPUT
5 nStrobe VCC
INPUT 8
10 nInhibit VCC 9
CLRN
13
INPUT
19 nRST VCC
DFF
DIO3 D
PRN
Q
Q3
CLRN
14
DFF
DIO4 PRN Q4
D Q
CLRN
15
DFF
DIO5 PRN Q5
D Q
CLRN
16
DFF
DIO6 PRN Q6
D Q
CLRN
17
DFF
DIO7 D
PRN
Q
Q7
CLRN
18
Figure 15 The schematic of the Receiver block

13
generated by the host (computer or other processor). The data bus is

8 bits wide.
The interface consists of two blocks: the data receiver (Figure
15) and the debouncer (Figure 17). The data receiver is an 8 bits
register which temporarily store the received instruction code. The
signals available are nStrobe, nInhibit and nRst, all of them being
active on low level as it is suggested by the “n” in front of their
names. nStrobe acts as a clock for the D type flip-flops in the
register, on its falling edge, the data present on the 8 data lines
(D0÷7), being stored in, and becoming available at the 8 outputs
(Q0÷7).
The nInhibit inhibits the clock when the host is sending the
second byte of the instruction (for instruction with two bytes). After
the code of an instruction with two bytes is detected, the Instruction
Decoder make active this signal until the second rising edge of the
nStrobe. The waveforms in Figure 16 illustrate the functioning of this
circuit.
Figure 16 The associated waveforms for the block Receiver

The block debouncer avoids false strobe edges (debouncer). If
the nStrobe signal generated by the host has not monotonous edges,
the processor would interpret these, as many strobe edges and the
communication would be erroneous. This block, sample three times
the external nStrobe signal, on three consecutives clock cycles and
only if all values are low, it drives the dataout to low or only if all are
high dataout will be high, otherwise the Dataout is staying
unchanged. This is realized with a shift register, working on the
internal 10MHz clock, and shifting the values of data sampled on the
three clocks. The coincidence of these 3 values is detected with a 2
gates NAND 35 and OR 34 which drive a DFF 24. When the circuit is
initialized after the power up, all flip-flops are forced in the high logic
level. The debouncer is shown in Figure 17 and associated
14
Figure 17 The debouncer

waveforms in Figure 18.
Figure 18 Waveforms for debouncer
8.2. Clock divider
The programmable logic device is supplied with a 20MHz clock from

an external oscillator. This clock is divided by two using a D type flip-
flop to 10MHz, in order to ensure a ½ duty cycle. Also this is the
clock signal for the ADC. This signal is the main clock in the digital
processor. In order to obtain all the internal necessary clock
frequencies a 20 bit binary counter is used (clkdiv block in Figure 19).
This block is designed using the Mega Wizard Plug-in Manager, but it
can be realized very easy cascading dividers by two, like the first
Figure 19 The clock divider

15
one. Every CLKDIV[k], k=0,1…17 will be a square wave with ½ filling

factor with the frequency:
10 MHz
f CLKDIV [k ] = (2)
2k
8.3. Instruction decoder
The instructions the device accepts consist of one or two

bytes. The one-byte instructions are commands (like Print, Irradiate,
Go next frame, etc) and the two bytes instructions are for reading
and writing to registers. The first byte contains on four bits the
instruction code and, on other four, the register number, and the
second byte is the value to be written or read from the register. Thus,
the instruction decoder must decode the first byte, and decide if it is a
command or a read-write instruction. First this instruction is fed into
two binary to decimal decoders (4to16dec in Figure 20). One decode
the higher significant byte of the instruction (D[7÷4]) and establish
which instruction it is, and the other decodes the lower nibble
(D[3÷0]) and establish which register is addressed. The outputs of
the second decoder are taken into account only if the instruction
code was 1 or 2 (logic 0 on eq0 or eq1 outputs of the 4to16dec
number 3). In these cases, the nrd and nwr signals are used to
enable the storage of the low nibble (D[3÷0]) in the second decoder
(4to16dec number 4) for register addressing. If the instruction code
was different from 1 or 2, than it means that a command has been
received, and the second decoder is disabled (logic 0 at all outputs)
and no registers are selected.
This block is also generating some other necessary signals for
other blocks. Using a Johnson counter (jonson 19) and two AND
(AND 20 and 21) gates, a short pulse, delayed by seven clock cycles
from negative edge of the internal nStrobe signal, is generated (on
the output Q3). It is used as a clock for two flip-flops (DFF 14 and 15)
for generating the signals for inhibiting the receiver (nInhibitR and
nInhibitT) during the second byte receiving or transmitting and
isolating the instruction decoder from the data lines. Also, the output
Q2 of the Johnson counter (see Appendix 2) delivers a short pulse (1
clock length), for storing the decoded instruction in the latches
(latch15b 1 and 2). The inhibition state finishes on the first positive
clock edge after the second nStrobe positive edge. This means that
the stopstate signal becomes for short time active and brings the two
16
flip-flops to logic 1. This happens only when nrd or nwr are active,
that is to say when it is a write or read instruction. Also two delayed
replicas of the nrd and nwr (nrd1 and nwr1) signals are generated
here for having the proper timing for the registers reading or writing.
One of these signals is generated and remains active just for the
duration of the second low state of the internal nStrobe of any
read/write instruction, when data is transferred into or from register.
Figure 20 The instruction decoder schematic

17
Figure 22 shows the timing for all three types of instructions:

write to register, read from register and command. The first window
shows a write operation in the control register. The code of this
instruction is 11H: first “1” means write, and second “1” is the
address of the control register. The data lines available in the chart
are the lines coming from the receiver block, and the data to be
written in the register is not possible to be seen.
The nInhibitR signal becomes active seven clocks after the
first negative edge of the internal nStrobe and keeps the state until
the second positive edge of the same nStrobe. The nWR1 is active
just for the second internal nStrobe pulse, when the data is stored in
the register. Its negative edge, together with the register selection
signal (one of the outputs from the latch15b number 2), generates
the clock for the one of the writable registers. This will be explained
in the next sub-chapter.
The second window in Figure 22 shows the waveforms for a read
instruction. This is similar with the writing, just the active internal
signal are different: nInhibitT and nRD (nRD1). The instruction code
is 20H. 2 means read instruction, and 0 is the address of the Status
register. For the second byte of this instruction, the host has to
release the data lines, and the digital processor will put the data in
the accessed register on the lines. The data will be available on the
data lines only during the second internal nStrobe low pulse.
Write instruction timing (in control register)
Figure 21.a. Instruction decoder timing: write instruction
18
The third window in Figure 22 shows the waveforms for a
Read instruction timing (from status register)
Command instruction (Irradiate)
Figure 22.b Instruction decoder timing: read and command

instruction
command instruction. The instruction code is 30H. It is a one-byte
instruction. This instruction starts the irradiation process (opens the
ion beam, records and process the signal from the ion detector,
counts the number of ions and shuts off the ion beam when the
preset number of ions is achieved). Internally, after receiving this
code, the processor activates, for the internal nStrobe low pulse
duration, the nIR signal. This is a low level active signal, and the
irradiation state machine will be activated.
This was the description of how the three basic instruction
works. For a write or read operation the difference will be just the
register selection signal which will be different, and for commands
the internal active signal will be changed. The listing of instructions is
19
presented in Appendix 1.
8.4. Registers
The registers bank consists of 7 writable registers (located inside this

block) and 7 readable registers (spread in other blocks). This block is
presented in Figure 23.
The writable registers are 8 bits wide and they can be loaded with
data (Load) and cleared (nrst). The seven writable registers are:
• the control register (CR), internal address 1h, internal
selection signal C. The bit significance:
D0=gain control bit 0 (G0); D1=gain control bit1 (G1); D2=
gain control bit 2 (G2);
D0/G2 D1/G1 D2/G0 Amplifier gain
0 0 0 2
0 0 1 4
0 1 0 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256
D3= ADC sampling frequency control bit: for D3=0 the

sampling frequency is 10MHz and for D3=1 it is 5MHz
D4= accelerator line control: D4=0 the ion beam is OFF and
for D4=1 the ion beam is ON
D5=TV camera switch: D5=0 tape surveillance camera, D5=1
fluorescent screen observer camera
D6= fluorescent screen switch: D6=1↓0 – screen out, D6=0↑1
– screen in
D7= Faraday cup switch: D7=1↓0 – cup out, D7=0↑1 – cup in
• the threshold register (TR), internal address 4h, internal
selection signal TH. It stores the threshold value for the
peak detector.
• the FF motor register (MFFR), internal address 5h, internal
selection signal GFL. Sets the speed of the FF and REW
motor. This value goes to one PWM generator that drives
the h-bridges for both motors attached to the roles. They
act like brakes. The value to be sent is 120
20
• the Preset number of ions registers (PNLR and PNHR).

This two form a 16 bits register, their content being
compared with the ion counter in order to detect the end of
the irradiation. PNLR has the internal address Bh and
PNHR has the internal address Ch, and the internal
selection signals PNIL and PNIH.
• the Print register (PRNR), internal address 8h, internal
selection signal PRN. The bits of this register directly drive
the needle of the printer head. The Print state machine
apply the printing command word just for few hundreds
milliseconds.
• the Pressure role motor register (MPRR), internal address
7h, internal selection signal GFI. Sets the speed of the tape
driving motor. This value goes to motor controller (motors)
Figure 23 The registers block

21
which apply a constant number of pulses (8192) to the

motor through the h-bridge.
The readable registers are located in other blocks, here being
located just the multiplexer that selects their outputs to the data
lines. These registers are:
• Frame counter register 1 (FCLR) – internal address 9h,
internal selection signal FCL
• Frame counter register 2 (FCHR) – internal address Ah,
internal selection signal FCH. FCLR and FCHR are located
in the Encread block (see Figure 31).
• Peak data register (MEM) – internal address Fh, internal
selection signal PK. MEM register is located in the
Readmemmachine block (see 8.7)
• Number of peaks register 1 (NPLR) – internal address Dh,
internal selection signal NPL.
• Number of peaks register 2 (NPHR) – internal address Eh,
internal selection signal NPH. NPL and NPH registers are
located in the Peakdetector block (see 0).
• Input register (INR) – internal address 2h, internal selection
signal IN (not implemented; used for ion fluence
measurements). Bits 3 to 0 of this register come from the
freq block (see 8.13)
• State register (SR) – internal address 0h, internal selection
signal S. The bit values are updated by different signals in
the circuit (State[x], x=0,1…7):
Bit 0=State[0] bit signals that the irradiation process is in progress
(logic 1) or is ready (logic 0)
Bit 1= State[1] bit signals beam line state: logic 1 means beam on
and logic 0 is beam off. This bit is the ACC output which drives the
deflection Faraday Cup.
Bit 2= State[2] bit is the full flag signal of the external FIFO
memory.
Bit 3= State[3] bit is the empty flag signal of the external FIFO
memory.
Bit 4= State[4] bit signals the acquire process (logic 1 means the
data from the ADC is storing in the FIFO memory).
Bit 5= State[5] bit signals that the digital processor is printing on
the film (logic 1).
Bit 6= State[6] bit signals that the tape is advanced to a new frame
(logic 1).
22
Bit 7= State[7] bit signals the overflow of the ion flux measurement
(logic1).
8.5. Irradiation machine
The irradiation machine is located in irradmachine block. Its role is to

control the irradiation process. The schematic of the irradiation
machine is shown in Figure 24.
Figure 24 The irradiation machine

The negative edge of the nIR signal will initiate the irradmachine. The
flip-flops DFF 35 and DFF 36 will set to logic 1: DFF 35 output is the
busy signal which is wired to STATE[0] bit. The output of DFF 36
initiates the clearing of the ion counter in the peakdetector block
(clearioncounter signal), but the flip-flop will be reset after half system
clock period(10MHz) by the circuit realized with DFF 40, DFF 49,
AND 41, AND48, NOT 45 and NOT 50. The clearioncounter signal
will also open the ion beam. After it falls again in logic 0, the
irradiation process is started and the ion counter will count the ions
recorded by the peakdetector block. After reaching the preset
number of ions, it will return to the irradmachine the end signal. This
is a high going pulse, which is the clock signal for DFF 17. Its output
enables a 12 bits counter (12bcount 31), which will count 212 system
clocks until it will activate the carryout signal (cout). In order to detect
extra particles that can come in this period (until the beam will be
23
switched off), the peakdetector must be maintained enabled a larger

time, and if some particles are recorded, than the frame is marked as
“bad”. The ion beam switching-off time is around 250 µs (response
time of the Faraday cup). The total counting time of the 12bcount is
212⋅100ns=409.6µs. This is period is located after the ion beam
command is activated. The counter’s carryout signal is than passed
through DFF 30 and DFF51, in order to avoid the hazard of cout
combinational logic, to generate the ready signal. Its activation
means the end of the irradiation process. It will reset DFF 35, DFF 17
and the 12bcount, leaving the irradmachine block in the same state
as it was at the beginning. The whole circuit is initialized at the power
up, or with an external reset signal via nReset. The following picture
(Figure 25) presents the waveforms of this circuit.
The irradiation process timing
Figure 25.a. Waveforms for irradmachine
Detail at the beging

Figure 26.b. Waveforms for irradmachine
24
Detail at the end
Figure 27.c. Waveforms for irradmachine
8.6. Peak detector
The peak detector is one of the most important parts of this

processor. It makes the digital signal processing of signal coming
from the detector, and counts the ions, which hit the detector. It
works in tandem with the irradiation machine. This is a simple version
of the peak detector, but with good results. The algorithm is the
following: the noise background is extracted from the data, each
sample is than compared with a threshold and as long as they are
above the threshold the maximum is searched by storing the biggest
sample found. When the values of the samples fall under the
threshold, the peak value is available. The threshold is setup
according to the signal recorded in the calibration step.
The block diagram of the peak detector is presented in Figure
28.
Read
0
0 RD Dout
MUX F M FIFO
1
C WR
A>B A>B
A A
R
Peak
ADCdata COMP COMP
S
B B A<B
Threshold
Clk N No of peaks
Figure 28. Peak detector - derivative algorithm

25
The algorithm is using the first derivative as peak detection method.

The derivative of the signal is changing the sign when the signal
passes through a maximum or a minimum. Considering only the
derivative change from positive to negative, only the peaks can be
detected. It is not necessary to compute the derivate values in every
point
dxk xk − xk −1
=
dt Ts
(3)
where xk are the signal samples and Ts is the sampling period,
because not the value is important, but the sign. This simplifies the
implementation, because checking the sign is simply performed with
a digital comparator.
After separating the pulse from the rest of the signal (MUX),
the data stream is filtered with a digital low pass filter (F), in order to
smooth the signal. This is brings the benefit of integration and it is
really necessary because the derivative will detect every local peak
in the signal. Then the derivative sign is checked (M and COMP). It is
enough to compare consecutive samples in order to determine the
sign of the derivative. Comparing with the previous algorithms, this
one ends with the first sample after the peak (the response time is
the pulse rise time).
The schematic diagram of the peak detector is presented in
Figure 29. The acquired data is feed at 10MHz into this block through
ADCdata[7..0] and it is compared with static data Thresold[7..0] from
the TR register by the numerical comparator comp 126. Its output is
used to separate data above the threshold (separate the pulse data
from the rest of the signal). This is accomplished by the multiplexer
mux8x2to1, which replaces the data under the threshold value with
zero. In order to avoid false peaks generated by noises, data should
be filtered first before processing. This is accomplished with two
cascaded low pass recursive stages:
x + yk −1
yk = x (4)
2
Each stage contains an 8 bit sum block (171 and 172) and memory
register for delay (144 and 161), which compute the equation 4, and
the division by two is just a shift to right with one bit (consider only
the most 8 significant bits). The register 5 creates a delayed sample
(xk-1) at Dout7…0. The comparator 128 checks the sign of the
derivative. Because the pulse can have sometime many consecutive
26
samples with the same value, both a>b and a<b should be
considered in order to get the derivative sign change. Because of
hazard, they have to be synchronized with the clock (DFF 133 and
134). DFF 137 will be set when the derivative sign is becoming
negative. Its output is the clock for the ioncounter 54, and also the
positive edge will store the peak value in the external FIFO memory.
The digital comparator 142 will signal when the number of ions
recorded is equal with the preset one (setionno[9...0]).
Figure 29 The peakdetector block
The waveforms associated with the peakdetector are in Figure

30. ADC data stream contains a pulse with two local peaks due to
the noise added by the electronics. After filtering, the new data
stream is smooth, presenting just a single peak. Immediately after
the signal start to decrease (the slope become negative, the
derivative show the peak position), it means that the signal reached
the maximum value. The peakdetector signals this vent activating the
signal “peak”. The positive edge of this signal stores the maximum
value into the FIFO memory. For an appropriate PCB design, proper
grounding and using a low noise amplifier, the signal is free of noise
and the signal comes smooth even before the filter F.
27
2 local peaks single peak 1 peak detected

after filtering
Figure 30 Waveforms associated with peakdetector
8.7. FIFO memory and interface
Due to the wide area that an internal FIFO memory will occupy, the
use of an external memory has been considered. It is a Cypress 32k
dual access FIFO. Interfacing this memory asks for 21 pins: 8 data
in, 8 data out, 2 for read and write, 1 for reset and 2 for signaling
flags. Internally, they are many blocks which read or write from/into
this memory: the peakdetector, the readmemmachine and the
acquire blocks. This sub-chapter will describe just the
readmemmachine and some other parts that are not included in any
28
block. The schematic of the readmemmachine is presented in Figure

31.
Figure 31 The readmemmachine block

According to the CY7C464 data sheet the data become available at
the data outputs at maximum 40ns from the negative edge of the
read signal and last 3 ns after the positive edge. In order to read the
data from memory, the readmemmachine uses a register to store the
data and a sequential circuit for generating the read low pulse and
the high load pulse inside it. A Johnson counter (jonson1 4) starts to
count the system clocks when nM is activated. Its Q0 output sets a
flip-flop (DFF 19) who’s output is MemRd signal. The output Q1 is
used to load the data, available on MEMDATIN[7..0] inputs, into the
register (reg 1), The output Q3 will reset later the whole sequential
circuit. After a “read from memory” instruction the data should be
transferred to computer. A new instruction will just overwrite the old
Figure 32 Waveforms associated to the readmemmachine
29
data. The waveforms showing the functioning of this block are

presented in Figure 32.
8.8. Acquire state machine
In order to adjust the proper gain for the analog chain, the signal that
is acquired by the ADC must be visualized. The acquire block reads
data coming from ADC and stores it into the FIFO memory. The start
moment of the acquiring process is triggered with a numerical
comparator. This block can be seen in Figure 33.
Figure 33 The acquire block
The comp 1 block compare the data coming from ADC

(ADCData[7..0]) with the threshold value (Thresold[7..0]) and starts
the acquiring process. The output ageb is masked by the busy signal.
This is active (logic 1) after the processor has received the instruction
C0h (acquire data to memory). The comp output ageb and busy,
drive the set (PRN) input of a flip-flop (DFF 4). As soon as nAcq has
been activated and the ADC data is exceeding the threshold value,
this flip-flop is set to 1 and the logic gate AND2 8 will leave the clock
(which is also the ADC clock) to increment the 32kcounter 9. Always,
the acquire stores 32k samples in the FIFO memory. The user can
read how many he wants (usually 128 are more than enough for
seeing a pulse). Transferring the data from chip to computer is quite
slow; it may take few minutes for 32678 samples. Coming back to the
counter, its clock is also the signal MemWr, and on the positive edge
the data is stored into memory. After completing the acquire
30
Figure 34 The print machine

(32counter full), its carry-out signal stops this process and reset the
entire machine (DFF 18, DFF 4 and 32counter 9). The signal busy is
mapped into the state register (STATE[4]).
8.9. Printer state machine
This block has been designed to generate signals for the printer
drivers according to the information contained in the PRNR. The
schematic is in Figure 34. The block is organized around a 3 bits shift
register (DFF 8, 9, 10). It is initially loaded with “100”, and at the end
of printing process is loaded again with the same state. When the
instruction decoder receives the printing instruction (90h), it activates
the nPRN signal (logic 0). The flip-flop DFF 4 will be set-up at the
falling edge of this signal, activating the busy signal and starting the
printing process. Printing means activating the needles once. This
happens when the shift register is in the state “010”. The clock
frequency of the register is around 4.76Hz. This means the printing
pulse is 210 ms long. The outputs of the print register (PRNR) are
chopped by the outputs 2 of the pulse register through 7 AND gates
(16 to 21 and 23). When DFF 10 receives the logic 1 (state “001”) the
block is returning again in the initial state (shift register and DFF 4
are reset).
8.10. Encoder reader
This block is named encread in the project and reads the data from
31
the angular encoder of the pressure role driving motor and

transforms it into frames count. The inputs are two quadrature square
waves ChanelA and ChanelB in Figure 35. They are generated by
the angular encoder attached to the pressure role motor, and they
are processed by debouncer blocks before.
Figure 35 The encread block
The main parts are the two 10bits up-down counters: the pulse
counter and the frame counter (counters 25 and 42). They are used
in the present design just as a indicator for the frame length.
Because the number of pulses given by the encoder is 2520 per
rotation, and the circumference of the driving role is 63 mm, the
number of pulses per frame is about 800 for about 20 mm. This
means that the role will turn one third of turn for advancing the tape
to a new frame. The counter carry output cout is the clock signal for
the next counter. The signals q[8] and q[9] were used to generate a
signal (slow) used by other block (Motors) to decide the speed of the
tape. First the tape was pulled with low speed (according to the value
in MPRLR) then it runs with high speed (according to the value in
MPRR), and in the end again with the low speed. This regime was
chosen in order to avoid the pressure role slipping on the film, and to
prevent long stopping time. Actual design does not use this, slow
being unused. The block Motors applies a constant number of pulses
to the PR motor.
In order to choose the right count direction the DFF 3 has
been used. ChanelA is the clock signal and ChanelB is the data
input. If the motor is turning forward, ChanelB has an advance of one
quarter of period from ChanelA, and the rising edge of the ChanelA
32
will find ChanelB in logic 1 and DFF 3 will go to logic 1. The pulse
counter and the frame counter will count forward. If the motor is
turning backward that ChanelB is delayed with a quarter of period,
and the flip-flop will go to logic 0, determining the counters to count
backwards. The counters can be initialized (reset) with external reset
signal or when resetting the registers (instruction A0h). This feature
is used only for monitoring the frame length.
8.11. PWM generators
In order to drive motors with variable power and speed, it is

universally accepted that the most efficient way is to use H-bridge
and PWM (pulse-width-modulation) signals. What is an H-bridge?
This is a bridge that has on its arms transistors, complementary on
the opposite arms. One diagonal is connected to the power supply
and on the other the load must be connected. More details can be
find in § 10. What is pulse width modulation? It is a square wave
signal for which the ratio between the logic 1 period and the 0 logic
period can be varied from 0 to 100%. The transistors act as switches
applying to the load the power supply with different polarity and for
variable repetitive time. The load (motor) acts as a filter and the
PWM signal is filtered and only the DC component will be extracted.
The idea to realize such generator in digital is coming from
analog: a triangular wave generator and a comparator with variable
threshold. The same way can be followed for digital implementation.
The triangular generator is an up-down counter and the comparator
is replaced with a numerical comparator. The counter’s output is
compared with a constant value or with a quasi-constant one
Figure 36 The PWM generator schematic
33
(compared with the PWM frequency), and at the output of the

comparator the PWM signal is available. This is the general idea that
is used for the PWM in Figure 36.
The up-down counter 8bcount 1 is the “triangle wave
generator”. It is an 8 bits counter. It is incremented or decremented
with a clock of 312.5 KHz (clkdiv4) this meaning that the PWM
frequency is about 312.5 KHz / 512=610Hz. Unfortunately this is an
audio frequency but the sound generated by the motors is anyhow
covered by the other sounds in the irradiation room. It counts up 256
clocks until the carry-out signal signals that the counter is full. DFF 9
is avoiding the false signals due to the combinational logic that
generates the carry signal, by sampling it on the falling edge of the
clock. Using another flip-flop (DFF 2), the counting direction is
changed based on this carry signal. Thus the counter output is
linearly grows from 0 to its maximum and then linearly decrease
again to 0. Its outputs are compared with a constant threshold value,
val[7..0]), that is preset through registers (MFFR, MRR, MPRHR,
MPRLR). As long as the counter’s output is smaller than the
threshold, the PWM signal is logic 0, and it switch to logic 1 when it
becomes greater than the threshold. The greater-than output (agb)
sampled on the falling edge of the clock is the PWM output. It is
available with both polarities because two transistors have to be
driven with one polarity and the others with the opposite polarity due
to their complementarity. Some simulation waveforms can be seen in
Figure 37.
Figure 37 PWM waveforms
8.12. Motor control block
This block is dedicated for driving the pressure-role motor. In order to

obtain stepped PWM driving (low-high-low) the threshold value at the
input of the PWM generator must be changed at precise times. This
34
Figure 39 Pressure role motor’s control block
block’s schematic is presented in Figure 39.

When the device receives the instruction 80h, the signal nSF is
activated (see the top level design in Appendix 2) which is connected
to signal go. The flip-flop DFF 2 is set and the busy signal toggle to
logic 1. It is wired to STATE[6] bit in the status register. It signals that
the tape is advanced to the next frame. It opens the gate AND 33
and the PWM signal will flow to the h-bridge. The pulsecnt 53 counts
8192 PWM pulses until the cout output will reset the counter and
Figure 38 Simulation waveforms from the block motors
35
DFF 2. The simulation waveforms can be studied in Figure 38. Using

15KHz PWM, the frame length will be almost constant around 22 mm
(between 20.5 and 23.5 mm).
8.13. Ion flux measurement
Flux measurement implies a frequency-meter. It must count the

number of ions hitting the detector during one second. The result is
available in 8 bits format on INR. The schematic of this block (named
freq) is available in Figure 40.
Usually a frequency-meter is based on a dividing gate (AND2 1) and
on one counter (fr8bcount 65). The pulses to be counted pass to the
counter as long as the gate signal (DFF 68 output) is in logic 1. In our
case the gate signal is clkdiv16 divided by 76 (count75). The
following flip-flop (DFF 74) makes a division by 2: this means the
high state of this signal is almost 1.003 s, this being the counting
time. This time value has been chosen because of simplicity of
schematic (it is not necessary another dividing chain). During this
time any pulse which occurs is counted. The digitized signal is
triggered by a digital comparator (8bcomp 71), its synchronized
output being the signal carrying the information about the ion flux to
be counted. The measured value of the flux (fr8bcount 65) is just a
little bit different from the real value, but corrections can be operated
on computer or on the host processor if they are really necessary.
The counter has a carry-out output which is signaling the overflow
(STATE7 in state register). Its outputs are temporarily stored in an 8
bits memory (8bitreg 66) in order to make it available till the next
measurement ends. Assuming that the flux is constant, the indication
will be stable. In reality, due to the statistic occurrence of the ion
passing through the aperture, the value will change. The maximum
ion flux value that can be measured is 256 ions/1.003s≅256 ions/s.
DFF 42 and jonson1 53 generate two pulses for loading the result in
memory (Q0) and for resetting the counter for a new measurement
(Q1). The associated waveforms for this block are presented in
Figure 41.
36
Figure 40 The ion flux-meter schematic
One can see the counting time, 996.1472s, and pulses are
very condensed at the beginning of the interval.
There are 20 groups of two pulses each (a), this means 40 pulses
(see Freq[7..0] in Figure 37).
Figure 41 Waveforms associated to the freq block
37
a) detail
b) detail of the detail

Figure 42 Waveforms associated to the freq block (detail)
8.14. Driving flipping magnets
In order to drive the flipping magnets for Faraday cup and fluorescent
screen, pulse generators must be used (Figure 43). The signals for
driving these magnets are mapped in the control register (CR): bits
D6 and D7. As it is said before, logic one means “IN” and 0 means
“OUT”. Because the flipping magnets must be driven just with a short
pulse (small power dissipation) the edges must be detected. For the
positive edge will be a pulse acting one branch of the bridge, and for
the negative edge another pulse acting the other branch. In order to
obtain these pulses the following schematic has been used. The idea
is simple. An edge sensitive flip-flop is used to start the pulse (DFF 1
or DFF 14) on the desired edge (Signal). Its output is the pulse
output. Also, it allows the clock to reach a counter (counter 7 or 16)
through a AND gate (AND2 5 or AND2 15). The counter counts 7
38
Figure 43 The edge detection circuit
clock periods and then reset the flip-flop and itself through QD output.
The pulse length is about 7 clock periods (CLKDIV[17]). This means
the pulse duration is about 267 µs.
The waveforms are available in Figure 44. Two such detectors are
used: one for Faraday cup (bit D7) and one for the fluorescent screen
(bit D6).
Figure 44 Waveforms associated to the edge detector
8.15. Digital circuit schematic
The entire schematic of digital processor is shown in the

following figure. The only parts left unexplained are the ADC clock
multiplexer (clkmux 10) and the ACC signal mixer, but they are
supposed to be very simple.
39
Digital processor schematic
40
The pins assignment for the FPGA is shown in the Figure 45.
It was done like this in order to achieve a simple PCB.
The external digital electronics around this processor is
reduced to the FIFO memory and some gates. It also includes the
EEPROM (EPC2LC20) for configuring the FPGA at power-up, reset
circuit, connectors with other blocks, the JTAG programming
interface and a 20MHz oscillator. The connection with EPC2 memory
is the classic one for multi-device JTAG chain configuration. Some
connectors for debugging the hardware are available too. This part
can be found in Error! Reference source not found..
Figure 45 Pin assignments for FPGA
9. Communication interface
The digital processor must be driven by a host computer or by
processor. It just receives instructions and executes them or sends
data back. The interface is a parallel one, having 8 bits bidirectional
data lines and one strobe signal driven always by the host (computer
41
or processor). The digital processor acts like a slave.

The present setup uses a laptop computer as host, equipped
with a data acquisition board. For the communication interface the
available on DAQ digital port and one counter output is used. The
interface is simple and fast enough.
9.1. Data acquisition board
The data acquisition is DAQ 6062E. It is PCMCIA card, with

analog inputs and outputs (12 bits), digital I/O’s and counters. Its
characteristics are described in appendix 4. Any other board based
on DAQ-STC device can be used, without changes in the software.
The connection diagram is shown in Figure 46.
They are some extra comments to make:
• the GPCTR1OUT is connected to the reset switch contacts
(SW1 on Error! Reference source not found.)
• The digital processor and all the digital circuitry must be
supplied from the computer power supply available at the
DAQ connector. For unexplained reason (even from
specialists from Altera) the communication does not work
properly if the power supply of the digital processor is
different. In this case very often the data that digital
processor receives or sends is FFh and not the proper one.
Digital processor Host computer

(FPGA FLEX10k10LC84) (DAQ 6062E)
16 DIO0 DIO0 52
17 DIO1 DIO1 17
18 DIO2 DIO2 49
19 DIO3 DIO3 47
21 DIO4 DIO4 19
22 DIO5 DIO5 51
23 DIO6 DIO6 16
24 DIO7 DIO7 48
25 nStrobe GPCTR0OUT 2
to reset switch Reset GPCTR1OUT 40
to ground GND DGND 44
to Vcc +5V +5V 8
Figure 46 Connections for the communication interface
42
It must be possible that some latch-up phenomenon can

occur because of tri-state circuits used inside the digital
processor.
9.2. Communication protocol
The communication protocol is a simple one. It must be a

master, which are a computer or another processor and a slave,
which is the above described digital processor. The slave is always
waiting for instructions. The master puts the data on the data lines
(instruction code) and then activates for short time the nStrobe signal
(low going pulse). This pulse must not be shorter than 6 system
clocks (600ns) due to the debouncer circuit, which samples the
nStrobe for 5 consecutive clock cycles. The digital processor uses
the falling edge of the nStrobe signal to store the signal in the
receiver latch. The data must be stable on the data lines at least 4 ns
after the negative edge of the IntStrobe. For safety, the data must
remain unchanged until the nStrobe returns to logic 1. If the
instruction is a command (codes greater than 30h) then this is a
single byte instruction. It ends after the releasing of nStrobe. The
host must test afterwards the status register, to find out when the
execution of the started instruction will end, by testing the
corresponding bit. If the instruction is a read/write one, than after the
first byte a second one should be transferred. If the instruction is a
write one (codes 1Xh), then the host must put the data on the lines
(the value to be written) and activate the nStrobe signal longer than
1.15µs, time necessary for the data to be stored in the addressed
register. If the instruction is a read one, then the host must switch its
lines direction to input and afterwards activate the nStrobe. Starting
1.3us after the nStrobe falling edge the data will be available on the
data lines, and it stays there as long as the nStrobe remains low.
The instructions codes and their description can be found in
Error! Reference source not found..
10. Power circuits
The power circuits are used for driving the motors and the
printer head. Also, driving the accelerator line asks a level
adaptation. All this circuits are subject for this chapter.
43
10.1. Motors drivers
The irradiation system contains three motors. All motors are driven
using the same schematic: galvanic separated H-bridge. The
schematic is presented in Figure 47.
The driving signals are TTL level (pins 3 and 4 on J3
connector) and they are coming directly from the FPGA. The bridge
is optically coupled with the rest of circuit in order to protect the low
power electronics. Two transistors were used as buffers to drive
common type optocouplers (CNY17). The power transistors in the
bridge are Tip102 for NPN and TIP105 for PNP. These are too big for
this purpose, but they were available from an old printer. Also, less
powerful transistors can be used (BD 677 and BD678). The bridge is
supplied at 12V DC.
Applying +5V to pin 3, Q6 will open to saturation, and the
LED’s in optocouplers U3 and U1 will light. The phototransistors from
U3 and U1 will be saturated also (0.2-0.4V collector-emitter voltage).
The current flowing through these transistors will generate a voltage
drop on the resistors R1 and R3, which will open the power
transistors Q1 and Q3 to saturation. Then the load, connected at J2
will be supplied with around 10V, with plus on pin 1 and minus on
pin2. If the driving signal is pulsed one, the load is connected to the
power supply just for short time during one period of the pulsed
+5V
+12V
R1 R4
1k 1k
3 6 U1 1 1 U4 6 3
Q1 1 5 5 1 Q4
2 2
TIP105 4 4 TIP105
R5 CNY17-4 2 J2 Motor 2 CNY17-4
R8
100k 100k
1
2
J1
M+ M-
1
2
R6 6 U2 1 1 U3 6 R7 12V
100k
5 5 100k
2 2
1 4 4 1
Q2 CNY17-4 2 2 CNY17-4 Q3
3 3
TIP102 R2 R3 TIP102
1k 1k
GNDPOW
R9 R10
100 100
R11 Q5 Q6 R12
1k Q2N2222 Q2N2222 1k
4
3
2
1
J3 TTL
Figure 47 H-bridge schematic

44
signal. If the load is inductor or motor, it acts like a low pass filter,
and only the DC component will be used. Varying the filling factor of
the pulsed wave, the DC voltage can be changed. It results a nice
and simple control of the DC on the load (from zero to maximum).
The same description is available for the other branch (Q5, U2, U4,
Q2 and Q4). This time, the polarity applied to the load is minus on pin
1 and plus on pin2 (reversed as in the previous). Some simulation
waveforms are presented in Figure 48. The bottom plots show the
two driving signals at the J3 connector (V(V1:+) and V(V2:+)), and
the top one shows the voltage V(Q1:c,Q4:c), on the load (pure
resistive). In this case, the DC component is zero, but it was chosen
to demonstrate both polarities.
The same schematics are used too for driving the magnets
which switch in and out the Faraday cup and the fluorescent screen.
The driving signal is just one short pulse, on one or the other input.
How this is done is described above in paragraph 0.
10V
0V
SEL>>
-11V
V(Q1:c,Q4:c)
5.0V
2.5V
0V
V(V2:+)
5.0V
2.5V
0V
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(V1:+)
Time
Figure 48 Waveforms for H-bridge
10.2. Printer head drivers
The printer head consists of nine needles (only seven are used)
actuated by 9 coils. They accept for short time voltage between 5
and 12 V, and the needle will be advanced for about 1mm. The coil
resistance is about 6 ohms. This means a quite high impulse current.
To drive the coils Darlington transistors like in Figure 49.
45
It consists of 9 optocouplers that drive 9 TIP102 transistors,

acting like switches. No protection diodes are necessary because
they are included in the transistors. The connector J3 brings TTL
signals from FPGA and J6 is attached to the printer head.
10.3. Driving TV cameras
In the irradiation system there are two video cameras available.

One is inside the accelerator pipe, in vacuum, attached to the beam
diagnostic system. It is suited for observing the fluorescent screen.
The second one is outside, and it is attached to the tape roller. The
R5
1 U5 6 R6
330 5 100k
2
4 1
2 CNY17-4 Q5
3
R16 R11 TIP102
1 U10 6 R17
1k
330 5 100k
2
4 1
2 CNY17-4 Q10
3
R27 R26 TIP102
1 U11 6 R28
1k
330 5 100k
2
4 1
2 CNY17-4 Q11
3
R34 R33 TIP102
1 U12 6 R35
J3 1k
330 5 100k
1 2
2 4 1
3 2 CNY17-4 Q16
4 3
5 R37 R36 TIP102
6 1 U13 6 R38
7 1k
8 330 5 100k
9 2
10 4 1 J6
11 2 CNY17-4 Q17
12 3 18 17
R44 R43 TIP102 16 15
CON12 1 U18 6 R45 14 13
1k 12 11
330 5 100k 10 9
2 8 7
4 1 6 5
2 CNY17-4 Q22 4 3
3 2 1
R51 R50 TIP102
1 U19 6 R52 Print Head
1k
330 5 100k
2
4 1
2 CNY17-4 Q23
3
R58 R57 TIP102
1 U24 6 R59
1k
330 5 100k
2
4 1
2 CNY17-4 Q28
3
R69 R68 TIP102
1 U25 6 R70
1k
330 5 100k
2
4 1
2 CNY17-4 Q33
3
R75 TIP102
J33
J32 1k
1
1
-12V
+12V
Figure 49 Printer head driver

46
operator can observe the tape movement and if something does not
work. Because the system is thought to be mobile, only one image is
available at a time through the Hauppage video capture device. This
part has the role to switch both, the video signal and the power
supply signal to one or the other video camera.
Figure 51 shows this circuit. It is driven from FPGA (pin 79 from
Flex10k10) through an optocoupler CNY17-4. It drives two TTL
compatible relays. One switches the video signals (K1) and the
second switches the power supply (K2). Switching the power supply
is necessary because the video camera is getting hot and it cannot
be cooled in vacuum.
10.4. Interfacing the beam shutter
U3 J2
J1 LM7805C/TO220 100k R1 IN 4
1 3 U2 CNY 17-1 R2
1 IN OUT 6 1 1 3
2 Q13
GND
+ C1 C2 + BD190 1 5 330 2
+5V 10uF 2
10uF 4
Out 4 2
2
5
D1
1 3
1N4148 R3 J3 2
D2 10k
5
1N4148
Figure 50 Beam shutter interface schematic

The beam shutter needs a voltage greater than 5V in order to
completely shut off the ion beam. The previous experiments with TTL
level drivers were unsuccessful. A continuous track of holes has
been obtained after etching the polymer. The electrostatic beam
shutter is driven through an optocoupler in order to insulate the
device and to ensure proper protection. The adapter schematic is
presented in Figure 50. It consists of a 6.4 V stabilizer (7805 + 2 x
1N4148), a switch transistor (BD190) and an optocoupler (CNY-17).
Applying TTL logic H (around 3.5V) on ACC input will open the
switch transistor (BD190). Its saturation voltage is around 0.4V. The
collector is connected to the shutter and delivers around 6V, which is
more than enough for completely shutting the ion beam (specification
from Uppsala is 5V for completely switch off the beam).
47
J11
5
4
5 1 3
4 J12 R78 2
3 1 1 U26 6
2 Video1
TVCam 270 5 R79
100k
4 K1
2 CNY17-4 VIDEO J14
16
1
5
4
1 3 J15
-12V
2 5
14
4
8
1 3
Video2 2
J16 5 Video Out

4
1 3
2
12V Cam1
K2 -12V
CAM POWER
16
1
D1 J175
4
1n4148 1 3
2
14
12V Cam2
8
+12V
R90
100
Figure 51 Schematic for switching the video camera
11. LabView program

The LabView programs are designed for driving the camera
via the 8 bits interface (§ 8.1). Two programs are available: one for
acquiring pulses in order to establish the gain and the threshold and
the other for performing the irradiation. Both of them are described in
this chapter. Before starting the experiment, all VI's should be
published on the Web. For this the operator must go in Tools, Web
Publishing Tool, and there do "Save to Disk" and "Start Web Server".
The operator must note the web addresses by clicking "Preview in
Browser". Then the VI's can be operated from other computer via
Internet Explorer. The computer used for remote must have LabView
Run Time Engine installed. Right mouse button must be clicked and
select "Request Control" in order to operate via html. The addresses
are like:
http://computername.domainname/Main.htm,
http://computername.domainname/Irradiation.htm,
http://computername.domainname/Acquire.htm,
http://computername.domainname/BeamDiagControl.htm.
11.1. Main control program
For easyness of operation the VI's which operates the camera can be
48
started from the main control panel. This instrument is called Main.vi.
It allows to open and close other applications and to reset the digital
processor in the FPGA. The main panel is presented in Figure 52.
On the panel there are three butons (Beam trimming, Acquire
and Irradiate) with arrows between them. The arrows show the order
the operator should follow. First the beam must be trimmed. After this
is accomplished, the next operation is to check the quality of the
signal and trimm the gain of the preamplifier. For this the "Acquire"
button must be pressed. This action will close the previous
application and open Acquire.vi. "GO" button will start the acquiring
procedure. After accomplishing the gain trimming, one can start the
irradiation procedure. By pressing the "Irradiate" button, any other VI
will be shut down and Irradiation.vi will be activated. After setting up
the irradiation parameters, the operator has to press GO button to
start the procedure.
On the panel there is also "Reset FPGA", which will reset teh
digital processor, and the "Stop" button that closes the Main.vi.
Warning: "Reset FPGA" must not be pressed when acquire or
irradiation processes are running. It is available only for extreme
cases, when the system is not responding.
Figure 52 Main.vi front panel Figure 53 BeamDiagControl

front panel
49
11.2. Beam diagnostic VI
The process of trimming the ion beam is achieved at the

beginning. The instrument available for this operation is
BeamDiagControl.vi. Its Panel is shown in the next figure.
This instrument can control the beam diagnostic system
(Faraday cup magnet, fluorescent screen magnet, TV camera switch
and the beam line and the gain and sampling frequency. Also it
displays the ion flux measured by the digital processor and the
overflow signal for the flux meter.
11.3. Acquire VI
In principle this VI activate the acquire block inside the FPGA.

This action must be preceded by settings and succeeded by reading
the acquired data from FIFO. The front panel of this VI is presented
in Figure 54. In the top left part the operator can find some
controllers:
• Gain control pointer slide button - for adjusting the gain of the
preamplifier. Four steps are available (20, 40 80 and 160). These
were the gains for the previous version. For the current version 4
more steps must be introduced.
• ADC Clk control - adjust the ADC clock frequency. Also four
values are available: 10, 5, 2.5 and 1.25 MHz
• The threshold controller - for setting-up the threshold for starting
the acquisition. When a pulse occurs and the signal level is going
above this threshold, the data is then routed to FIFO memory. On
its right is an indicator that points the same threshold value but in
ADC counts.
In the top-left there are some indicators:
• Info field - gives information about the current process: “Waiting for
acquire to finish”, “Downloading data”
• Progress bar - shows the progress of the data downloading
process from FIFO to computer
• Status register indicator - shows with LED’s the states of every bit
in the status register
• Sample - shows the value of current read sample when transferred
from memory to computer
• The Peaks data graph - shows the acquired waveform
50
Figure 54 Acquire.vi – front panel
• The path dialog - located at the bottom of the screen, corresponds

to the path where the file with recorded data will be stored on
computer
The diagram of this VI, described in the following, is shown
detailed in Error! Reference source not found.. It consists of a
sequence structure with 7 frames.
The first frame (frame 0) reset the digital processor. For this,
GPCTR 1 is used in order to generate an about 200ms positive
pulse.
The second frame (frame 1) creates the file for saving the data,
adding in the title “AcqData”, the time (hours, minutes and seconds)
51
and the extension “.txt”. The file is spreadsheet type (ASCII).

The frame 2 writes in the control register. The gain and the
sampling frequency will be programmed and also the ion beam is
being open. A sub-vi, called “Write data to register” is used. The
delay of 100ms is not so important and can miss. The instruction
code is 17d=11h.
The fourth frame (frame 3) is setting up the threshold (the value of
the signal which starts the acquisition process). The threshold’s
decimal value must be converted in ADC counts and using the
instruction 20d=14h this is sent to the register in FPGA.
The following frame (frame 4) is clearing the FIFO memory. The
instruction code is 176d=B0h.
Frame 5 reads the state register (instruction 32d=20h) and
displays this on the front panel.
Frame number 6 includes another sequence structure, also with 7
frames. Subframe 0 reads the state register and displays its status.
Subframe 1 resets the memory again. Subframe 2 starts the acquire
process (instruction 192d=C0h). Subframe 3 reads the state register
and verifies if acquiring is end (bit 4=0) in a while loop. If the
condition is accomplished, then (subframe 4) the ion beam is cut off
(write in control register and reset the bit 4) and the programm quits
the “while” loop. Subframe 5 brings data from FIFO to computer,
converts into voltage values and stores them in a vector (Sample
Data). This is done in a “for” loop, executing a sequence that loads a
sample value from FIFO into FPGA (64d=40h), reads the state
register and displays it, brings the sample value into the computer
(47d=2Fh) using the subvi “Read Data from Register” and converts
the data to voltage. Subframe 6 reads and displays again the state
register (operator can check if FIFO is empty) and subframe 7 saves
the data to disk.
Frame number 7 closes the file and the program ends. It has to be
restarted for a new acquire.
The subvi’s will be described in the following paragraph.
Downloading more than 128 samples takes too long time and no
additional information will be obtained. This is necessary for high flux,
but it takes long time for all 32k of data.
11.4. Irradiation VI
This is instrument is the main one. It operates the whole system

during irradiation. It allows setting up the parameters, running the
52
process and recording data. The main panel is shown in Figure 55. It
contains controls, info field, graphs and digital displays. Their
functionality is described in the following.
• Gain – controls slide for the preamplifier gain. This value goes in
bits 0 and 1 in control register.
• F sample – control slide button for the ADC sampling frequency.
Four sampling frequencies are available: 10MHz, 5MHz, 2.5MHz
and 1.25MHz. This value goes in bits 2 and 3 in control register.
• Threshold – digital control for the threshold value (above which
the digital processor inside FPGA considers that a pulse starts). It
is displayed in ADC counts too. This value goes in TR.
• No of Ions/Frame – control for programming the number of
desired ions per frame. This value goes in PNILR and PNIHR in
FPGA.
• No of Frames – program the desired number of frames for the
current irradiation.
• Fluorescent screen – this button flips in and out the fluorescent
screen. This is bit D6 in control register.
• Faraday Cup – this button flips in and out the Faraday cup for
beam intensity measurements. This is bit D7 in control register.
• Video – it switch the images from video cameras: Beam Camera
for looking o fluorescent screen or Tape Camera to survey the
tape motion.
• Minimum energy – control the minimum value for accepting good
peaks
• Maximum energy - control the maximum value for accepting good
peaks
• Good Frame – is a digital indicator. Green light for this indicator
means that the current frame had fulfilled the tests and is
considered good one.
• Comments – character field in which the user can introduce some
comments about the irradiation that he wants to be saved in the
file.
• Info – Field for displaying messages about the current action.
• Frame Counter - displays the frame counter value (the software
counter)
• No of Ions Detected - Displays the number of ions detected in the
current frame.
• Peak - the value of the peak that is currently brought from FPGA.
• Peaks Data Graph - displays the amplitude of peaks detected
53
versus the frame number (the history of irradiation process)

• Channels - displays the results of the multichannel analyzer.
• Folder - the folder where the data file will be saved.
Figure 55 Front panel of main.vi
12. Mechanics
The mechanical part includes the beam diagnostic system and the
tape roller. The first one is located inside the beam line, in vacuum,
and the second one is attached through a flange by the first and is
located outside the vacuum. Both will be described in the following
paragraphs.
54
Fluorescent
BNC connector
screen Flipping magnet for
fluorescent screen
Mounting
flange
BNC connector
Flipping magnet for Faraday cup TV camera
Figure 56 Beam diagnostic system

12.1. Beam diagnostics
The beam diagnostic system has been designed to fit in a standard

accelerator pipe, in order to adjust the ion beam for the desired flux.
As it was briefly described in the paragraph 2.1, it contains a Faraday
cup, a fluorescent screen actuated by flipping magnets and a TV
camera. All are mounted in a metallic structure, like shown in Figure
56 and Figure 57.
On the mounting flange are fixed four metallic cylinders which
support two plates (black and yellow in the figures above). The black
plate is metallic and supports the TV camera. In the middle it has a
hole to allow the ion beam to pass forward. Under the first plate it is a
flipping magnet and the fluorescent screen. This can be flipped in
and out for diagnosing the ion beam. When it is flipped in, it blocked
the ion beam, the ions being stopped in the screen. No beam will be
recorded at the detector level. Under the fluorescent screen the
55
Fluorescent
BNC connector screen
Flipping magnet for
fluorescent screen
Mounting
flange
Faraday cup
NC connector
O ring
Flipping magnet for Faraday cup TV camera
Figure 57 Beam diagnostic system
Faraday cup is located together with its flipping magnet. A better

view is in Figure 57, where the Faraday cup is colored with blue.
After this level, the vacuum ends. A metallic plate closes the beam
line. In its center there is a hole and a nozzle on top (blue in the left
side of Figure 57, with a very fine hole (50 – 300 µm) covered with a
titanium foil (6 µm thick) for vacuum separation. In accordance with
the irradiation angle, the nozzle has to be changed. Two types where
designed, one for 90 degrees and another for 35.26 degrees, these
being the angles of interest.
12.2. Tape roller
The tape roller is dedicated for polymer tape transport in front of the
ion beam. A 3D view is presented in both Figure 58 and Figure 55.
56
TV camera Needle printer head Role Metallic

role
Tape role Role
Base plate
Rubber
pressure
role
Ion DC motor
detector with
DC motors encoder
for tape
advance
Figure 58 Tape roller (bottom view)
Needle printer head z

TV camera y
Tape roles
Guiding x
role
Base plate
Polymer
tape Guiding
role
Rubber DC motor
Ion pressure with
detector role encoder
for tape
advance
Figure 59 Tape roller

57
Everything is hosted by an aluminum plate with four metallic legs.

The polymer tape is supplied from the right tape role and it is
collected on the left tape role. Each role has attached one DC motor
(Figure 58), which can act as a break or pull, or can role the tape
from one role to the other (FF and REW). The tape is guided by two
guiding roles and pulled by the metallic role and by the pressure role.
The metallic role is actuated by a DC motor, which has angular
encoder attached for tape displacement monitoring. In the middle,
behind the tape (red color) is located the ion detector, its position
being adjustable (on y and z axis) in order to match the central axis
of the tape. Exactly above the ion detector, is the printer head, which
marks the irradiation point. The intersection between the middle axis
of the tape and the z axis passing through the mark defines the
irradiation point. The tape roles can be monitored with a TV camera.
Figure 60 Tape roller attached to the beam diagnostic (35.26

degrees)
58
The tape roller is attached with two screws on the beam

diagnostic mounting flange, outside the vacuum, under 90 or 35.26
degrees angle (Figure 60 and Figure 61).
Figure 61 Tape roller attached to the beam diagnostic (90

degrees)
59
Appendix 1 Electronic schematics
Amplifier 2 (8 gain levels)
60
2 poles, gain 1.47, fT=50kHz 2 poles, gain 2,1, fT=1MHz
High pass filter Low pass filter

+5Vaf
+5Vaf
C1
33p
7 1
7 1 U1
R1 U2
120k 3
R3 +
5 J1 3 R2 6
C2 C3 +
4 6 2
-
3 1 2 OP37/SO
-
2 4.7k 12k 4 8
22pF 4 8 OP37/SO
From preamp 22pF
2
R4 R5 C4
C5 320k 4.7k 6.8pF
15pF JP1 -5Vaf
-5Vaf
1 HP
JP2
1 2
BP Inverter JP3
1 2
Half wave rectifier
-5Vaf R6 1k R8 +5Vaf HP
1 3
+5Vaf
10k R72 10k
R9
0 +5Vaf
7 1
U3 C6 C7
+ R10
3 D1 10nF 510
R11 + 7 1
6 10uF U4 toADC
2
-
BAT82 3 JP4
R12 +
10k 4 8 OP37/SO 6 1 2
2
-
AD817 BP
4 8
1k
-5Vaf D2
C8 BAT82 R13 -5Vaf
3pF R14 1k C9
10k 3pF
+5V +5Vaf
R15
10
+ C10 + C11 + C12 + C13
C14 C15 10uF 10uF C16 C17 10uF 10uF
100nF 100nF 100nF 100nF
C18 C19 + C20 + C21 C22 C23 + C24 + C25

100nF 100nF 10uF 10uF 100nF 100nF 10uF 10uF
R16
10
-5V -5Vaf
Debouncer
61
Digital circuits
62
ADCClk
VC
VC VC
C1 C2
U1
R1 13 12
10 DGND 100nF DVDD CLK 100nF
14 11 DGND
VC R2 AVDD DVDD
15 10
U2 AVDD D7 ADCD7
1 8 10 C3 16 9
NC SEL 100nF VRTS D6 ADCD6
2 7
3 +Vin NC 6 2.5V 17 8
TEMP Vout VRT D5 ADCD5
4 5
C4 C5 GND TRIM C7 18 7
AVDD D4 ADCD4
1uF 100nF AD780 C6
100nF C8 C9 19 6
VIN D3 ADCD3
100uF 100nF
100nF 20 5
AVSS D2 ADCD2
21 4
AVSS D1 ADCD1
22 3
VRBS D0 ADCD0
23 2
R3 VRB DVSS
24 1
toADC DVSS NOE
51
C10 DGND AD775 DGND
10pF
Analog to digital converter
63
Power supplies
64
Power drivers
65
U1
J1 LM7805C/TO220
1 3
1 IN OUT +5V
GND
+5Va 100nF
C2 C3
C1 100nF
1000uF
2
J2
J3 J4 J5 J6 J7
hole1 hole2 hole3 hole4
hole5 1
AGND
1
1
LM7905C/TO220
1
100nF
DGND C4 C5 C6
GND
100nF
J8 1000uF
2 3
1 IN OUT -5V
DGND
U2
-5Va
U3
J9 LM7805C/TO220
1 3
1 IN OUT VC
+5Vadc
GND
C7 C8 C9
100nF 100nF
1000uF
2
J10
1
AGND
Voltage stabilizers
66
Appendix 2 - FPGA schematics
Top level design in FPGA

67
Receiver
68
Debouncer
Edge detector
69
Instruction decoder
70
Registers
71
Irradiation machine
72
Peak detector
73
Acquire
74
Readmem machine
75
Freq
76
Print
77
Encread
PWM
78
Motors
79
Appendix 3 – Instruction description
Write instructions
• Write in control register (Wr CR)

Register address: 1h
Instruction code: 11h VVh, where VVh is the data to be written;
11h=17d
Number of bytes: 2
Action: write VVh in CR
• Write in pressure role motor register 1 (Wr MPRLR) (the

register has been removed temporarily)
13h=19d
Number of bytes: 2
Action: write VVh in MPRLR
• Write in threshold register (Wr TR)

14h=20d
Number of bytes: 2
Action: write VVh in TR
• Write in motor fast forward register (Wr MFFR)

15h=21d
Number of bytes: 2
Action: write VVh in MFFR
• Write in motor rewind register (Wr MRR) (the register has

been removed temporarily)
16h=22d
Number of bytes: 2
Action: write VVh in MRR
80
• Write in pressure role motor register 2 (Wr MPRHR)

17h=23d
Number of bytes: 2
Action: write VVh in MPRHR
• Write in print register (Wr PRNR)

18h=24d
Number of bytes: 2
Action: write VVh in PRNR
• Write in preset number of ions low register (Wr PNLR)

Register address: Bh
Instruction code: 1Bh VVh, where VVh is the data to be written;
1Bh=27d
Number of bytes: 2
Action: write VVh in PNLR
• Write in preset number of ions high register (Wr PNHR)

Register address: Ch
Instruction code: 1Ch VVh, where VVh is the data to be written;
1Ch=28d
Number of bytes: 2
Action: write VVh in PNHR
Read instructions:
• Read from state register (Rd SR)

Instruction code: 20h VVh, where VVh is the data in SR; 20h=32d
Number of bytes: 2
Action: read VVh from CR
• Read from input register (Rd INR)

81
Instruction code: 22h VVh, where VVh is the data existing in INR;
22h=34d
Number of bytes: 2
Action: read VVh from INR
• Read from frame counter register 1 (Rd FCLR)

Instruction code: 29h VVh, where VVh is the data existing in FCLR;
29h=41d
Number of bytes: 2
Action: read VVh from FCLR
• Read from input register (Rd FCHR)

Register address: Ah
Instruction code: 2Ah VVh, where VVh is the data existing in FCHR;
2Ah=42d
Number of bytes: 2
Action: read VVh from FCHR
• Read from number of peaks register 1 (Rd NPLR)

Register address: Dh
Instruction code: 2Dh VVh, where VVh is the data existing in NPLR;
2Dh=45d
Number of bytes: 2
Action: read VVh from NPLR
• Read from number of peaks register 2 (Rd NPHR)

Register address: Eh
Instruction code: 2Eh VVh, where VVh is the data existing in NPHR;
2Eh=46d
Number of bytes: 2
Action: read VVh from NPHR
• Read from peak data register (Rd MEM)

Register address: Fh
Instruction code: 2Fh VVh, where VVh is the data existing in MEMR;
2Fh=47d
Number of bytes: 2
Action: read VVh from MEMR
82
Commands:
• Start irradiation (Irrd)

Instruction code: 30h; 30h=48d
Number of bytes: 1
Action: start the irradiation process. This process is signaled by
turning to 1 bit 0 in SR and will last until it returns to 0.
• Bring peak from memory in FPGA (RdPk)

Number of bytes: 1
Action: bring a peak value from external FIFO into MEM register
inside FPGA
• Go next frame (GoNF)

Number of bytes: 1
Action: start the tape advancement process. The tape will be
transported to next frame position. The process is signaled by turning
to 1 bit 6 in SR and will last until it returns to 0.
• Print (PRN)
Number of bytes: 1
Action: start printing on tape process. The tape is marked with the
needle printing head. The process is signaled by turning to 1 bit 5 in
SR and will last until it returns to 0.
• Reset registers (RstR) (internal signal removed)

Instruction code: A0h; A0h=160d
Number of bytes: 1
Action: reset all registers in FPGA.
• Reset FIFO memory (RstFIFO)

Instruction code: B0h; B0h=176d
Number of bytes: 1
Action: reset FIFO memory.
• Acquire signal (Acq)

Instruction code: C0h; C0h=192d
83
Number of bytes: 1
Action: start acquiring data from detector. 128 bytes of data from the
input signal is stored in FIFO memory. The process is signaled by
turning to 1 bit 4 in SR and will last until it returns to 0. Also the ion
beam will be open, this being signaled with bit 1 in SR on logic 1.
84
Appendix 4 Connections and cables
Appendix 4
Panels of irradiation system
C17
C1
C12 C18 C19

C2
C13 C20 C21
C3
C10
C22
C14
C7 C25 C26
C4 C9 C15
C8
C11 C23 C24
C5 C16
C6
Panel 1 – Card 1 Panel 2 – Card 2 Panel 3 – Card 3 Panel 4 – Card 4 Panel 5 – Card 5 Panel 6– Card 6
Irradiation system front panel - Connector numbering
MOTORS
PRINTER HEAD
C27
K TEST A
C34
C29 C31 C30
OUT C28 C33
ENCODER
C32
Back panel Front panel
Preamplifier front and back panel Tape roller panel
85
Connecting the preamplifier
C28 C9 R10
J4 K12
Preamplifier
EPF10k10
C28
J8, J7 C3
U20
J5, J6 K1
C27 C27’ C3’ Card 1
Cables: K1 and K12

K1 – multiple wires, band
Signal C3’ C27’ Signal
-5V 1 1 -5V
GND 2 2 GND
GND 3 3 GND
GND 4 4 GND
+5V 5 5 +5V
NC 6 6 NC
G1 7 7 G1
G0 8 8 G0
DGND 9 9 DGND
Preamplifier – panel 1
Signal C27 Preamplifier Signal
-5V 1 J8 -5V
GND 2 J10 GND
GND 3 J10 GND
GND 4 J10 GND
+5V 5 J7 +5V
NC 6 NC
G1 7 J6 G1
G0 8 J5 G0
DGND 9 J10 DGND
86
Preamplifier J4 – Panel C28
K12 – LEMO connectors, coaxial
Card 1 U20 – Panel C3

Signal C3 U20 Signal
-5V 1 8 -5V
GND 2 7 GND
GND 3 4 GND
GND 4 5 GND
+5V 5 6 +5V
NC 6 NC
G1 7 3 G1
G0 8 1 G0
DGND 9 2 DGND
87
Connecting the printer head
C34 Tape roller panel
C34’
K8
J3
EPF10k10
C10 C10’
C5
J4
J6 K2
Card 3 C20 C20’ C5’ Card 1
Cables: K2 and K8
K2 - multiple wires, band

Needle 3 1 1 Needle 3
GND 8 8 GND
+5V 9 9 +5V
NC 10 10 NC
Panel 1 C5 – Card 1 J4
Signal J4 C5 Signal
+5V 1 9 +5V
88
GND 9 8 GND
10 NC

Signal C20 J3 Signal
1 NC
9 Needle 7
10 Needle 8
GND 8 11 GND
12 NC

Signal C10 J6 Signal
1 +12V
2 Needle 8
3 +12V
4 Needle 7
+12V 16 5 +12V
+12V 14 7 +12V
+12V 12 9 +12V
+12V 10 11 +12V
+12V 8 13 +12V
+12V 6 15 +12V
+12V 4 17 +12V
89
NC 2
NC 1
K8 – multiple wires, band

+12V 16 16 +12V
+12V 14 14 +12V
+12V 12 12 +12V
+12V 10 10 +12V
+12V 8 8 +12V
+12V 6 6 +12V
+12V 4 4 +12V
NC 2 2 NC
NC 1 1 NC
90
Connecting flipping magnets and encoder
C32’
K5
J5 EPF10k10
J4 C1
J6
K6 J5
Card 4 C16 C16’ C1’ Card 1
Cables: K2 and K8
K6 – band, multiple wires
+5V 1
A 2
B 3
GND 4
+5V 5 1 +5V
PWM 6 2 PWM
nPWM 7 3 nPWM
GND 8 4 GND
NC 9
NC 10
5 NC
6 NC
7 NC
8 NC
9 NC
10 NC
91
10 NC
9 NC
8 NC
+5V 1 7 +5V
A 2 6 A
B 3 5 B
GND 4 4 GND
+5V 5
PWM 6
nPWM 7
GND 8
NC 9
NC 10
3 NC
2 NC
1 NC
Card 1 J6 and J5 – Panel 1 C1

Signal C1 J5 Signal J6 Signal
+5V 1 NC 1 +5V
A 2 NC 2 A
B 3 NC 3 B
GND 4 4 GND
+5V 5 1 +5V
PWM 6 2 PWM
nPWM 7 3 nPWM
GND 8 4 GND
NC 9
NC 10
Card 4 J4 and J5 – Panel 4 C16

Signal C16 J4 Signal J5 Signal
+5V 1 1 +5V
Q1Q7 2 3 Q1Q7
Q2Q6 3 4 Q2Q6
GND 4 2 GND
+5V 5 1 +5V
92
Q3Q9 6 3 Q3Q9
Q4Q8 7 4 Q4Q8
GND 8 2 GND
NC 9
NC 10
93
Connecting the motors
C33’
J7 J8
C24 C24'
JP4
K4
EPF10k10
J18 J9 J10
C2
J13 K7
Card 5 C23 C2’
C23’ Card 1
Cables: K4 and K7
K4 – multiple wire, band

VCC 1 1 VCC
X3 2 2 X3
VCC 3 3 VCC
X2 4 4 X2
VCC 5 5 VCC
X1 6 6 X1
VCC 7 7 VCC
GND 8 8 GND
GND 9 9 GND
GND 10 10 GND

X3 - 1 1 1 X3 - 1
X3 - 2 2 2 X3 - 2
NC 3 3 NC
NC 4 4 NC
NC 5 5 NC
NC 6 6 NC
94
X1 - 1 7 7 X1 - 1
X1 - 2 8 8 X1 - 2
NC 9 9 NC
NC 10 10 NC
NC 11 11 NC
X2 - 1 12 12 X2 - 1
X2 - 2 13 13 X2 - 2
X3 - 1 14 14 X3 - 1
X3 - 2 15 15 X3 - 2
NC 16 16 NC
NC 17 17 NC
NC 18 18 NC
NC 19 19 NC
X1 - 1 20 20 X1 - 1
X1 - 2 21 21 X1 - 2
NC 22 22 NC
NC 23 23 NC
X2 - 1 24 24 X2 - 1
X2 - 2 25 25 X2 - 2
Card1 JP4 – Panel 1 C2

Signal JP4 C2 Signal
VCC 1 1 VCC
X3 2 2 X3
VCC 3 3 VCC
X2 4 4 X2
VCC 5 5 VCC
X1 6 6 X1
VCC 7 7 VCC
GND 8 8 GND
9 GND
10 GND
Panel 5 C23 – Card 5 J9, J10, J18

Signal C23 J9 Signal J10 Signal J18 Signal
VCC 1 1 VCC
X3 2 3 X3
VCC 3 1 VCC
X2 4 3 X2
95
VCC 5 1 VCC
X1 6 3 X1
VCC 7
GND 8 2 GND
GND 9 2 GND
GND 10 2 GND
4 NC
4 NC
4 NC
Panel 5 C24 – Card 5 J7, J8, J13

Signal C24 J7 Signal J8 Signal J13 Signal
X3 - 1 1 1 X3 - 1
X3 - 2 2 2 X3 - 2
NC 3
NC 4
NC 5
NC 6
X1 - 1 7 1 X1 - 1
X1 - 2 8 2 X1 - 2
NC 9
NC 10
NC 11
X2 - 1 12 1 X2 - 1
X2 - 2 13 2 X2 - 2
X3 - 1 14 1 X3 - 1
X3 - 2 15 2 X3 - 2
NC 16
NC 17
NC 18
NC 19
X1 - 1 20 1 X1 - 1
X1 - 2 21 2 X1 - 2
NC 22
NC 23
X2 - 1 24 1 X2 - 1
X2 - 2 25 2 X2 - 2
96
TV camera switch and Beam control
C26 C25
C25 Panel 6
K9 J2
C7
EPF10k10
to beam
control
J15 J3
K13
Card 5 C17 C8
Card 1
Cables: K9 and K13
Panel 1 C7 – Panel 6 C25: cable K9 – LEMO

Panel 1 C8 – Panel 5 C17: cable K13 – LEMO
97
Connecting TV cameras
Hauppauge
S Video
K13
K22
K23
Hauppauge
C18 C19
C20 C21
K15 K10
K14
C22
K10 K14
Role
TV camera
K15
Panel 5
cables K10, K14, K15, K22, K23

The pictures are captured through a Hauppauge USB WinTV device
connected via USB to the laptop. TV cameras have power supply (12V) and
video out. Switching the camera means switch the power line and the video
line.
Panel 5 C22 – Hauppauge WinTV SVideo: cable K10 – Lemo cable
Panel 5 C21 – Role TV camera (video): cable K14 – Lemo cable attached to
the role video camera
Panel 5 C20 – Role TV camera (+12V): K15 – Lemo cable attached to the
role video camera
Panel 5 C18 – Beam diagnostic System: K22 – Lemo cable
Panel 5 C19 – Beam diagnostic System: K23 – Lemo cable
98
Computer interface
SW1
DAQ 6062
EPF10k10
C6’
J1
SCB-68
K3
National Instruments U15
C6’ Card 1
cable K3

Signal C6' SCB-68 Signal
nStrobe 1 2 nStrobe
+5V 2 14 +5V
GND 3 13 GND
D3 4 47 D3
D7 5 48 D7
GND 6 15 GND
D2 7 49 D2
D6 8 16 D6
GND 9 50 GND
D1 10 17 D1
D5 11 51 D5
GND 12 18 GND
D0 13 52 D0
D4 14 19 D4
GND 15 53 GND
Reset 16 40 Reset
Card 1 J1, SW1, U15 – Panel 1 C6

Signal C6 J1 Signal SW1 Signal U15 Signal
nStrobe 1 1 nStrobe
+5V 2 +5V U15-3 +5V
GND 3 7 GND U15-2 GND
D3 4 6 D3
D7 5 2 D7
GND 6 7 GND
99
D2 7 7 D2
D6 8 3 D6
GND 9 7 GND
D1 10 8 D1
D5 11 4 D5
GND 12 7 GND
D0 13 9 D0
D4 14 5 D4
GND 15 SW1 GND
Reset 16 SW2 Reset
100
Connecting the Beam diagnostic system
Faraday cup flipping Fluorescent
magnet screen flipping
(K18, K19) magnet
(K16, K17)
Vacuum video
Faraday cup camera
repeller (K14, K15)
(K21, K20)
Cable connections to beam diagnostic
C14 K17
J1
C15 K16
Card 4
cables K17, K16
101
Connection between the cards
• Card 1 – Card 2
Card 1 Card 2
Connector Signal Signal Connector
J8 +5VA +5VA J19
J9 AGND AGND J21
J11 -5VA -5VA J23
J24 +5VADC +5VADC J12
J25 AGND AGND J13
• Card 4 – Card 5
+12 V for TV cameras is cut-off on card 5 and it is brought from card 4 (see
appendix 4).
• Card 4 – accelerator level adaptor
+12V is brought from card 4
102
Appendix 5 – Boards: layout and placement
Not used
R35→100nF
1n
4k7
Card 1 Assembly top
103
Card 1 Assembly bottom
104
10k
10nF
cut
1k
10k
Card 1 – Top layer
105
cut
Card 1 – Bottom layer
106
Card 1 - Power layer
107
Card 1 - Ground layer
108
Card 2 – Assembly top
109
110
111
112
113
Card 4 – Top layer
114
115
+12V
from
card 4
GND
from Cut
card 4
Card 5 – Bottom layout
116
Card 5 – Top layout
117
Amplifier 1 – Assembly top
Amplifier 1 – Top layer
Amplifier 1 – Bottom layer
+12V
from card 4
Level adapter – Assembly top and Bottom layer
118
Amplifier 2 Assembly top
Amplifier 2 Bootom layer
Amplifier 2 Top layer
Amplifier 2 (8 gain levels)
119
Appendix 6 – Mechanical Assemblies
Beam diagnostic system
Lateral view
Back side view
120
Tape roller
Tape roller – top view
Tape roller – side view
121
Tape roller and beam diagnostic assembled together
Tape roller and beam diagnostic assembled together - 90°
Tape roller and beam diagnostic assembled together - 35°
122
Electronic control unit
Electronic control unit - front panel
123
Preset number of ions irradiation system Bibliography
BIBLIOGRAPHY
[1] Radiation detectors and signal processing, H. Spieler, 2001,

Heidelberg University
[2] A new ion detector array and digital signal processor based interface,
Measurement science and technology , No. 5, 1994, pp. 389-393
[3] S1223 pin diode series – datasheet, Hamamatsu Photonics K.K. Solid
State Division, 2001, Japan
[4] Sensors, signals and systems for electromagnetic radiation
experiments in physics – PhD thesis, M. Minerskjold, Royal Institute of
Technology Stockholm, 1998
[5] Beam control in the spot scanning irradiation, M. Kanazawa et all,
Proc. of the second asian particle accelerator conference, Beijing, China,
2001, pp. 846-848
[6] Development of Krakow external microbeam – report no. 1955/AP –
single ion hit facility, W. Polak et all, Polish Academy of Science, Krakow,
2004
[7] A mixed analog-digital pulse spectrometer, Joao M.R. Cardoso, J.
Basilio Simoes, Carlos M.B.A. Correia, Nuclear Instruments and Methods
in Physics Research A 422 (1999) 400Ð404
[8] A new approach to automated peak detection, Kristin H. Jarman, Don
S. Daly, Kevin K. Anderson, Karen L. Wahl, Chemometrics and Intelligent
Laboratory Systems 69 (2003) 61– 76
[9] A PC104 Multiprocessor DSP System for Radiation Spectroscopy
Applications, J. Basílio Simões, João Cardoso, Nuno Cruz, and Carlos M.
B. A. Correia,
[10] Past, present and future of data acquisition systems in high energy
physics experiments, J. Toledoa, F.J. Moraa, H. Mullerb, Microprocessors
and Microsystems 27 (2003) 353–358
[11] CdZnTe spectra improvement through digital pulse amplitude
correction using the linear sliding method
[12] Joao M. Cardoso, J. Bas!ilio Simoes, Tiago Menezes, Carlos M.B.A.
Correia, Nuclear Instruments and Methods in Physics Research A 505
(2003) 334–337
[13] A Computer-Based Digital Signal Processing for Nuclear
Scintillator Detectors, M. A. Ashour, A. M. Abo Shosha
[14] Highly integrated pulse processor, Michel Bordessoule, Roger
Bosshard, Nuclear Instruments and Methods in Physics Research A 356
(1995) 452-456
Preset number of ions irradiation system Bibliography
[15] Digital Pulse Processing: New Possibilities in Nuclear Spectroscopy,

W.K. Warburton, M. Momayezi, B. Hubbard-Nelson and W. Skulski,
Conference on Industrial Radiation and Radioisotope Measurement
applications (IRRMA-99), October 3-7, 1999, Raleigh
[16] Linear electronics for Si-detectors and its energy calibration for use
in heavy ion experiments
[17] N. Taccetti, G. Poggi, L. Carraresi, M. Bini, G. Casini, R. Ciaranfi,
L. Giuntini, P.R. Maurenzig, M. Montecchi, A. Olmi, G. Pasquali, S.
Piantelli, A.A. Stefanini, Nuclear Instruments and Methods in Physics
Research A 496 (2003) 481–495
[18] Optimized Linear Pulse Amplifier circuit based on a Composite Op
Amp Configuration, João M. Cardoso, J. Basílio Simões, Carlos M. B. A.
Correia
[19] Pulse processing architectures, J. Basõ« lio Simoes, Carlos M.B.A.
Correia, Nuclear Instruments and Methods in Physics Research A 422
(1999) 405Ð410
[20] Sonomicrometric Arrival Time Detection Using Reconfigurable
FPGA, Pong P. Chu and Tamman Shaar
[21] Development of a compact and precise ion irradiation system,
Toshiyuki Iida, Fuminobu Sato, Teruya Tanaka, Masao Naito
[22] Design of a single ion hit facility, M. Cholewa, A. Saint, G.J.F.
Legge, T. Kamiya, Nuclear Instruments and Methods in Physics Research B
130 fI997) 275-279
[23] A DSP controlled data acquisition system for CELSIUS, M.
Bengtsson, T. Lofnes, V. Ziemann, Nuclear Instruments and Methods in
Physics Research A 441 (2000) 76-80

Irradiation System

Caricato da

Informazioni sul documento

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Irradiation System

Caricato da

Copyright:

Formati disponibili

Preset number of ions irradiation system Acknoledgement

This work has been supported from contract HPRN-CT-2000-00047,

9.10. Encoder reader 31

9.14. Driving flipping magnets 38

9.15. Digital circuit schematic 39

9.16. Data acquisition board 42

9.17. Communication protocol 43

10. Power circuits 43

10.1. Motors drivers 44

10.2. Printer head drivers 45

10.3. Driving TV cameras 46

10.4. Interfacing the beam shutter 47

11. LabView program 48

11.1. Main control program 48

11.2. Beam diagnostic VI 50

12.1. Beam diagnostics 55

12.2. Tape roller 56

PRESET NUMBER OF IONS IRRADIATION SYSTEM

Fluorescent Faraday Ion Detector REW Motor Electronics Power Configuration

Pressure Driving Motor

Figure 1 Detailed block diagram of the irradiation system

2.1. Beam trimming

The beam trimming is achieved using the beam diagnostic system. It

register (address 0h). This process can be controlled with the VI

Pressure Driving Motor III

a) Trimming the beam with the Faraday cup

Figure 2.a Trimming the ion beam

Fluorescent Faraday Ion Detector REW Motor Electronics Power Configuration

Pressure Driving Motor

b) Trimming the beam with the fluorescent screen NetMeeting

Fluorescent Faraday Ion Detector REW Motor Electronics Power Configuration

b) Trimming the beam measuring the ion flux

Figure 3.b Trimming the ion beam

2.2. Adjusting the preamplifier gain

In order to achieve this, a special block (Acquire) has been included

in the digital processor. It takes 256 samples of the signal, starting

Figure 4 Acquiring pulses for gain adjustment

Figure 6 Irradiation process

Warning: removing the window will expose the diode to air.

The preamplifier consists of two stages. The first one is an

Det- Op27 15p

-5V +5V R0 5k 20k

Figure 9 The first stage of the detector preamplifier

capacitance in parallel for compensating the frequency response and

-5V +5V 15p 15p

Figure 10 The second stage of the preamplifier

Figure 11 Shaping filter: F1 - High pass filter, F2 - Low pass filter

6. Negative pulse suppressor

Figure 12 The negative pulse suppressor

7. Analog to digital converter

Figure 13 The analog to digital converter

The level adapter is built around AD817, which is a fast

while maintaining very low power consumption (60 mW). In order to

Figure 14 Layout for ADC

8. Digital processor FPGA

beam (around 250us)

8.1. 8 bit Computer interface

The interface with a host computer or other processor is a bi-

Figure 15 The schematic of the Receiver block

generated by the host (computer or other processor). The data bus is

Figure 16 The associated waveforms for the block Receiver

Figure 17 The debouncer

Figure 18 Waveforms for debouncer

8.2. Clock divider