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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Module 3 Notes (Part-A)


Signed Numbers and Strings: Signed number Arithmetic Operations, String operations.
Memory and Memory interfacing: Memory address decoding, data integrity in RAM and
ROM, 16-bit memory interfacing. 8255 I/O programming: I/O addresses MAP of x86 PC’s,
programming and interfacingthe 8255.
Text book 1: Ch 6: 6.1, 6.2. Ch 10: 10.2, 10.4, 10.5. Ch 11: 11.1 to 11.4

3.1 String Manipulation Instructions


A series of data bytes or words available in memory at consecutive locations, to be referred
to collectively or individually, are called as byte strings or word strings. For referring to a
string, two parameters are required:
(a) Starting or end address of the string and
(b) Length of the string.

There are 5 types of string instructions:


1.MOVS/MOVSB/MOVSW
2.CMPS/CMPSB/CMPSW
3.SCAS/SCASB/SCASW
4.LODS/LODSB/LODSW
5.STOS/STOSB/STOSW
These instructions can be preceded by a prefix to instruction
REP/REPE/REPZ/REPNE/REPNZ.

REP: Repeat Instruction Prefix


This instruction is used as a prefix to other instructions. The instruction, to which the REP
prefix is provided, is executed repeatedly until the CX register becomes zero.
REP: Repeat the followed instruction till CX=0 if CX=0 exit
REPE/REPZ: if CX=0 or ZF=0; if it is non zero, ZF=1 if it is equal or zero.
REPNE/REPNZ: if CX=0 or ZF=1; if it is zero, ZF=1 hence exit.
Example:
REPZ CMPSB ; compare string bytes until CX=0 or until string bytes are not equal i.e.
ZF=0.
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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

MOVSB/MOVSW: Move String Byte or String Word


This copies a word or byte from source (DS) to destination (ES) segment. SI stores the offset
of source word or byte, DI stores the offset of destination word or byte. For multiple word or
byte moves the count is moved to CX. SI and DI are automatically adjusted to point to next
source and destination. If DF=0 SI and DI are incremented by 1 or 2 bytes depending on
byte or word move. If DF=1 then SI and DI will automatically decrement by 1 or 2 bytes
depending on byte or word move. MOVS does not affect any flags.
Example:
REP MOVSB ; decrement CX and move a string byte from source
; pointed by SI till CX=0

CMPS: Compare String Byte or String Word


It is used to compare a byte(word) in one string with a byte(word) in another string. SI holds
the offset of source string found in DS. DI holds the offset of destination string found in ES.
Comparing is done by subtracting the byte or word pointed to by SI from byte or word
pointed by DI. After comparison SI, DI will increment or decrement based on DF. CX is
used as a counter which decrements by 1 after comparison. This will go until CX=0.
Example:
REPE CMPSW ; if both strings are completely equal i.e. CX becomes zero
; the ZF is set, otherwise, ZF is reset.

SCAS: Scan String Byte or String Word


This compares a string byte with a byte in AL or string word with a word in AX. Here the
source is assumed to be in AL/AX. It does not change operands. Flags are updated. The
string to be scanned must be in ES and DI points to it(string in ES is a destination string).
CX acts as a counter and decrements by 1 after each comparison, this will continue till
CX=0.
Example:
MOV AX, SEG
MOV ES, AX
MOV DI, OFFSET
MOV CX, 010H

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

MOV AX, WORD


CLD
REPNE SCASW ; Scan the 010H bytes of the string, till a match to WORD is found

LODS: Load String Byte or String Word


The LODS instruction loads the AL/AX register by the content of a string pointed by DS: SI
register pair. The SI is modified automatically depending upon DF. If it is a byte transfer
(LODSB), the SI is modified by one and it is a word transfer (LODSW), the SI is modified by
two. No other flags are affected by this instruction.
Example:
CLD ; SI will auto incremented
MOV SI, OFFSET S-STRING ; SI pointing to string source
LODSB S-STRING ; load source string to al

STOS: Store String Byte or String Word


The STOS instruction stores the AL/AX register contents to a location in the string pointed
by ES:DI register pair. The DI is modified accordingly. No flags are affected by this
instruction.
Example:
MOV DI, OFFSET D-STRING ; point DI to dest string
STOS D-STRING ; If it is byte type then it is replaced with AL or it is replaced with
AX.

Write a program using string instruction to accept a string from keyboard and
check for palindrome and accordingly display appropriate message.
05M Dec-17 June-18
Note: Function 0AH is used to read a string of characters from keyboard.
.MODEL SMALL
.DATA
STR DB 'MALAYALAM'
LEN EQU $-STR
HALFLEN DW LEN/2

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

MSGYES DB 10,13,'PAL $'


MSGNO DB 10,13,’NPAL $'
.CODE
MOV AX,@DATA
MOV DS,AX
MOV SI,0
MOV DI,LEN
DEC DI
MOV CX,HALFLEN
BACK:MOV AL,STR[SI]
CMP AL,STR[DI]
JNE EXIT
INC SI
DEC DI
LOOP BACK
LEA DX,MSGYES
JMP DISP
EXIT: LEA DX,MSGNO
DISP: MOV AH,09H
INT 21H
MOV AH,4CH
INT 21H
END

Write an ALP to search a given character in the array of characters using string
instructions and also find the search position.
.MODEL SMALL
.DATA
ARRAY DB 11H, 22H, 43H, 55H, 89H, 09H, 78H, 66H, 77H, 59H
SER_NO DB 09H
SER_POS DB ?
.CODE

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

MOV AX, @DATA


MOV DS, AX
MOV CX, 000AH
LEA DI, ARRAY
MOV AL, SER_NO
CLD
REPNE SCAS ARRAY
MOV AL, 10
SUB AL,CL ;TO FIND SEARCH POSITION SUBTRACT WITH 10
MOV SER_POS, AL
END

WALP using 8086 for String Transfer


model small
.data
str1 DB 'abcdef'
len DB $-str1
str2 DB ?
.code
mov AX,@data
mov DS,AX
mov ES,AX
mov SI,OFFSET str1
mov DI,OFFSET str2
cld
mov CX,len
repnz movsb
mov AH,4CH
int 21H
end

WALP using 8086 for String Reversing


.model small
.data
str DB 'abcdef'
len EQU $-str
halflen DW len/2
.code
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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

mov AX,@data
mov DS,AX
mov SI,0
mov DI,len
dec DI
mov CX,halflen
back: mov AL,str[SI]
xchg AL,str[DI]
mov str[SI],AL
inc SI
dec DI
loop back
mov AH,4CH
int 21H
end

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

3.2 Programmable Peripheral Interface 8255


3.2.1 Features of 8255A
• The 8255A is a widely used, programmable, parallel I/O (Input/output) device.
• It can be programmed to transfer data under various conditions, from simple I/O to
interrupt I/O.
• It is compatible with all Intel and most other microprocessors.
• It is completely TTL (Transistor–transistor logic) compatible.
• It has three 8-bit ports : Port A, Port B and Port C
• Its bit set/reset mode allows setting and resetting of individual bits of Port C.
• The 8255 can operate in 3 I/O modes :
(i) Mode 0, (ii) Mode 1 and (iii) Mode 2
• All I/O pins of 8255 have 2.5 mA DC driving capacity.

Pin Symbols Functions


These bi-directional, tri-state data bus lines are connected to the
D0 – D7
system data bus. They are used to transfer data and control word
(Data Bus)
from µp to 8255 or to receive data or status word from 8255 to µp.
PA0 – PA7 These 8-bit bi-directional I/O pins are used to send data to
(Port A) output device and to receive data from input device.

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

PB0 – PB7 These 8-bit bi-directional I/O pins are used to send data to
(Port B) output device and to receive data from input device.
These 8-bit bi-directional I/O pins are divided into two groups PCL
(PC3-PC0) and PCU (PC7-PC0). These groups individually can
PC0 – PC7
transfer data in or out when programmed for simple I/O, and
(Port C)
used as handshake signals when programmed for handshake or
bi-directional modes.
When this pin is low, the CPU can read the data in the ports or
(Read)
the status word, through the data buffer.
When this pin is low, the CPU can write data on the ports or in
(Write)
the control register through the data bus buffer.
This is an active low input which can be enabled for data transfer
(Chip Select)
operation between the CPU and the 8255.
This is an active high input used to reset 8255. When RESET
Reset input is high, the control register is cleared and all the ports are
set to the input mode.
These input signals along with RD and WR inputs control the
A0 and A1 selection of the control/status word registers or one of the three
ports.

Why interfacing is required? Explain


To connect any interfacing device (keyboard/stepper motor/Seven segment) to
processor, we require a peripheral interface. To drive any device, processor cannot be
connected directly to an application. Processor should be connected via peripheral
interface device like 8255 (PPI), using this device we can read or write to device or
device to processor.

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

3.2.2 Block diagram of 8255


The internal block diagram of 8255A consists of data bus buffer, control logic and Group A
and Group B controls.
Data Bus Buffer: This tri-state bi-directional buffer is used to interface the internal data
bus of 8255 to the system data bus. Input or Output instructions executed by the CPU
either Read data from, or Write data into the buffer.
Control Logic: The control logic block accepts control bus signals as well as inputs from
the address bus, and issues commands to the individual group control blocks. It issues
appropriate enabling signals to access the required data/ control words or status word.

Fig: Block diagram of 8255A


Group A and Group B Controls:
Each of the Group A and Group B control blocks receives control words from the CPU and
issues appropriate commands to the ports associated with it. The Group A control blocks
controls Port A and PC7 – PC4 while the Group B control block controls Port B and PC4-PC0.
Port A: This has an 8-bit latched and buffered output and an 8-bit input latch. It can be
programmed in three modes: mode 0, mode 1 and mode 2.

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Port B: This has an 8-bit data I/O latch/buffer and an 8-bit data input buffer. It can be
programmed in mode 0 and mode 1.
Port C: This has one 8-bit unlatched input buffer and an 8-bit output latch/buffer. Port C
can be splitted into two parts and each can be used as control signals for port A and B in
the handshake mode. It can be programmed for bit set/ reset operation.

3.2.3Operation Modes of 8255


8255 operates in two modes:
i) Bit Set-Reset (BSR) Mode and
ii) I/O Modes
Mode 0: Simple Input/output
Mode 1: Input/output with handshake
Mode 2: Bi-directional I/O data transfer

Bit Set-Reset (BSR) Mode:


The individual bits of Port C can be set or reset by sending out a single OUT instruction to
the control register. When Port C is used for control/status operation, this feature can be
used to set or reset individual bits.

I/O Modes:
Mode 0 – Simple Input/ Output
In this mode, ports A, B are used as two simple 8-bit I/O ports, Port C as two 4-bit ports.
Each port can be programmed to function as simply an input port or an output port.
The input/output features in Mode 0 are as follows:
• Outputs are latched.
• Inputs are buffered, not latched.
• Ports do not have handshake or interrupt capability.

3.2.4Control Word Formats


A high on the RESET pin causes all 24 lines of the three 8-bit ports to be in the input
mode. All flip-flops are cleared and the interrupts are reset. This condition is maintained
even after the RESET goes low. The ports of the 8255 can be programmed for any other
mode by writing a single control word into the control register, when required.

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Bit Set/Reset Control Word Format

The eight possible combinations of the status of bits D3 – D1 (B2 B1 B0) in the Bit Set-Reset
format determine particular bit in PC0 – PC7 being set or reset as per the status of bit D0. A
BSR word is to be written for each bit that is to be set or reset.
For example, if bit PC3 is to be set and bit PC4 is to be reset, appropriate BSR words that
will have to be loaded into the control register will be, 0XXX0111 and 0XXX1000,
respectively, where X is don’t care.

Example-1: Write a program to blink Port C bit 0 of the 8255. Assume


address of control word register of 8255 is 83H. Use Bit Set/Reset Mode.
Solution:
i) Control Word to make bit 0 high
0 X X X 0 0 0 1 =01H
ii) Control Word to make bit 0 low
0 X X X 0 0 0 0 =00H
Source Program:
BACK : MOV AL, 01H
OUT 83H, AL
CALL DELAY
MOV AL, 00H
OUT 83H, AL
CALL DELAY
JMP BACK

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

8255 I/O Mode Definition Format

Example-2: Write a program to initialize 8255 in the configuration given


below:
1. Port A : Simple input ; Port B : Simple output
2. Port CL : Output ; Port CU : Input
Assume address of the control word register of 8255 is 83H.
Solution:
1 0 0 1 1 0 0 0 =98H
Source program : MOV AL, 98H
OUT 83H, AL

Example-3: Write a program to initialize 8255 in the configuration given


below :
1. Port A : Output with handshake ;Port B : Input with handshake
2. Port CL : Output ; Port CU : Input
Assume address of the control word register of 8255 is 23H
Solution:
1 0 1 0 1 1 1 0 =AEH
Source program : MOV AL, 0AEH
OUT 23H, AL

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Example-4:
(a) Find the control word if PA = Out, PB = in, PC0-PC3 = in and PC4-PC7 = out.
(b) Program the 8255 to get data from Port B and Send it to Port A. In addition, data
from PCL is sent out to the CPU. Use port address of 300H – 303H for the 8255 chip.
Solution:
a) Using the control word format of I/O mode we get the control word of 1000 0011 in
binary or 83H.

Fig 11-13: 8255 configuration example

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Example-5:

Example-6:

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Fig 11-14: 8255 configuration example

Buffering 300 – 31FH Address Range:


• When accessing the system bus via the expansion slot; we must make sure that the
plug-in card does not interfere with the working of system buses on the motherboard.
• To do that we isolate (buffer) a range of I/O addresses using the 74LS245 chip.

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

• In buffering, the data bus is accessed only for a specific address range, and access by
any address beyond the range is blocked.
• The following Fig shows how the I/O address range 300H-31FH is buffered with the
use of the 74LS245.

• The following Fig shows another example of 8255 interfacing using the 74LS138
decoder. As shown in the Fig., Y0 and Y1 are used for the 8255 and 8253,
respectively. The Table shows the 74LS 138 address assignment.

The following Fig shows the circuit for buffering all the buses. The 74LS244 is used to boost
the address and control signals.

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Fig: Design of 8-bit ISA PC Bus Extender


The following shows a test program to toggle the PA and PB bits. Notice that in order to
avoid locking up the system, INT 16H is used to exit upon pressing any key.
The 74LS138 is a high speed 1-of-8 Decoder/Demultiplexer. This device is ideally
74LS138
suited for high speed bipolar memory chip select address decoding.
The 74LS244 is an octal buffer and line driver designed to be employed as memory
74LS244 address drivers, clock drivers, and bus-orientated transmitters/receivers which
provide improved PC board density.
The 74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous
74LS245
2-way data communication between data buses.
The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for
8253 microprocessors to perform timing and counting functions using three 16-bit
registers.
The 8255A is a general purpose programmable I/O device designed to transfer the
8255 data from I/O to interrupt I/O under certain conditions as required. It can be used
with almost any microprocessor.

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Example 7:

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

Write an ALP to read PB and Check number of one’s in a given 8-bit data at PB
and display FFH on PA if it is even parity else 00H on PA if it is odd parity. 05M
Dec-17
.MODEL SMALL
.DATA
PA EQU 0300H
PB EQU 0301H
PC EQU 0302H
CWR EQU 0303H
.CODE
MOV AX, @DATA
MOV DS, AX
MOV DX, CWR
MOV AL, 82H ; PB is input and PA is output
OUT DX, AL
MOV CX, 08H
CLC
XOR BH, BH
MOV DX, PB
IN AL, DX ; Read the data from PB
L1: ROL AL, 01H
JNC SKIP
INC BH ; Count number of ones
SKIP: LOOP L1
MOV AL, BH
MOV BL, 02H
MOV AH, 00H
DIV BL
CMP AH, 00H ; check for remainder
JZ EVEN1 ; if remainder is zero then even number of ones
MOV AL, 00H
JMP DISP

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Microprocessors and Microcontrollers 17CS44 Module-3 Notes

EVEN1: MOV AL, 0FFH


DISP: MOV DX, PA
OUT DX, AL
MOV AH, 4CH
INT 21H
END

With an example, explain how to identify overflow and underflow using flags in a
flag register for performing arithmetic operation on 16-bit number. 06M Dec-17
June-17 and June-18
MOV AX,74F5H
ADD AX,95EBH

74F5H 0111 0100 1111 0101


95EBH 1001 0101 1110 1011
1 0AE0H 1 0000 1010 1110 0000
CF=1 since there is carry beyond d15
AF=1 since there is a carry from d3 to d4
PF=0 since there is an odd number of 1s in the above lower byte
ZF=0 since the result is not zero
SF=0 since d15 of the result is 0, so result is +ve number.
OF = 1 indicates that the result has exceeded the capacity of machine.

Note that storing values that are too low in an integer variable (e.g. attempting to store
-1 in an unsigned integer) is properly referred to as integer overflow, or more broadly
"integer wraparound". The term underflow normally refers to floating point
numbers only.

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