Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Sonali Ray
Electronics & Communication Engg. Dept.
MNNIT Allahabad Meenakshi Sharma
Prayagraj, India Electronics & Communication Engg. Dept.
sonalirai15@gmail.com MNNIT Allahabad
Prayagraj, India
Rohini Srivastava meenakshi.pulastya@gmail.com
Electronics & Communication Engg. Dept.
MNNIT Allahabad Nitin Sahai
Prayagraj, India Biomedical Engineering Department
rohini@mnnit.ac.in North East Hill University (NEHU)
Shillong, India
R.P. Tewari nsahai@nehu.ac.in
Applied Mechanics Dept.
MNNIT Allahabad Dinesh Bhatia
Prayagraj, India Biomedical Engineering Department
rptewari@mnnit.ac.in North East Hill University (NEHU)
Shillong, India
Basant Kumar bhatiadinesh@rediffmail.com
Electronics & Communication Engg. Dept.
MNNIT Allahabad
Prayagraj, India
singhbasant@mnnit.ac.in
I. INTRODUCTION
Fig. 1. AV delay. (a) and (c) Paced AV delay in a dual chamber pacing
The pacemakers are used for the patients who are suffering
mode. (b) and (d) Sensed AV delay in a triggered mode.
from bradycardia; a type of arrhythmia. Bradycardia is the
The heart rate due to physiological contraction of atria and flowchart for the implementation of low delay dual chamber
ventricles, is detected synchronously by the electrodes of the pacemaker is shown in Fig.2. The work process, mentioned in
dual chamber pacemaker. Fig.1 shows the atrio-ventricular the flow chart is repeated for the different ranges of heart beat.
(AV) delay of the dual chamber pacemaker. Fig 1(a) and Fig Algorithm and the flow chart for the proposed work are shown
1(b) show the AV delay which is shorter than the intrinsic below:
conduction. The pacing stimulus is delivered by the pulse At negative edge of Clock A
generator of the pacemaker at the end of the AV delay. Fig 1(c) 1. Sense A → 1
and Fig 1 (d) represent a longer delay and before the end of the
delay, the intrinsic QRS is sensed and ventricular pacing is 2. Check if Beat A = 1
inhibited [1]. It can be seen from the Fig 1, if the delay of the 3. If Yes Pace A =0, else Pace A =1 and Sense
pacemaker increases, one QRS complex may skip to be paced. A →0
Thus, in this paper our motive is to reduce the delay between • At negative edge of Clock V
sensing and pacing of the right chambers of the heart. A person
with 72 beats per minute will have one ECG beat of 0.8 second 4. Sense V → 1
duration. A pacemaker, whether a single chamber or dual 5. Check if Beat V = 1
chamber, waits for 0.8 seconds and then sends a stimuli to the 6. If Yes Pace V =0, else Pace V =1 and Sense
heart if internal pacing is absent. In spite of the delay another V →0
important parameter of the pacemaker is the heart beat range.
This range defines the degree of the blockage of the heart: first • Clock V is delayed version of Clock A
degree, second degree and third degree (complete) heart block. Beat A and Pace A are low power signals compared
Among all of these three degrees of blocking, third degree is to Beat V and Pace
the most life threating blocking as in this none of the electrical
impulse reaches from SA node to AV node [2].
Clock goes from 1 ࡳ› 0
Roopa T.et.al.[3] presented a hardware implementation of
single and dual chamber pacemaker using Verilog on Xilinx
14.1. They have generated ECG on Modelsim and delivered
the delay between sensing and pacing of 3.842 ns for dual Sense=1
chamber pacemaker. But the simulation was performed for the
heart beat ranging from 35-125 bpm at the interval of 20 bpm.
In the proposed work we have taken the heart beat interval of
10 bpm. Omkar et.al. [4] presented a hardware implementation
of pacemaker for different modes, but they delivered much Beat=1 Pace=0
larger delay between sensing and pacing as compare to the
proposed work. The delay is a critical parameter in the design
of the pacemaker, as a larger delay may become one of the
causes for the patient’s death. Thus the algorithm designed in
the proposed work attempts to minimize the time consumption Pace=1
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2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
Fig. 3 shows the simulation result for the heart beat range 30-
40 bpm, the atrial and pacing cycle duration is high for this
range. Fig 3 to Fig 6 show the beat range selected from one of
the (a,b,c,d) wave forms and pacing of atria/ ventricles
according to these beat ranges. The Register-Transfer-Level
(RTL) of the dual chamber demand pacemaker is shown in Fig.
7.
Fig. 3. Sensing and pacing timing diagram of Dual Chamber Pacemaker for
heart beat range from 30-40 bpm
Fig. 4. Sensing and pacing timing diagram of Dual Chamber Pacemaker for
heart beat range from 40-50 bpm
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2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
TABLE II. COMPARISON OF THE PROPOSED WORK WITH THE REPORTED V. FUTURE WORK
WORK [3] IN DEVICE UTILITY
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