La 9868P

A B C D E
1 1
VNKAE
2 Rosetta 10AN/10ANG 2
LA-9868P REV 1.0 Schematic

3 AMD KABINI Quad Core 25W only for UMA 3
AMD KABINI Quad Core 15W for DIS&UMA

2013-03-18 Rev 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/09/27 Deciphered Date 2015/09/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9868P
Date: Thursday, May 16, 2013 Sheet 1 of 42
A B C D E
A B C D E
AMD GPU
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
AMD Sun Pro M2, 64bit with 1GB DDR3(2Gbit) PCIe Gen2 X4
1
5Gbps Single Channel BANK 0, 1, 2, 3 page 10,11
1
AMD Sun Pro M2, 64bit with 2GB DDR3(4Gbit)

1.5V DDRIII 1333/1600 MT/s
page 12-19
AMD FT3 APU APU SMBUS
LVDS/eDP Conn DP0 X4 Jaguar Core USB 2.0 Left TouchScreen Cardreader PCIeMini Card
USB port 0
page 25
USB port 4
page 20
USB port 2
page 28
For BT
page 20
Integrated Yangtze FCH
USB 2.0 USB Right1 USB Right2 Int. Camera
5V 480Mbps USB2.0 port 8 USB2.0 port 9 USB port 3 USB port 1
page 24 page 24 page 20 page 23
HDMI Conn DP1 X4
(1.4b & 3D)
page 21 BGA 769-balls USB Right1 USB Right2
2
USB 3.0 USB3.0 port 0 USB3.0 port 1 2
page 24 page 24
5V 5Gbps
CRT Conn DAC

page 22
SATA port 0 SATA HDD

5V 6Gbps SATA port 0
PCIe Gen1 X1 page 23
PCIeMini Card For WLAN APU SMBUS
2.5bps SATA port 1
PCIe port 2 SATA ODD
page 23 5V 6Gbps SATA port 1
page 23
SPK Conn
page 27
RTL8106E 10/100M PCIe Gen1 X1

2.5bps HD Audio HDA Codec JPIO
PCIe port 1 ALC259
page 25 3.3V 24MHz (HP & MIC)
3 page 26 page 27 3
page 5-9
SPI BUS
3.3V 33HZ
LPC Bus
3.3V 33 MHz
SPI ROM APU SMBus

(4MB) page 7 ENE KB9012
Touch Screen Control/B page 29
page 20 EC SMBus
DC/DC Interface CKT. Touch Pad Int.KBD G-Sensor

page 31 page 30 page 30 page 25
4 4
Power Circuit DC/DC USB2.0&LAN/B

page 32~41 page 25 Security Classification Compal Secret Data Compal Electronics, Inc.
Block Diagram
Power On/Off CKT & Power/B RTC CKT. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.0
page 30 page 9 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-9868P
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.15A +3VL

DESIGN CURRENT 0A +5VL
B+
Ipeak=12A, Imax=8.4A, Iocp min=14A +5VALW
D D
SUSP#
N-CHANNEL DESIGN CURRENT 4A +5VS

TPS22966 ODD_PWR
N-CHANNEL DESIGN CURRENT 2A +5VS_ODD

TPS22966
RT8243A
Ipeak=8A, Imax=5.6A, Iocp min=10A
+3VALW
3VALW_APU_PWREN
P-CHANNEL DESIGN CURRENT 330mA +3VALW_APU

AO-3413
1.8_0.95VALW_PWREN
+3V_LAN
DESIGN CURRENT 2.5A
+1.8VALW
SY8032
C
SUSP# C
N-CHANNEL +1.8VS
TPS22966
VGA_PWRGD
N-CHANNEL +1.8VGS
TPS22966
SUSP#
N-CHANNEL DESIGN CURRENT 4A

+3VS
TPS22966 LCD_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A

AO-3413 +LCD_VDD
DGPU_PWR_EN
DESIGN CURRENT 60mA +3VS_DGPU
P-CHANNEL
AO-3413
DESIGN CURRENT 2A +3V_WLAN

B SYSON B
Ipeak=12A, Imax=8.4A, Iocp min=13.8A +1.5V

RT8207M VGA_PWRGD

+1.5VGS
TPS22966
SUSP#
DESIGN CURRENT 1.5A
+0.75VS
1.8_0.95VALW_PWREN
Ipeak=2.5A, Imax=1.75A, Iocp min=16A +0.95VALW
SY8208D 0.95VS_PWREN#

+0.95VS
FDS6676
VR_ON
Ipeak=15A, Imax=10.5A, Iocp min=30A APU_CORE
A
RT8880A Ipeak=13A, Imax=9.1A, Iocp min=30A APU_CORE_NB
A
GPU_DPRSLPVR
Ipeak=21A, Imax=14.7A, Iocp min=40A VGA_CORE
ISL62881
Power Tree
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
LA-9868P
5 4 3 2 1
A B C D E
Voltage Rails ( O MEANS ON X MEANS OFF )

UMA
+5VS BTO Option Table
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW Function
+0.95VS
+1.8VALW
1 power +1.8VS description 1
plane +0.95VALW
+1.5VS
+VSB explain
+0.75VS
+APU_CORE BTO
+APU_CORE_NB
SIGNAL
STATE SLP_S3# SLP_S5#
State
Full ON HIGH HIGH
S1(Power On Suspend) HIGH HIGH
S3 (Suspend to RAM) LOW HIGH
S4 (Suspend to Disk) LOW HIGH

S0
O O O O O O S5 (Soft OFF) LOW LOW
S1 G3 LOW LOW
2 O O O O O O 2
S3
O O O O O X
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O O X X X
S5 S4/AC & Battery
don't exist
O X X X X X
APU SM Bus Address (SCL0/SDA0)

APU POWER SEQUENCE
Power Device HEX Address G-A +RTC
3 3
+3VS DDR SO-DIMM A A0H 1010 0000 b 3VALW_APU_PWREN
+3VS DDR SO-DIMM B A2H 1010 0010 b
G-B +3VALW_APU
+3VS WLAN
1.8_0.95VALW_PWREN
+1.8VALW
+0.95VALW
SYSON
G-C +1.5V
EC SM Bus1 Address EC SM Bus2 Address SUSP#
G-D +3VS
Power Device HEX Address Power Device HEX Address +1.8VS
+3VL Smart Battery 16H 0001 0110 b +3VS G-Sensor 40H 0100 0000 b +1.5VS
+3VL Charger 12H 0001 0010 b +3VS VGA thermal 82H 1000 0010 b
+0.95VS
+3VS APU thermal 98H 1001 1000 b
VR_ON
G-E +APU_CORE
4 +APU_CORE_NB 4

Notes List
Custom 1.0
LA-9868P
A B C D E
5 4 3 2 1
<10,11> DDR_AB_DQS[0..7]
<10,11> DDR_AB_DQS#[0..7] DDR_AB_D[0..63] <10,11>

UC1A
<10,11> DDR_AB_MA[0..15]
MEMORY
DDR_AB_MA0 AG38 M_ADD0 M_DATA0 B30 DDR_AB_D0
DDR_AB_MA1 W 35 M_ADD1 M_DATA1 A32 DDR_AB_D1
DDR_AB_MA2 W 38 M_ADD2 M_DATA2 B35 DDR_AB_D2
DDR_AB_MA3 W 34 M_ADD3 M_DATA3 A36 DDR_AB_D3
DDR_AB_MA4 U38 M_ADD4 M_DATA4 B29 DDR_AB_D4
DDR_AB_MA5 U37 M_ADD5 M_DATA5 A30 DDR_AB_D5
DDR_AB_MA6 U34 M_ADD6 M_DATA6 A34 DDR_AB_D6
DDR_AB_MA7 R35 M_ADD7 M_DATA7 B34 DDR_AB_D7
D D
DDR_AB_MA8 R38 M_ADD8
DDR_AB_MA9 N38 M_ADD9 M_DATA8 B37 DDR_AB_D8 UC1B
DDR_AB_MA10 AG34 M_ADD10 M_DATA9 A38 DDR_AB_D9 PCIE
DDR_AB_MA11 R34 M_ADD11 M_DATA10 D40 DDR_AB_D10
DDR_AB_MA12 N37 M_ADD12 M_DATA11 D41 DDR_AB_D11
DDR_AB_MA13 AN34 M_ADD13 M_DATA12 B36 DDR_AB_D12 R10 P_GPP_RXP0 P_GPP_TXP0 L2
DDR_AB_MA14 L38 M_ADD14 M_DATA13 A37 DDR_AB_D13 R8 P_GPP_RXN0 P_GPP_TXN0 L1
DDR_AB_MA15 L35 M_ADD15 M_DATA14 B41 DDR_AB_D14
M_DATA15 C40 DDR_AB_D15 R5 P_GPP_RXP1 P_GPP_TXP1 K2 PCIE_ATX_LANRX_P1 CC31 2 0.1U_0402_16V7K
<25> PCIE_LANTX_ARX_P1 PCIE_ATX_C_LANRX_P1 <25>
<10,11> DDR_AB_BS0
DDR_AB_BS0 AJ38 M_BANK0 LAN <25> PCIE_LANTX_ARX_N1
R4 P_GPP_RXN1 P_GPP_TXN1 K1 PCIE_ATX_LANRX_N1 CC41 2 0.1U_0402_16V7K
PCIE_ATX_C_LANRX_N1 <25> LAN
GPP
DDR_AB_BS1 AG35 M_BANK1 M_DATA16 F40 DDR_AB_D16
<10,11> DDR_AB_BS1
DDR_AB_BS2 N34 M_BANK2 M_DATA17 F41 DDR_AB_D17 <23> PCIE_WLANTX_ARX_P2 N5 P_GPP_RXP2 P_GPP_TXP2 J2 PCIE_ATX_WLANRX_P2 CC11 2 0.1U_0402_16V7K
<10,11> DDR_AB_BS2 PCIE_ATX_C_WLANRX_P2 <23>
M_DATA18 K40 DDR_AB_D18 WLAN <23> PCIE_WLANTX_ARX_N2
N4 P_GPP_RXN2 P_GPP_TXN2 J1 PCIE_ATX_WLANRX_N2 CC21 2 0.1U_0402_16V7K WLAN
<10,11> DDR_AB_DM[0..7] PCIE_ATX_C_WLANRX_N2 <23>
DDR_AB_DM0 B32 M_DM0 M_DATA19 K41 DDR_AB_D19
DDR_AB_DM1 B38 M_DM1 M_DATA20 E40 DDR_AB_D20 N10 P_GPP_RXP3 P_GPP_TXP3 H2
DDR_AB_DM2 G40 M_DM2 M_DATA21 E41 DDR_AB_D21 N8 P_GPP_RXN3 P_GPP_TXN3 H1
DDR_AB_DM3 N41 M_DM3 M_DATA22 J40 DDR_AB_D22
DDR_AB_DM4 AG40 M_DM4 M_DATA23 J41 DDR_AB_D23 +0.95VS_APU_GFX
1 2 P_TX_ZVDD W 8 P_TX_ZVDD_095 P_RX_ZVDD_095 W7 P_RX_ZVDD 2 1 +0.95VS_APU_GFX
DDR_AB_DM5 AN41 M_DM5 RC1 1.69K_0402_1% RC2 1K_0402_1%
DDR_AB_DM6 AY40 M_DM6 M_DATA24 M41 DDR_AB_D24
DDR_AB_DM7 AY34 M_DM7 M_DATA25 N40 DDR_AB_D25
Y40 M_DM8 M_DATA26 T41 DDR_AB_D26 L5 P_GFX_RXP0 P_GFX_TXP0 G2 PCIE_ATX_GRX_P0 CC5 1 2 VGA@ 0.1U_0402_16V7K
<12> PCIE_GTX_C_ARX_P0 PCIE_ATX_C_GRX_P0 <12>
2 VGA@
GRAPHICS
M_DATA27 U40 DDR_AB_D27 L4 P_GFX_RXN0 P_GFX_TXN0 G1 PCIE_ATX_GRX_N0 CC6 1 0.1U_0402_16V7K
<12> PCIE_GTX_C_ARX_N0 PCIE_ATX_C_GRX_N0 <12>
DDR_AB_DQS0 B33 M_DQS_H0 M_DATA28 L40 DDR_AB_D28
DDR_AB_DQS#0 A33 M_DQS_L0 M_DATA29 M40 DDR_AB_D29 J5 P_GFX_RXP1 P_GFX_TXP1 F2 PCIE_ATX_GRX_P1 CC7 1 2 VGA@ 0.1U_0402_16V7K
DDR_AB_DQS1 B40 M_DQS_H1 M_DATA30 R40 DDR_AB_D30 J4 P_GFX_RXN1 P_GFX_TXN1 F1 PCIE_ATX_GRX_N1 CC8 1 2 VGA@ 0.1U_0402_16V7K
MEMORY
DDR_AB_DQS#1 A40 T40 DDR_AB_D31
DDR_AB_DQS2 H41
M_DQS_L1 M_DATA31
G5 E2 PCIE_ATX_GRX_P2 CC9 1 2 VGA@ 0.1U_0402_16V7K VGA
DDR_AB_DQS#2 H40
M_DQS_H2
AF40 DDR_AB_D32
VGA<12> PCIE_GTX_C_ARX_P2
G4
P_GFX_RXP2 P_GFX_TXP2
E1 PCIE_ATX_GRX_N2 CC10 1 2 VGA@ 0.1U_0402_16V7K PCIE_ATX_C_GRX_P2 <12>
M_DQS_L2 M_DATA32 P_GFX_RXN2 P_GFX_TXN2
C DDR_AB_DQS3 P41 M_DQS_H3 M_DATA33 AF41 DDR_AB_D33 C
DDR_AB_DQS#3 P40 M_DQS_L3 M_DATA34 AK40 DDR_AB_D34 D7 P_GFX_RXP3 P_GFX_TXP3 D2 PCIE_ATX_GRX_P3 CC11 1 2 VGA@ 0.1U_0402_16V7K
DDR_AB_DQS4 AH41 M_DQS_H4 M_DATA35 AK41 DDR_AB_D35 E7 P_GFX_RXN3 P_GFX_TXN3 D1 PCIE_ATX_GRX_N3 CC12 1 2 VGA@ 0.1U_0402_16V7K
DDR_AB_DQS#4 AH40 M_DQS_L4 M_DATA36 AE40 DDR_AB_D36
DDR_AB_DQS5 AP41 M_DQS_H5 M_DATA37 AE41 DDR_AB_D37
DDR_AB_DQS#5 AP40 M_DQS_L5 M_DATA38 AJ40 DDR_AB_D38
FT3 REV 0.51
DDR_AB_DQS6 BA40 M_DQS_H6 M_DATA39 AJ41 DDR_AB_D39
DDR_AB_DQS#6 AY41 M_DQS_L6 FT3_BGA769 @
DDR_AB_DQS7 AY33 M_DQS_H7 M_DATA40 AM41 DDR_AB_D40
DDR_AB_DQS#7 BA34 M_DQS_L7 M_DATA41 AN40 DDR_AB_D41
AA40 M_DQS_H8 M_DATA42 AT41 DDR_AB_D42
Y41 M_DQS_L8 M_DATA43 AU40 DDR_AB_D43
M_DATA44 AL40 DDR_AB_D44
DDR_A_CLK0 AC35 M_CLK_H0 M_DATA45 AM40 DDR_AB_D45
<10> DDR_A_CLK0
DDR_A_CLK0# AC34 M_CLK_L0 M_DATA46 AR40 DDR_AB_D46
<10> DDR_A_CLK0#
DDR_A_CLK1 AA34 M_CLK_H1 M_DATA47 AT40 DDR_AB_D47
<10> DDR_A_CLK1
DDR_A_CLK1# AA32 M_CLK_L1
<10> DDR_A_CLK1#
DDR_B_CLK0 AE38 M_CLK_H2 M_DATA48 AV41 DDR_AB_D48
<11> DDR_B_CLK0
DDR_B_CLK0# AE37 M_CLK_L2 M_DATA49 AW 40DDR_AB_D49
<11> DDR_B_CLK0#
DDR_B_CLK1 AA37 M_CLK_H3 M_DATA50 BA38 DDR_AB_D50
<11> DDR_B_CLK1
DDR_B_CLK1# AA38 M_CLK_L3 M_DATA51 AY37 DDR_AB_D51
<11> DDR_B_CLK1#
M_DATA52 AU41 DDR_AB_D52
MEM_MAB_RST# G38 M_RESET_L M_DATA53 AV40 DDR_AB_D53
<10,11> MEM_MAB_RST#
MEM_MAB_EVENT# AE34 M_EVENT_L M_DATA54 AY39 DDR_AB_D54
<10,11> MEM_MAB_EVENT#
M_DATA55 AY38 DDR_AB_D55
DDR_A_CKE0 L34 M0_CKE0
<10> DDR_A_CKE0
DDR_A_CKE1 J38 M0_CKE1 M_DATA56 BA36 DDR_AB_D56
<10> DDR_A_CKE1
DDR_B_CKE0 J37 M1_CKE0 M_DATA57 AY35 DDR_AB_D57
<11> DDR_B_CKE0
DDR_B_CKE1 J34 M1_CKE1 M_DATA58 BA32 DDR_AB_D58
<11> DDR_B_CKE1
M_DATA59 AY31 DDR_AB_D59
B B
DDR_A_ODT0 AN38 M0_ODT0 M_DATA60 BA37 DDR_AB_D60
<10> DDR_A_ODT0
DDR_A_ODT1 AU38 M0_ODT1 M_DATA61 AY36 DDR_AB_D61
<10> DDR_A_ODT1
DDR_B_ODT0 AN37 M1_ODT0 M_DATA62 BA33 DDR_AB_D62
<11> DDR_B_ODT0
DDR_B_ODT1 AR37 M1_ODT1 M_DATA63 AY32 DDR_AB_D63
<11> DDR_B_ODT1
DDR_A_SCS0# AJ34 M0_CS_L0 M_CHECK0 V41
<10>
<10>
<11>
DDR_A_SCS0#
DDR_A_SCS1#
DDR_B_SCS0#
DDR_A_SCS1#
DDR_B_SCS0#
AR38
AL38
M0_CS_L1
M1_CS_L0
M_CHECK1
M_CHECK2
W 40
AB40 +5VS FAN Control Circuit
DDR_B_SCS1# AN35 M1_CS_L1 M_CHECK3 AC40 +3VS
<11> DDR_B_SCS1#
M_CHECK4 U41
DDR_AB_RAS# AJ37 M_RAS_L M_CHECK5 V40
<10,11> DDR_AB_RAS#
1
<10,11> DDR_AB_CAS#
DDR_AB_CAS# AL34 M_CAS_L M_CHECK6 AA41 1A
DDR_AB_WE# AL35 M_WE_L M_CHECK7 AB41 1 @ 2 +FAN1 R1 JFAN @
<10,11> DDR_AB_WE# R2 0_0603_5% 10K_0402_5% 6
+MEM_VREF AD40 5 GND
M_VREF
AC38 AD41 M_ZVDDIO 1 2 4 GND
M_VREFDQ M_ZVDDIO_MEM_S
+1.5V 4
2
39.2_0402_1% RC4 3
1 2 ESD@ MEM_MAB_RST# FT3 REV 0.51 <29> FANPWM 3
remove from CRB_ver0C 2
CC94 180P_0402_50V8J <29> FAN_SPEED1 2
Check List 1.02 FT3_BGA769 @ 1 +FAN1 1
1
close to APU C1
0.01U_0402_25V7K ACES_50273-0040N-001
@
2
+1.5V MEMORY Reference Voltage (Cap follower checklist 1.02) EVENT# pull high
1
1
2
D1 C3
RC6 +1.5V
1K_0402_1% BAS16_SOT23-3 2
2
A 15mil 10U_0603_6.3V6M A
1
+MEM_VREF RC7 1 2 1K_0402_5% MEM_MAB_EVENT#

2
2 2
RC8 CC18
1K_0402_1% CC17
1U_0402_6.3V6K 0.1U_0402_16V7K Security Classification Compal Secret Data
1 1 2012/09/27 2015/09/27 Title
Issued Date Deciphered Date
1
FT3 DISP/MISC/HDT
Close to APU AD40 1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
EDP_LCD_TXOUT0+_R 1 2 0.1U_0402_16V7K EDP_LCD_TXOUT2+

CC109 EDP@
EDP_LCD_TXOUT0-_R 1 2 0.1U_0402_16V7K EDP_LCD_TXOUT2-
CC110 EDP@
LCD_ENBKL : APU to EC to LCD +3VS
UC1C LVDS_CLK&LVDS_DATA layout follow EDP AUX route 85 ohm
DISPLAY/SVI2/JTAG/TEST
A9 TDP1_TXP0 DP_150_ZVSS B16 DP_150_ZVSS RC13 1 2 150_0402_1%
<21> APU_HDMI_TX2+
B9 TDP1_TXN0 DP_2K_ZVSS A21 DP_2K_ZVSS RC9 1 2 2K_0402_1% EDP_LVDS_CLK_R RC14 1 LVDS@ 2 4.7K_0402_5%
<21> APU_HDMI_TX2-
D DP_BLON B17 LCD_ENBKL D
LCD_ENBKL <20,29>
A10 TDP1_TXP1 DP_DIGON A17 LCD_ENVDD EDP/LVDS EDP_LVDS_DATA_R RC15 1 LVDS@ 2 4.7K_0402_5%
<21> APU_HDMI_TX1+ LCD_ENVDD <20>
B10 TDP1_TXN1 DP_VARY_BL A18 LCD_INT_PWM
<21> APU_HDMI_TX1- LCD_INT_PWM <20> HDMI DDC PU RES move
HDMI <21> APU_HDMI_TX0+
A11 TDP1_TXP2 to HDMI page
B11 TDP1_TXN2 TDP1_AUXP D17 APU_HDMI_CLK
<21> APU_HDMI_TX0- APU_HDMI_CLK <21> APU_CRT_DATA RC17 2 1 4.7K_0402_5%
TDP1_AUXN E17 APU_HDMI_DATA
APU_HDMI_DATA <21>
A12 TDP1_TXP3
HDMI
<21> APU_HDMI_CLK+ APU_CRT_CLK RC12 2 1 4.7K_0402_5%
DISPLAY
B12 TDP1_TXN3 TDP1_HPD H19
<21> APU_HDMI_CLK- HDMI_HPD <21,8>
EDP use 2 Lane for FHD RC75 1 LVDS@ 2 0_0402_5% EDP_LCD_TXOUT2+ A4 LTDP0_TXP0 LTDP0_AUXP D15 EDP_LVDS_CLK_R CC1011 LVDS@ 2 0_0402_5% APU_CRT_HSYNC RC18 1 2 1K_0402_5%
<20> EDP_LCD_TXOUT2+_R EDP_LVDS_CLK <20>
<20> EDP_LCD_TXOUT2-_R RC76 1 LVDS@ 2 0_0402_5% EDP_LCD_TXOUT2- B4 LTDP0_TXN0 LTDP0_AUXN E15 EDP_LVDS_DATA_RCC1031 LVDS@ 2 0_0402_5% EDP_LVDS_HPD RC45 2 @ 1 100K_0402_5%
EDP_LVDS_DATA <20>
EDP Cap co-lay
<20> EDP_LCD_TXOUT1+_R CC107 1 LVDS@ 2 0_0402_5% EDP_LCD_TXOUT1+ A5 LTDP0_TXP1 LTDP0_HPD H17 EDP_LVDS_HPD
EDP_LVDS_HPD <20>
<20> EDP_LCD_TXOUT1-_R CC108 1 LVDS@ 2 0_0402_5% EDP_LCD_TXOUT1- B5 LTDP0_TXN1
DAC_RED B14 APU_CRT_R
APU_CRT_R <22>
EDP/LVDS
EDP/LVDS <20> EDP_LCD_TXOUT0+_R RC77 1 LVDS@ 2 0_0402_5% EDP_LCD_TXOUT0+ A6 LTDP0_TXP2 EDP Cap co-lay
RC78 1 LVDS@ 2 0_0402_5% EDP_LCD_TXOUT0- B6 LTDP0_TXN2 DAC_GREEN A14 APU_CRT_G
CC107 CC108 <20> EDP_LCD_TXOUT0-_R APU_CRT_G <22> CC101 CC103
EDP@ EDP@ LCD_TXCLK+ A7 B15 APU_CRT_B EDP@ EDP@
LTDP0_TXP3 DAC_BLUE
0.1U_0402_16V7K 0.1U_0402_16V7K <20> LCD_TXCLK+ APU_CRT_B <22> 0.1U_0402_16V7K 0.1U_0402_16V7K
LCD_TXCLK- B7 LTDP0_TXN3
<20> LCD_TXCLK-
G19 APU_CRT_HSYNC
CRT
DAC_HSYNC
APU_CRT_HSYNC <22> EDP_LVDS_HPD RC44 2 EDP@ 1 100K_0402_5%
SVT,SVC,SVD, APU_PWRGD is 1.8V Output K15 DISP_CLKIN_H DAC_VSYNC E19
APU_CRT_VSYNC <22>
PROCHOT is 3.3V Input H15 DISP_CLKIN_L LCD_ENBKL RC19 2 1 100K_0402_5%
DAC_SCL D19 APU_CRT_CLK
APU_CRT_CLK <22>
G31 SVT DAC_SDA D21 APU_CRT_DATA LCD_INT_PWM RC20 2 1 100K_0402_5%
<38> APU_SVT APU_CRT_DATA <22>
D27 SVC
<38> APU_SVC
E29 SVD DAC_ZVSS A16 DAC_ZVSS RC21 1 2 499_0402_1% APU_CRT_R RC22 1 2 150_0402_1%
<38> APU_SVD
+3VS
C B22 SIC THERMDA H27 TEST4 T1 APU_CRT_G RC24 1 2 150_0402_1% C
<13,25,29> EC_SMB_CK2
B21 SID THERMDC H29 TEST5 T2
<13,25,29> EC_SMB_DA2
MISC
DIECRACKMON D25 APU_CRT_B RC27 1 2 150_0402_1%
RC26 2 1 1K_0402_5% APU_PROCHOT# APU_RST# B20 A27 TEST14 T3
APU_RST_L BP0
A20 LDT_RST_L BP1 B27 TEST15 T4 APU_CRT_HSYNC RC30 1 @ 2 1K_0402_5%
BP2 A26 TEST16 T5
+1.8VS
APU_PWRGD B19 APU_PWROK BP3 B26 TEST17 T6
<38> APU_PWRGD
A19 LDT_PWROK PLLTEST1 B28 TEST18 T34
RC32 1 2 300_0402_5% APU_RST# PLLTEST0 A28 TEST19 T35
<29,38> APU_PROCHOT# APU_PROCHOT# A22 PROCHOT_L BYPASSCLK_H B24 TEST25_H route TEST25_H/L AND TEST28_H/L differentially
RC34 1 2 300_0402_5% APU_PWRGD APU_ALERT# B18 ALERT_L BYPASSCLK_L A24 TEST25_L
PLLCHRZ_H AV35 TEST28_H T7 +1.8VS
APU_TDI D29 TDI PLLCHRZ_L AU35 TEST28_L T8
+1.8VS T28 APU_TDO D31 TDO M_TEST E33 TEST31 T9 NOTE: DP_STEREOSYNC & APU_HSYNC PU FOR
TEST
APU_TCK D35 TCK INTERNAL(HDMI enable), DP_STEREOSYNC & TEST25_L RC35 1 2 510_0402_1%
RPC2 APU_TMS D33 TMS FREE_2 A29
APU_TRST# G27 GIO_TSTDTM0_SERIALCLKH21 TEST36 APU_HSYNC PD FOR CUSTOMER(HDMI disable) TEST36 RC37 1 @ 2 1K_0402_5%
1 8 APU_TDI TRST_L
2 7 APU_TCK T32 APU_DBRDY B25 DBRDY GIO_TSTDTM0_CLKINIT H25 TEST37 TEST37 RC39 1 @ 2 1K_0402_5%
3 6 APU_TMS T37 APU_DBREQ# A25 DBREQ_L
4 5 APU_TRST# USB_ATEST0 AJ10 TEST42 T12 DP_STEREOSYNC RC36 1 @ 2 1K_0402_5%
D23 VDDCR_NB_SENSE USB_ATEST1 AJ8 TEST43 T13 TEST36 RC41 1 @ 2 1K_0402_5%
<38> APU_VDDNB_SEN_H
1K_8P4R_5% G23 VDDCR_CPU_SENSE M_ANALOGIN R32 TEST39 T14
<38> APU_VDD_SEN_H TEST37 RC46 1 @ 2 1K_0402_5%
T15 VDDMEM_SENSE E25 VDDIO_MEM_S_SENSE M_ANALOGOUT N32 TEST40 T16
2 1 APU_DBREQ# E23 AP29 TEST41 T17
RC28 <38> APU_VDD_SEN_L VSS_SENSE TMON_CAL TEST25_H RC43 1 2 510_0402_1%
MISC
1K_0402_5%
T18 VDD095_FB_H AV33 VDD_095_FB_H HDMI_EN/DP_STEREOSYNCE21 DP_STEREOSYNC
T19 VDD095_FB_L AU33 VDD_095_FB_L
DP_STEREOSYNC
Used to align shutter glasses with the interleaved video frame +3VS
B B
1 2 ESD@ APU_RST# RPC4
CC99 1000P_0402_50V7K FT3 REV 0.51
APU_ALERT# 1 8
1 2 ESD@ APU_PWRGD FT3_BGA769 @ DP_STEREOSYNC 2 7
CC93 180P_0402_50V8J +1.8VS
TEST19 3 6
TEST18 4 5
close to APU 1K_8P4R_5%
DC1
2 1 APU_PROCHOT#
@ESD@
SCV00001K00 close to APU
A A
Security Classification Compal Secret Data

FT3 DISP/MISC/HDT
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
UC1E
CLK/SATA/USB/SPI/LPC
BA14 SATA_TX0P W4
USBCLK/14M_25M_48M_OSC
<23> SATA_ATX_DRX_P0
AY14
SATA HDD <23> SATA_ATX_DRX_N0
BA16
SATA_TX0N
SATA_RX0N
USB_ZVSS AG4 USB_ZVSS RC57 1 2 11.8K_0402_1%
<23> SATA_DTX_C_ARX_N0
AY16 AL4
<23> SATA_DTX_C_ARX_P0
AY19
SATA_RX0P
SATA_TX1P
USB_HSD0P
USB_HSD0N AL5
USB20_P0 <24>
USB20_N0 <24> USB2.0-Left1 (Debug Port)
<23> SATA_ATX_DRX_P1
BA19 AJ4
SATA ODD <23> SATA_ATX_DRX_N1
AY17
SATA_TX1N
SATA_RX1N
USB_HSD1P
USB_HSD1N AJ5
USB20_P1 <23>
USB20_N1 <23> WLAN (BT)
<23> SATA_DTX_C_ARX_N1
SATA
D D
BA17 AG7
<23> SATA_DTX_C_ARX_P1
RC58 2 1 1K_0402_1%SATA_ZVSS AR19
SATA_RX1P
SATA_ZVSS
USB_HSD2P
USB_HSD2N AG8
USB20_P2 <28>
USB20_N2 <28> Cardreader
RC59 2 1 1K_0402_1%SATA_ZVSS_095 AP19 AG1
+0.95VS SATA_ZVDD_095 USB_HSD3P
USB_HSD3N AG2
USB20_P3 <20>
USB20_N3 <20> Int. Camera
T20 SATA_ACT BA30 SATA_ACT_L/GPIO67 USB_HSD4P AF1
USB20_P4 <20>
AF2
AY12 SATA_X1
USB_HSD4N
USB_HSD5P AE1
USB20_N4 <20>
Touch Screen
USB_HSD5N AE2
USB
BA12 SATA_X2 USB_HSD6P AD1
USB_HSD6N AD2
U4 AC1
VGA <12> CLK_PCIE_VGA
<12> CLK_PCIE_VGA# U5
GFX_CLKP
GFX_CLKN
USB_HSD7P
USB_HSD7N AC2
AC8 AB1
USB2.0-Right1
GPP_CLK0P USB_HSD8P
USB20_P8 <24>
AC10 GPP_CLK0N USB_HSD8N AB2
USB20_N8 <24>
AE4 AA1
LAN <25> CLK_LAN
<25> CLK_LAN#
AE5
GPP_CLK1P
GPP_CLK1N
USB_HSD9P
USB_HSD9N AA2
USB20_P9 <24>
USB20_N9 <24> USB2.0-Right2
CLK
AC4 AE10 USBSS_ZVSS RC60 1 2 1K_0402_1%
WLAN <23> CLK_WLAN
<23> CLK_WLAN#
AC5
GPP_CLK2P
GPP_CLK2N
USB_SS_ZVSS
AE8
USB_SS_ZVDD_095_USB3_DUAL USBSS_ZVDD RC61 1 2 1K_0402_1% +0.95VALW
AA5 GPP_CLK3P USB_SS_0TXP T2
USB30_TX0P <24>
AA4 GPP_CLK3N USB_SS_0TXN T1
USB30_TX0N <24>
C
AP13 X14M_25M_48M_OSC USB_SS_0RXP V2
USB30_RX0P <24>
USB3.0-Right1 C
USB_SS_0RXN V1
USB30_RX0N <24>
48M_X1 N2 X48M_X1
USB_SS_1TXP R1
USB30_TX1P <24>
USB_SS_1TXN R2
USB30_TX1N <24>
48M_X2 N1 X48M_X2 USB_SS_1RXP W1
USB30_RX1P <24>
USB3.0-Right2
USB_SS_1RXN W 2
USB30_RX1N <24>
EMI@
RC62 1 2 22_0402_5%LPC_CLK0 AY2 LPCCLK0
<29,8> CLK_PCI_EC
RC63 1 2 0_0402_5% LPC_CLK1 AW 2 LPCCLK1 SPI_CLK/GPIO162 AU7 APU_SPI_CLK 1 @ 2 APU_SPI_CLK_R
<8> CLK_PCI_DDR 0_0402_5%
@EMI@ SPI_CS1_L/GPIO165 AW 9 APU_SPI_CS1# RC130
LPC
SPI
1
AT2 LAD0 SPI_CS2_L/GPIO166 AR4 APU_SPI_CS2# T21
<29> LPC_AD0
AT1 LAD1 SPI_DO/GPIO163 AR11 APU_SPI_MOSI RC10
<29> LPC_AD1
EC <29> LPC_AD2
<29> LPC_AD3
AR2
AR1
LAD2
LAD3
SPI_DI/GPIO164 AR7
SPI_HOLD_L/GEVENT9_LAU11
APU_SPI_MISO 10_0402_5%
@EMI@
AP2 LFRAME_L SPI_WP_L/GPIO161 AU9 APU_SPI_WP# T22
<29,8> LPC_FRAME#
2
AP1 LDRQ0_L
2
AV29 SERIRQ/GPIO48 CC13
<29> SERIRQ
AP25 LPC_CLKRUN_L 10P_0402_50V8J
AV2 LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L @EMI@
1
FT3 REV 0.51
FT3_BGA769 @
B B
48KMHz CRYSTAL
48M_X2
SPI ROM
48M_X1 RC1011 885@ 2 33_0402_5%
RC64 1M_0402_5% <29> EC_SPIDO 885@
<29> EC_SPIDI RC1021 2 33_0402_5%
RC1211 885@ 2 33_0402_5%
<29> EC_SPICLK 885@
<29> EC_SPICS# RC1241 2 33_0402_5%
2 1
2 1 4M Byte
UC5
APU_SPI_MOSI 5 2 APU_SPI_MISO
3 4 SI SO
3 4 APU_SPI_CLK_R 6
SCLK
YC1 RC66 1 2 10K_0402_5% APU_SPI_CS1# 1
48MHZ_8PF_X3S048000D81H-W CS
1 1 +3VALW_APU 7
HOLD
CC22 CC23 3
4.7P_0402_50V8J WP
4.7P_0402_50V8J Socket: SP07000F500/SP07000H900
2 2 Please place UC5 close to UC1 APU, 8 4
VCC GND
2
MX25L3205DM2I-12G SO8
4MB ROM P/N: CC25
A
SA00004LI00 1
0.1U_0402_16V4Z A
SW said ROM can change to 4MB

FT3-SATA/CLK/USB/SPI/LPC
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
Follow check list & ORB_0C +1.8VALW PCIE_RST# is for PCIE devices on APU
design 10 ms RC delay circuit 1 2 ESD@ SYS_PWRGD
on +1.8-V S5 power rail. UC1D APU_PCIE_RST#_R RC68 1 2 33_0402_5%
CC97 180P_0402_50V8J APU_PCIE_RST# <12,23,25>
47K_0402_5%
ACPI/SD/AZ/GPIO/RTC/MISC RC72
RC71 2
2
LPC_RST#_R AY4 LPC_RST_L SD_PWR_CTRL BA23 1 @
close to APU APU_PCIE_RST#_R AY9 PCIE_RST_L SD_CLK/GPIO73 AY22 CC28
100K_0402_5%
RSMRST# AY5 AY23 150P_0402_50V8J
RSMRST_L SD_CMD/GPIO74
AY20 2
DC2 SD_CD/GPIO75
1
1 2 RSMRST# <29> PBTN_OUT# BA8 PWR_BTN_L SD_WP/GPIO76 BA20
<29> EC_RSMRST#
SD
Sequence
<29> SYS_PWRGD SYS_PWRGD AM19 PWR_GOOD
CH751H-40PT_SOD323-2 T23 AY7 SYS_RESET_L/GEVENT19_L SD_DATA0/GPIO77 BA22
AW 11 AY21 A_RST# is for LPC devices
CC29
APU_PCIE_WAKE#
1U_0402_6.3V6K
2 WAKE_L/GEVENT8_L SD_DATA1/GPIO78
<25> APU_PCIE_WAKE#
SD_DATA2/GPIO79 AY24
D LPC_RST#_R RC73 1 2 33_0402_5% D
<29> SLP_S3# SLP_S3# AY3 SLP_S3_L SD_DATA3/GPIO80 BA24 LPC_RST# <29>
SLP_S5# BA5
2
AMD G3-S5 clock issue SLP_S5_L
1 <29> SLP_S5# 1
SD_LED/GPIO45 AY25
CC27 RC74
AU13 TEST0
100K_0402_5%
T25 TEST1/TMS AY10 TEST1/TMS SCL0/GPIO43 AU25 APU_SCLK0
APU_SCLK0 <10,11,23> 150P_0402_50V8J @
TEST0/2 AY6 TEST2 SDA0/GPIO47 AV25 APU_SDATA0 2
APU_SDATA0 <10,11,23>
1
+1.8VALW
<29> KB_RST#
AR23 KBRST_L SCL1/GPIO227 AY11 APU_SCLK1
APU_SCLK1 <30>
RC127 1 2 10K_0402_5% SYS_PWRGD <29> GATEA20
AR31 GA20IN/GEVENT0_L SDA1/GPIO228 BA11 APU_SDATA1
APU_SDATA1 <30>
<29> EC_SCI#
AN5 LPC_PME_L/GEVENT3_L
<29> EC_SMI# AL7 LPC_SMI_L/GEVENT23_L GPIO49 AP27 APU SMBus0 for S0 , SMBus1 for S5
GPIO50 AY28 PW_CLEAR# 1 2 If APU_SMBUS no use pull high 10K
+3VALW_APU SLP_S3#, SLP_S5# PU reserve GPIO51 BA28 JPW @
AP15 AC_PRES/IR_RX0/GEVENT16_L GPIO55 AV23 PANEL_SEL
IR
RC128 1 2 2.2K_0402_5% SLP_S3# AV13 AP21 RPC1
@ <24> SLP_CHG_CB0 IR_TX0/GEVENT21_L GPIO57
ODD_PWR <31>
RC129 1 @ 2 2.2K_0402_5% SLP_S5# BA9 IR_TX1/GEVENT6_L GPIO58 BA26 Board_ID0 APU_SDATA0 1 8
<24> SLP_CHG_CB1 BA10 IR_RX1/GEVENT20_L GPIO59 AV19 Board_ID1 APU_SCLK0 2 7 +3VS
<25> LAN_EN
AV15 IR_LED_L/LLB_L/GPIO184 GPIO64 AY27 PXS_RST# APU_SCLK1 3 6
PXS_RST# <12>
GPIO
SPKR/GPIO66 BA27 APU_SDATA1 4 5 +3VALW_APU
APU_SPKR <26>
<23> CLKREQ_WLAN#
AU29 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 GPIO68 AU21 PXS_PWREN
+3VALW_APU PXS_PWREN <14,39>
AW 29 CLK_REQ1_L/GPIO61 GPIO69 AY26 TOUCH_SEL 2.2K_8P4R_5%
RPC5 <27> SPK_DET AR27 CLK_REQ2_L/GPIO62 GPIO70 AV21 SM_DET +3VS
1 8 USB_OC#0 <25> CLKREQ_LAN#
AV27 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 GPIO71 AM21
GPIO174 PD CHK1.03
MSIC
2 7 USB_OC#2 <13> CLKREQ_PEG#
AY29 CLK_REQG_L/GPIO65/OSCIN GPIO174 BA3 APU_GPIO174
SM_DET RC1351 269@ 2 10K_0402_5%
3 6 USB_CHG_OC#
4 5 ODD_PLUGIN# USB_OC#0 AY8 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L GEVENT2_L AV17 GEVENT2 Board_ID0 RC1371 UMA@ 2 10K_0402_5%
<24,29> USB_OC#0
USB_CHG_OC# AW 1 USB_OC1_L/TDI/GEVENT13_L GEVENT4_L BA4 Board_ID1 RC1381 UMA@ 2 10K_0402_5%
<24,29> USB_CHG_OC#
100K_8P4R_5% <23> ODD_PLUGIN# ODD_PLUGIN# AV1 USB_OC2_L/TCK/GEVENT14_L GEVENT7_L AR15
<24,29> USB_OC#2 USB_OC#2 AY1 USB_OC3_L/TDO/GEVENT15_L GEVENT10_L AP17 HDMI_HPD_N
C GEVENT11_L AP11 C
RC92 1
EMI@
2 33_0402_5% HDA_BITCLK AN2 GEVENT17_L AN8 ODD_DA#_APU SW request
10K_0402_5% <26> AZ_BITCLK_HD AZ_BITCLK
PXS_RST# RC1331 VGA@ 2 1K_0402_5%
RC23 <26> AZ_SDOUT_HD RC93 1 2 33_0402_5% HDA_SDOUT AN1 AZ_SDOUT BLINK/GEVENT18_L AU17
2 1 APU_PCIE_WAKE# SM_DET 1 2
RC25 <26> AZ_SDIN0_HD AZ_SDIN0_HD AK2 AZ_SDIN0/GPIO167 GEVENT22_L BA6 EC_LID_OUT#
2 1 APU_GPIO174 EC_LID_OUT# <29> RC136 259@ 1K_0402_5%
AK1 AZ_SDIN1/GPIO168
HDA
10K_0402_5% AM1 AZ_SDIN2/GPIO169 GENINT1_L/GPIO32 BA29
AL2 AZ_SDIN3/GPIO170 GENINT2_L/GPIO33 AP23
VGA_PWRGD <15,39> +3VALW_APU
<26> AZ_SYNC_HD RC98 1 2 33_0402_5% HDA_SYNC AM2 AZ_SYNC
EMI@ <26> AZ_RST_HD# RC1001 2 33_0402_5% HDA_RST# AL1 AZ_RST_L FANOUT0/GPIO52 AV31
CC15 1 2 10P_0402_50V8J AZ_BITCLK_HD FANIN0/GPIO56 AU31 EC_LID_OUT# RC94 1 2 10K_0402_5%
RC96 1 @ 2 10K_0402_5% HDA_BITCLK 32K_X1 AJ2 X32K_X1 +3VS

RC97 1 @ 2 10K_0402_5% AZ_SDIN0_HD
CC30 1 2 10P_0402_50V8J 32K_X1

AJ1
RTC CLK RTCCLK AV11 RTC_CLK
RTC_CLK <29>
YC2 32K_X2
2
X32K_X2
FT3 REV 0.51
G
4 3 QC2
1
FT3_BGA769 @ 2N7002KW_SOT323-3
RC104
20M_0402_5% HDMI_HPD_N 1 3
HDMI_HPD <21,6>
1 2
S
8P_0402_50V8D VRAM_SEL
2
CC31 1 2 32.768KHZ_7PF_Q13MC1461000100 32K_X2 RPC6 Control by X76

PXS_PWREN 1 8 +3VS
H L PXS_EN# 2 7 +3VALW_APU
Board_ID0 3 6 +3VS +3VS
eDP LVDS Board_ID1 4 5
STRAP PINS PANEL_SEL
panel panel
2
2
10K_8P4R_5% RC95
VGA@ RC125
B 10K_0402_5% 10K_0402_5% B
CLK_PCI_EC CLK_PCI_DDR LPC_FRAME# GEVENT2 RTC_CLK
EDP@ TOUCH@
H L
TOUCH_SEL
21
PANEL_SEL
21
BOOT FAIL TIMER CLKGEN Non Touch
PULL SPI ROM 1.8V SPI ROM NORMAL POWR Touch
TOUCH_SEL Panel RC99
HIGH ENABLE UP/RESET TIMING Panel (turn off EHCI) Place at GPU RC126
1K_0402_5%
10K_0402_5%
DEFAULT DEFAULT DEFAULT For DIS LVDS@
NTOUCH@
QC3A
1
1
2N7002KDWH_SOT363-6
BOOT FAIL TIMER CLKGEN H L
LPC ROM 3.3V SPI ROM FAST POWER PXS_PWREN 6 1
PULL DISABLED DISABLED VGA@
UP/RESET TIMING Sleep& QC3B
LOW SM_EN PlayMusic ALC259
FOR SIMULATION 2N7002KDWH_SOT363-6
DEFAULT DEFAULT (ALC269) ODD DA#
2
4 3 PXS_EN# +3VS +3VS
VGA@
+3VALW_APU EC_PXCONTROL
2
EC_PXCONTROL <29>
5
Board Conf. Board_ID0 Board_ID1 RC105
PX5 0 0 10K_0402_5%
Reserved 0 1
1
1
1
1
2
DIS 1 0
1
@ @
RC107 RC108 RC106 RC109 RC110 UMA 1 1 ODD_DA#_APU 6 1
10K_0402_5% 10K_0402_5% 10K_0402_5% PXS_RST# 1 2 @ESD@ ODD_DA# <23>
10K_0402_5% 10K_0402_5%
CC48 180P_0402_50V8J
2
2
1
2
2
<29,7> CLK_PCI_EC ODD_DA#_APU 1 2 ESD@ CC32 QC1A

<7> CLK_PCI_DDR CC104 180P_0402_50V8J 0.1U_0402_16V4Z 2N7002KDWH_SOT363-6
<29,7> LPC_FRAME# Onkyo No Brand @
A 2 A
GEVENT2
SPK_DET 0 1
RTC_CLK
close to APU
1
1
1
@ @ RC114 @
RC112
RC113 RC111 2K_0402_5% RC115
2K_0402_5% 2K_0402_5%
2K_0402_5% 2K_0402_5% Issued Date 2012/09/27 Deciphered Date 2015/09/27 Title
2
FT3 GPIO/AZ/MISC
2
2
2
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
AMD CKL v1.01 10uF 0.1uF 180pF

1.5V OF APU VDDIO_MEM_S 2 8 4 UC1F
UC1G UC1H
3A J35 VDDIO_MEM_S_1
POWER
VDDCR_CPU_1 L21
15A/21A GND GND
+1.5V +1.5V +APU_CORE
L32 VDDIO_MEM_S_2 VDDCR_CPU_2 L23 A8 VSS_1 VSS_63 J3 W 29 VSS_125 VSS_187 AL39
L37 VDDCR_CPU_3 L25 A13 J7 W 39 AL41
3A N35
VDDIO_MEM_S_3
VDDIO_MEM_S_4 VDDCR_CPU_4 L27 A23
VSS_2
VSS_3
VSS_64
VSS_65 J8 W 41
VSS_126
VSS_127
VSS_188
VSS_189 AM11
R31 VDDIO_MEM_S_5 VDDCR_CPU_5 L29 A31 VSS_4 VSS_66 J39 Y1 VSS_128 VSS_190 AM27
1@ R37 VDDCR_CPU_6 N21 A35 K11 Y2 AM31
10U_0603_6.3V6M CC40
0.1U_0402_16V7K CC34
0.1U_0402_16V7K CC41
0.1U_0402_16V7K CC35
0.1U_0402_16V7K CC42
10U_0603_6.3V6M CC39
0.1U_0402_16V7K CC33
0.1U_0402_16V7K CC36
0.1U_0402_16V7K CC43
0.1U_0402_16V7K CC37
1 1 2 2 2 2 2 2 2 2 VDDIO_MEM_S_6 VSS_5 VSS_67 VSS_129 VSS_191
CC14 U32 VDDIO_MEM_S_7 VDDCR_CPU_7 N23 A39 VSS_6 VSS_68 K13 AA3 VSS_130 VSS_192 AN3
U35 VDDIO_MEM_S_8 VDDCR_CPU_8 N27 B8 VSS_7 VSS_69 K17 AA7 VSS_131 VSS_193 AN7
47U_0805_6.3V6M
W 31 VDDIO_MEM_S_9 VDDCR_CPU_9 R21 B13 VSS_8 VSS_70 K19 AA8 VSS_132 VSS_194 AN39
2 2 1 1 1 1 1 1 1 1 2 W 32 VDDIO_MEM_S_10 VDDCR_CPU_10 R23 B23 VSS_9 VSS_71 K21 AA11 VSS_133 VSS_195 AP31
D D
W 37 VDDIO_MEM_S_11 VDDCR_CPU_11 R27 B31 VSS_10 VSS_72 K23 AA15 VSS_134 VSS_196 AR3
AA31 VDDIO_MEM_S_12 VDDCR_CPU_12 U21 B39 VSS_11 VSS_73 K25 AA19 VSS_135 VSS_197 AR13
AA35 VDDIO_MEM_S_13 VDDCR_CPU_13 U23 C1 VSS_12 VSS_74 K27 AA25 VSS_136 VSS_198 AR17
AC32 VDDIO_MEM_S_14 VDDCR_CPU_14 U27 C2 VSS_13 VSS_75 K29 AA29 VSS_137 VSS_199 AR21
AC37 VDDIO_MEM_S_15 VDDCR_CPU_15 W 21 C5 VSS_14 VSS_76 K31 AA39 VSS_138 VSS_200 AR25
AE31 VDDIO_MEM_S_16 VDDCR_CPU_16 W 23 C7 VSS_15 VSS_77 L3 AC3 VSS_139 VSS_201 AR29
AE35 VDDIO_MEM_S_17 VDDCR_CPU_17 W 27 C9 VSS_16 VSS_78 L7 AC7 VSS_140 VSS_202 AR39
AG32 VDDIO_MEM_S_18 VDDCR_CPU_18 AA21 C11 VSS_17 VSS_79 L8 AC11 VSS_141 VSS_203 AR41
AG37 VDDIO_MEM_S_19 VDDCR_CPU_19 AA23 C13 VSS_18 VSS_80 L10 AC15 VSS_142 VSS_204 AU1
AJ35 VDDIO_MEM_S_20 VDDCR_CPU_20 AA27 C15 VSS_19 VSS_81 L11 AC19 VSS_143 VSS_205 AU2
AL32 VDDIO_MEM_S_21 VDDCR_CPU_21 AC21 C17 VSS_20 VSS_82 L15 AC25 VSS_144 VSS_206 AU3
AL37 VDDIO_MEM_S_22 VDDCR_CPU_22 AC23 C19 VSS_21 VSS_83 L19 AC29 VSS_145 VSS_207 AU15
AMD CKL v1.01 10uF 4.7uF 1uF 180pF AR35 VDDIO_MEM_S_23 VDDCR_CPU_23 AC27 C21 VSS_22 VSS_84 L31 AC31 VSS_146 VSS_208 AU19
VDDCR_CPU_24 AE21 C23 L39 AC39 AU23
1.8VALW & 1.8VS OF APU VDD_18 1 7 1 VDDCR_CPU_25 AE23
VDDCR_CPU_26 AE27
C25
C27
VSS_23
VSS_24
VSS_25
VSS_85
VSS_86
VSS_87
L41
M1
AC41
AE3
VSS_147
VSS_148
VSS_149
VSS_209
VSS_210
VSS_211
AU27
AU39
VDD_18_ALW 1 6 1 C29 M2 AE7 AV9
VDDCR_NB_1 L13
13A/17A C31
VSS_26
VSS_27
VSS_88
VSS_89 N3 AE25
VSS_150
VSS_151
VSS_212
VSS_213 AW 3
+APU_CORE_NB
VDDCR_NB_2 L17 C33 VSS_28 VSS_90 N7 AE29 VSS_152 VSS_214 AW 7
+1.8VALW +1.8VALW_APU +1.8VS
VDDCR_NB_3 N11 C35 VSS_29 VSS_91 N15 AE32 VSS_153 VSS_215 AW 13
0.5A VDDCR_NB_4 N13 C37 VSS_30 VSS_92 N19 AE39 VSS_154 VSS_216 AW 15
1.5A
1 @ 2 VDDCR_NB_5 N17 C39 VSS_31 VSS_93 N25 AG3 VSS_155 VSS_217 AW 17
RC116 0_0603_5% VDDCR_NB_6 R11 C41 VSS_32 VSS_94 N29 AG5 VSS_156 VSS_218 AW 19
VDDCR_NB_7 R13 D9 N31 AG10 AW 21
1U_0402_6.3V6K CC50
1U_0402_6.3V6K CC51
1U_0402_6.3V6K CC54
1U_0402_6.3V6K CC55
10U_0603_6.3V6M CC57
1U_0402_6.3V6K CC60
1U_0402_6.3V6K CC61
1U_0402_6.3V6K CC64
CC49
1U_0402_6.3V6K CC52
1U_0402_6.3V6K CC53
1U_0402_6.3V6K CC58
1U_0402_6.3V6K CC59
1U_0402_6.3V6K CC62
1U_0402_6.3V6K CC63
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VSS_33 VSS_95 VSS_157 VSS_219
VDDCR_NB_8 R17 D11 VSS_34 VSS_96 N39 AG11 VSS_158 VSS_220 AW 23
VDDCR_NB_9 U13 D13 VSS_35 VSS_97 P1 AG13 VSS_159 VSS_221 AW 25
VDDCR_NB_10 U17 E3 P2 AG15 AW 27
4.7U_0603_6.3V6K
VSS_36 VSS_98 VSS_160 VSS_222

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDCR_NB_11 W 13 E4 VSS_37 VSS_99 R3 AG19 VSS_161 VSS_223 AW 31
VDDCR_NB_12 W 17 E9 VSS_38 VSS_100 R7 AG25 VSS_162 VSS_224 AW 33
C VDDCR_NB_13 AA13 E11 VSS_39 VSS_101 R15 AG29 VSS_163 VSS_225 AW 35 C
VDDCR_NB_14 AA17 E13 VSS_40 VSS_102 R19 AG31 VSS_164 VSS_226 AW 37
VDDCR_NB_15 AC13 E27 VSS_41 VSS_103 R25 AG39 VSS_165 VSS_227 AW 39
VDDCR_NB_16 AC17 E31 VSS_42 VSS_104 R29 AG41 VSS_166 VSS_228 AW 41
VDDCR_NB_17 AE15 E35 VSS_43 VSS_105 R39 AH1 VSS_167 VSS_229 AY13
VDDCR_NB_18 AE17 E38 VSS_44 VSS_106 R41 AH2 VSS_168 VSS_230 AY15
VDDCR_NB_19 AE19 E39 VSS_45 VSS_107 U1 AJ3 VSS_169 VSS_231 AY18
0.1A VDDCR_NB_20 AG17 G3 VSS_46 VSS_108 U2 AJ7 VSS_170 VSS_232 AY30
AL10 VDDIO_AZ_ALW_1 VDDCR_NB_21 AG21 G7 VSS_47 VSS_109 U3 AJ15 VSS_171 VSS_233 BA2
+1.5VS
AL11 VDDIO_AZ_ALW_2 G11 VSS_48 VSS_110 U7 AJ17 VSS_172 VSS_234 BA7
0.5A 1.5A G13 U8 AJ19 BA13
3.3VALW & 3.3VS OF APU +1.8VALW_APU B1
B2
VDD_18_ALW_1
VDD_18_ALW_2
VDD_18_1
VDD_18_2
A2
A3
+1.8VS G15
G17
VSS_49
VSS_50
VSS_51
VSS_111
VSS_112
VSS_113
U11
U15
AJ23
AJ25
VSS_173
VSS_174
VSS_175
VSS_235
VSS_236
VSS_237
BA15
BA18
VDD_18_3 B3 G21 VSS_52 VSS_114 U19 AJ29 VSS_176 VSS_238 BA21
VDD_18_4 C3 G25 VSS_53 VSS_115 U25 AJ31 VSS_177 VSS_239 BA25
+1.5VS 0.2A 0.2A G29 VSS_54 VSS_116 U29 AJ32 VSS_178 VSS_240 BA31
+3VALW_APU +3VS +3VS_APU AL13 VDD_33_ALW_1 VDD_33_1 AM15 G35 VSS_55 VSS_117 U31 AJ39 VSS_179 VSS_241 BA35
+3VALW_APU +3VS_APU
AM13 VDD_33_ALW_2 VDD_33_2 AM17 G37 VSS_56 VSS_118 U39 AL3 VSS_180 VSS_242 BA39
for VDDIO_AZ_ALW 0.1A 1A 5A G39 W3 AL8 A15
0.2A VSS_57 VSS_119 VSS_181 VSSBG_DAC
1 @ 2 +0.95VALW_APU_USB3
AR5 VDD_095_USB3_DUAL_1 VDD_095_1 AG23 +0.95VS_APU
G41 VSS_58 VSS_120 W5 AL15 VSS_182 VBURN AL31
RC117 0_0603_5% AU4 VDD_095_USB3_DUAL_2 VDD_095_2 AG27 H11 VSS_59 VSS_121 W 11 AL17 VSS_183 PSEN AM29
AV7 AJ21 H13 W 15 AL19
1U_0402_6.3V6K CC71
1U_0402_6.3V6K CC72
CC66
1U_0402_6.3V6K CC67
1U_0402_6.3V6K CC69
1U_0402_6.3V6K CC70
VDD_095_USB3_DUAL_3 VDD_095_3 VSS_60 VSS_122 VSS_184

1 1 1 1 1 1
AW 5 VDD_095_USB3_DUAL_4 VDD_095_4 AJ27 H23 VSS_61 VSS_123 W 19 AL25 VSS_185
for VDDIO_33_ALW 0.2A 0.5A VDD_095_5 AL21 H31 VSS_62 VSS_124 W 25 AL29 VSS_186
AE11 VDD_095_ALW_1 VDD_095_6 AL23
4.7U_0603_6.3V6K
+0.95VALW_APU FT3 REV 0.51 FT3 REV 0.51

2 2 2 2 2 2 AE13 VDD_095_ALW_2 VDD_095_7 AL27
AJ11 VDD_095_ALW_3 VDD_095_8 AM23 FT3_BGA769 @ FT3_BGA769 @
1U_0402_6.3V6K CC74
1U_0402_6.3V6K CC75
1 1 AJ13 VDD_095_ALW_4 VDD_095_9 AM25

0.6A
VDD_095_GFX_1 U10
B +0.95VS_APU_GFX B
2 2 4.5uA VDD_095_GFX_2 W 10 AMD CKL v1.01 10uF 1uF 180pF
+RTC_APU AN4 VDDBT_RTC_G VDD_095_GFX_3 AA10
FT3 REV 0.51

VDD_095_USB3_DUAL 2 3 1
VDD_095 2 5 1
FT3_BGA769 @ VDD_095_ALW 4
Place on TOP VDD_095_GFX 1 1
+0.95VS
0.95VALW & 0.95VS OF APU
2
PJ2
2
+0.95VALW +0.95VALW_APU_USB3 JUMP_43X79
AMD CKL v1.01 4.7uF 1uF 180pF 1A @
+0.95VALW +0.95VALW_APU +0.95VS_APU
1
VDDIO_AZ_ALW 1 3 1 0.5A +0.95VS_APU_GFX
1
1 @ 2 1 @ 2 5A LC1 0.6A
VDDIO_33_ALW 2 RC119 0_0603_5% 1U_0402_6.3V6K CC78 RC120 0_0603_5% 1 2
1U_0402_6.3V6K CC83
1U_0402_6.3V6K CC82
1U_0402_6.3V6K CC84
1U_0402_6.3V6K CC85
FBMA-L11-201209-300LMA30T
10U_0603_6.3V6M CC77
1U_0402_6.3V6K CC79
1U_0402_6.3V6K CC80
1 1 1 1 1 1 1 1
VDDIO_33 2 1
10U_0603_6.3V6M CC86
1U_0402_6.3V6K CC91
1U_0402_6.3V6K CC92
10U_0603_6.3V6M CC95
1U_0402_6.3V6K CC89
1U_0402_6.3V6K CC90
10U_0603_6.3V6M CC87
1U_0402_6.3V6K CC88
1U_0402_6.3V6K CC96
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
RTC OF APU +RTC_APU +RTC_APU_R
4.5uA RC122
1 2
A 10K_0402_5% A
1
0.22U_0402_16V7K
+3VL +RTC 1
CC98
RC123
DC5 120_0402_5%
2 1
2
1 2
CH751H-40PT_SOD323-2 route to 20mil

@
JCMOS
FT3 PWR/GND
2
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
+VREF_DQA 1
JDDR3L
2
DDR3 SO-DIMM A SO-DIMM VREF
DDR_AB_D0
3
5
VREF_DQ
VSS
VSS
DQ4
4
6
DDR_AB_D4
DDR_AB_D5
Reverse Type +1.5V +1.5V
DDR_AB_D1 7 DQ0 DQ5 8
9 DQ1 VSS 10 DDR_AB_DQS#0
VSS DQS0# DDR_AB_DQS[0..7] <11,5>
1
DDR_AB_DM0 11 12 DDR_AB_DQS0
13 DM0 DQS0 14 RD1 RD2
VSS VSS DDR_AB_DQS#[0..7] <11,5>
DDR_AB_D2 15 16 DDR_AB_D6 1K_0402_1% 1K_0402_1%
DDR_AB_D3 17 DQ2 DQ6 18 DDR_AB_D7
DQ3 DQ7 DDR_AB_D[0..63] <11,5>
19 20
2
DDR_AB_D8 21 VSS VSS 22 DDR_AB_D12
DQ8 DQ12 DDR_AB_DM[0..7] <11,5>
DDR_AB_D9 23 24 DDR_AB_D13 +VREF_DQA +VREF_CAA
25 DQ9 DQ13 26
D VSS VSS DDR_AB_MA[0..15] <11,5> D
DDR_AB_DQS#1 27 28 DDR_AB_DM1
DQS1# DM1
1
DDR_AB_DQS1 29 30 MEM_MAB_RST# 2 1 @ 2 1 @
DQS1 RESET# MEM_MAB_RST# <11,5>
31 32 RD3 RD4
DDR_AB_D10 33 VSS VSS 34 DDR_AB_D14 CD1 CD2 1K_0402_1% CD3 CD4 1K_0402_1%
DQ10 DQ14
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
DDR_AB_D11 35 36 DDR_AB_D15
0.1U_0402_16V7K
0.1U_0402_16V7K
37 DQ11 DQ15 38 1 2 1 2
2
2
43 DQ17 DQ21 44
DDR_AB_DQS#2 45 VSS VSS 46 DDR_AB_DM2
DDR_AB_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_AB_D22
DDR_AB_D18 51 VSS DQ22 52 DDR_AB_D23
DDR_AB_D19 53 DQ18 DQ23 54
55 DQ19 VSS 56 DDR_AB_D28
Close to JDDR3L.1 Close to JDDR3L.126
DDR_AB_D25 59 DQ24 DQ29 60
DDR_AB_DM3 63 VSS DQS3# 64 DDR_AB_DQS3
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS VSS
DDR_A_CKE0 73 74 DDR_A_CKE1
<5> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <5>
75 76
77 VDD VDD 78 DDR_AB_MA15
DDR_AB_BS2 79 NC A15 80 DDR_AB_MA14
<11,5> DDR_AB_BS2 BA2 A14
C 81 82 C
DDR_AB_MA12 83 VDD VDD 84 DDR_AB_MA11
DDR_AB_MA9 85 A12/BC# A11 86 DDR_AB_MA7
87 A9 A7 88
DDR_AB_MA5 91 A8 A6 92 DDR_AB_MA4
93 A5 A4 94
99 A1 A0 100
DDR_A_CLK0 101 VDD VDD 102 DDR_A_CLK1
<5> DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 <5>
DDR_A_CLK0# 103 104 DDR_A_CLK1#
<5> DDR_A_CLK0# CK0# CK1# DDR_A_CLK1# <5>
105 106
DDR_AB_MA10 107 VDD VDD 108 DDR_AB_BS1
A10/AP BA1 DDR_AB_BS1 <11,5>
DDR_AB_BS0 109 110 DDR_AB_RAS#
<11,5> DDR_AB_BS0 BA0 RAS# DDR_AB_RAS# <11,5>
111 112
DDR_AB_WE# 113 VDD VDD 114 DDR_A_SCS0#
<11,5> DDR_AB_WE# W E# S0# DDR_A_SCS0# <5>
DDR_AB_CAS# 115 116 DDR_A_ODT0
<11,5> DDR_AB_CAS# CAS# ODT0 DDR_A_ODT0 <5>
117 118
DDR_AB_MA13 119 VDD VDD 120 DDR_A_ODT1
A13 ODT1 DDR_A_ODT1 <5>
DDR_A_SCS1# 121 122
<5> DDR_A_SCS1# 123 S1# NC 124
125 VDD VDD 126 +VREF_CAA
127 TEST VREF_CA 128
133 DQ33 DQ37 134 Layout Note: Layout Note: Place these 4 Caps near
DDR_AB_DQS4 137 DQS4# DM4 138 Place near JDDR3L Command and Control signals of DIMMA
B
DDR_AB_D34 141 VSS DQ38 142 DDR_AB_D39 B
DDR_AB_D35 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_AB_D44 +1.5V Layout Note:
VSS DQ44
DDR_AB_D40 147
DQ40 DQ45
148 DDR_AB_D45 Place near JDDR3L.203 and 204
DDR_AB_D41 149 150
151 DQ41 VSS 152 CD43 1
VSS DQS5#
DDR_AB_DQS#5 2 47U_0805_6.3V6M
DDR_AB_DM5 153 154 DDR_AB_DQS5
155 DM5 DQS5 156
VSS VSS CD10 1 2 10U_0603_6.3V6M
DDR_AB_D43 159 DQ42 DQ46 160 DDR_AB_D47 +1.5V
DQ43 DQ47 CD11 1 2 10U_0603_6.3V6M
161 162
DQ48 DQ52 CD13 1 2 10U_0603_6.3V6M CD5 1 2 0.1U_0402_16V4Z
DDR_AB_D49 165 166 DDR_AB_D53 +0.75VS
167 DQ49 DQ53 168
VSS VSS CD14 1 2 10U_0603_6.3V6M CD6 1 2 0.1U_0402_16V4Z
DDR_AB_DQS#6 169 170 DDR_AB_DM6
DQS6 VSS CD16 1 2 10U_0603_6.3V6M CD7 1 2 0.1U_0402_16V4Z CD9 2 1 1U_0402_6.3V6K
173 174 DDR_AB_D54
DQ50 DQ55 CD18 1 2 10U_0603_6.3V6M CD12 2 1 1U_0402_6.3V6K
DDR_AB_D51 177 178 CD8 1 2 0.1U_0402_16V4Z
DDR_AB_D57 183 DQ56 DQ61 184
189 DM7 DQS7 190
195 DQ59 DQ63 196
197 VSS VSS 198 MEM_MAB_EVENT#
SA0 EVENT# MEM_MAB_EVENT# <11,5>
A 199 200 APU_SDATA0 A
+3VS VDDSPD SDA APU_SDATA0 <11,23,8>
201 202 APU_SCLK0
SA1 SCL APU_SCLK0 <11,23,8>
203 204
0.1U_0402_16V4Z
2 +0.75VS VTT VTT +0.75VS

205 206
CD20
207 GND1 GND2 208

1 BOSS1 BOSS2
LCN_DAN06-K4406-0103 2012/09/27 2015/09/27 Title
@
DDRIII-SODIMMA
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
+1.5V
JDDR3H
+1.5V DDR3 SO-DIMM B SO-DIMM VREF
+VREF_DQB 1
3 VREF_DQ VSS
2
4 DDR_AB_D4
Reverse Type +1.5V
+1.5V

DQ0 DQ5
1
DDR_AB_D1 7 8
1
DQ1 VSS DDR_AB_DQS[0..7] <10,5>
9 10 DDR_AB_DQS#0 RD8
VSS DQS0# RD6
DDR_AB_DM0 11 12 DDR_AB_DQS0 1K_0402_1%
DM0 DQS0 DDR_AB_DQS#[0..7] <10,5> 1K_0402_1%
13 14
DDR_AB_D2 15 VSS VSS 16 DDR_AB_D6 DDR_AB_D[0..63] <10,5>
2
2
19 DQ3 DQ7 20 +VREF_DQB +VREF_CAB
VSS VSS DDR_AB_DM[0..7] <10,5>
D
DDR_AB_D9 23 DQ8 DQ12 24 DDR_AB_D13 D
DQ9 DQ13 DDR_AB_MA[0..15] <10,5>
1
25 26
1
VSS VSS 2 1 @ 2 1 @
DDR_AB_DQS#1 27 28 DDR_AB_DM1 RD7
DQS1# DM1 CD21 CD22 RD5 CD23 CD24
DDR_AB_DQS1 29 30 MEM_MAB_RST# 1K_0402_1%
DQS1 RESET# MEM_MAB_RST# <10,5> 1K_0402_1%
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
31 32
0.1U_0402_16V7K
0.1U_0402_16V7K
DDR_AB_D10 33 VSS VSS 34 DDR_AB_D14 1 2 1 2
2
2
37 DQ11 DQ15 38
43 DQ17 DQ21 44
Close to JDDR3H.1 Close to JDDR3H.126
DDR_AB_D19 53 DQ18 DQ23 54
DDR_AB_D25 59 DQ24 DQ29 60
65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS VSS
DDR_B_CKE0 73 74 DDR_B_CKE1
<5> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <5>
75 76
77 VDD VDD 78 DDR_AB_MA15
C C
DDR_AB_BS2 79 NC A15 80 DDR_AB_MA14
<10,5> DDR_AB_BS2 BA2 A14
81 82
DDR_AB_MA9 85 A12/BC# A11 86 DDR_AB_MA7
87 A9 A7 88
93 A5 A4 94
99 A1 A0 100
DDR_B_CLK0 101 VDD VDD 102 DDR_B_CLK1
<5> DDR_B_CLK0 CK0 CK1 DDR_B_CLK1 <5>
DDR_B_CLK0# 103 104 DDR_B_CLK1#
<5> DDR_B_CLK0# CK0# CK1# DDR_B_CLK1# <5>
105 106
DDR_AB_MA10 107 VDD VDD 108 DDR_AB_BS1
A10/AP BA1 DDR_AB_BS1 <10,5>
DDR_AB_BS0 109 110 DDR_AB_RAS#
<10,5> DDR_AB_BS0 BA0 RAS# DDR_AB_RAS# <10,5>
111 112
DDR_AB_WE# 113 VDD VDD 114 DDR_B_SCS0#
<10,5> DDR_AB_WE# W E# S0# DDR_B_SCS0# <5>
DDR_AB_CAS# 115 116 DDR_B_ODT0
<10,5> DDR_AB_CAS# CAS# ODT0 DDR_B_ODT0 <5>
117 118
DDR_AB_MA13 119 VDD VDD 120 DDR_B_ODT1
A13 ODT1 DDR_B_ODT1 <5>
DDR_B_SCS1# 121 122
<5> DDR_B_SCS1# 123 S1# NC 124
125 VDD VDD 126 +VREF_CAB
127 TEST VREF_CA 128
Layout Note: Layout Note: Place these 4 Caps near
DDR_AB_D33 131 DQ32 DQ36 132 DDR_AB_D37 Place near JDDR3H Command and Control signals of DIMMB
133 DQ33 DQ37 134
B
Layout Note: B
139 DQS4 VSS 140 DDR_AB_D38 Place near JDDRH.203 and 204
DDR_AB_D35 143 DQ34 DQ39 144
DDR_AB_D41 149 DQ40 DQ45 150
DDR_AB_DM5 153 VSS DQS5# 154 DDR_AB_DQS5 +1.5V
155 DM5 DQS5 156
DDR_AB_D42 157 VSS VSS 158 DDR_AB_D46 +0.75VS
DQ42 DQ46 +1.5V
DDR_AB_D43 159 160 DDR_AB_D47 CD30 1 2 10U_0603_6.3V6M
161 DQ43 DQ47 162
DDR_AB_D48 163 VSS VSS 164 DDR_AB_D52 CD31 1 2 10U_0603_6.3V6M CD29 2 1 1U_0402_6.3V6K
DDR_AB_D49 165 DQ48 DQ52 166 DDR_AB_D53 CD25 2 1 0.1U_0402_16V4Z
167 DQ49 DQ53 168 CD33 1 2 10U_0603_6.3V6M CD32 2 1 1U_0402_6.3V6K
DDR_AB_DQS#6 169 VSS VSS 170 DDR_AB_DM6 CD26 2 1 0.1U_0402_16V4Z
DDR_AB_DQS6 171 DQS6# DM6 172 CD34 1 2 10U_0603_6.3V6M
173 DQS6 VSS 174 DDR_AB_D54 CD27 2 1 0.1U_0402_16V4Z
DDR_AB_D50 175 VSS DQ54 176 DDR_AB_D55 CD36 1 2 10U_0603_6.3V6M
DDR_AB_D51 177 DQ50 DQ55 178 CD28 2 1 0.1U_0402_16V4Z
179 DQ51 VSS 180 DDR_AB_D60 CD38 1 2 10U_0603_6.3V6M
DDR_AB_D57 183 DQ56 DQ61 184
189 DM7 DQS7 190
195 DQ59 DQ63 196
A A
1 2 197 VSS VSS 198 MEM_MAB_EVENT#
SA0 EVENT# MEM_MAB_EVENT# <10,5>
RD9 10K_0402_5% 199 200 APU_SDATA0
+3VS VDDSPD SDA APU_SDATA0 <10,23,8>
201 202 APU_SCLK0
SA1 SCL APU_SCLK0 <10,23,8>
203 204
0.1U_0402_16V4Z
2 +0.75VS VTT VTT +0.75VS

205 206
CD40
207 GND1 GND2 208 Security Classification Compal Secret Data Compal Electronics, Inc.
1 BOSS1 BOSS2
LCN_DAN06-K4806-0103
DDRIII-SODIMMB
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
LA-9868P
5 4 3 2 1
A B C D E
PCIE_ATX_C_GRX_P[3..0] UV1A PCIE_GTX_C_ARX_P[3..0]

<5> PCIE_ATX_C_GRX_P[3..0] PCIE_GTX_C_ARX_P[3..0] <5>
<5> PCIE_ATX_C_GRX_N[3..0]
PCIE_ATX_C_GRX_N[3..0] PART 1 0F 9 PCIE_GTX_C_ARX_N[3..0]
PCIE_GTX_C_ARX_N[3..0] <5> LVDS Interface
UV1D
1 1
PCIE_ATX_C_GRX_P0 AA38 Y33 PCIE_GTX_ARX_P0 .1U_0402_16V7K CV1 1 2 VGA@ PCIE_GTX_C_ARX_P0 PART 7 0F 9
PCIE_ATX_C_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PCIE_GTX_ARX_N0 1 2 VGA@ PCIE_GTX_C_ARX_N0
CV2
PCIE_RX0N PCIE_TX0N AK27
.1U_0402_16V7K RSVD/VARY_BL AJ27
Y35 W33 PCIE_GTX_ARX_P1 .1U_0402_16V7K CV3 1 2 VGA@ RSVD/DIGON
PCIE_ATX_C_GRX_P1 PCIE_GTX_C_ARX_P1
PCIE_ATX_C_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_GTX_ARX_N1 1 2 VGA@ PCIE_GTX_C_ARX_N1 LVDS CONTROL
CV4
PCIE_RX1N PCIE_TX1N
.1U_0402_16V7K
PCIE_ATX_C_GRX_P2 W38 U33 PCIE_GTX_ARX_P2 .1U_0402_16V7K CV5 1 2 VGA@ PCIE_GTX_C_ARX_P2 AK35

V37 PCIE_RX2P PCIE_TX2P U32 PCIE_GTX_ARX_N2 1 2 VGA@ TXCBP_DPB3P AL36
PCIE_ATX_C_GRX_N2 CV6 PCIE_GTX_C_ARX_N2
PCIE_RX2N PCIE_TX2N TXCBM_DPB3N
.1U_0402_16V7K
AJ38
V35 U30 PCIE_GTX_ARX_P3 .1U_0402_16V7K 1 2 VGA@ TX3P_DPB2P AK37
PCIE_ATX_C_GRX_P3 CV7 PCIE_GTX_C_ARX_P3
U36 PCIE_RX3P PCIE_TX3P U29 PCIE_GTX_ARX_N3 1 2 VGA@ TX3M_DPB2N
PCIE_ATX_C_GRX_N3 CV8 PCIE_GTX_C_ARX_N3
PCIE_RX3N PCIE_TX3N AH35
.1U_0402_16V7K TX4P_DPB1P AJ36
U38 T33 TX4M_DPB1N
T37 PCIE_RX4P PCIE_TX4P T32 AG38
PCIE_RX4N PCIE_TX4N TX5P_DPB0P AH37
TX5M_DPB0N
T35 T30 AF35
R36 PCIE_RX5P PCIE_TX5P T29 NC#AF35 AG36
PCIE_RX5N PCIE_TX5N NC#AG36
LVTMDP
R38 P33
P37 PCIE_RX6P PCIE_TX6P P32
PCIE_RX6N PCIE_TX6N AP34
TXCAP_DPA3P AR34
P35 P30 TXCAM_DPA3N
N36 PCIE_RX7P PCIE_TX7P P29 AW37
PCIE_RX7N PCIE_TX7N TX0P_DPA2P AU35
2 TX0M_DPA2N 2
N38 N33 AR37
M37 NC NC N32 TX1P_DPA1P AU39
NC NC AC Coupling Capacitor TX1M_DPA1N
PCI EXPRESS INTERFACE
PCIeR Gen1 and Gen2 only: Recommended value is 100 nF 10%.
AP35
M35 N30 PCIeR Gen3: Recommended value is 220 nF 10%. TX2P_DPA0P AR35
L36 NC NC N29 TX2M_DPA0N
NC NC AN36
NC AP37
L38 L33 NC
K37 NC NC L32
NC NC
K35 L30 VGA@ SUN-PRO M2_FCBGA962

J36 NC NC L29
NC NC
J38 K33
H37 NC NC K32
NC NC
H35 J33
G36 NC NC J32
NC NC
G38 K30 For MEMCLK 1GHz Brand Description Comment PS_3[3:1] R_pu(ohm) R_pd(ohm)
F37 NC NC K29
NC NC
skHynix H5TQ2G63DFR-N0C 1.5V/1GHz 000 NC 4750
F35 H33
E37 NC NC H32
NC NC gDDR3-2Gbit
3 3
Samsung K4W2G1646E-BC1A 1.5V/1GHz 111 4750 NC
CLOCK
CLK_PCIE_VGA AB35
<7> CLK_PCIE_VGA CLK_PCIE_VGA# AA36 PCIE_REFCLKP
<7> CLK_PCIE_VGA# PCIE_REFCLKN
CALIBRATION
Y30 VGA_PCIE_CALRP RV1 1 VGA@ 2 1.69K_0402_1%
PCIE_CALR_TX +0.95VGS
2 VGA@ 1 AH16 Y29 VGA_PCIE_CALRN RV3 1 VGA@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX +0.95VGS
RV2 1K_0402_5%
GPU_RST# AA30
3.3-V tolerant PERSTB
1
VGA@ SUN-PRO M2_FCBGA962

VGA@
RV212
100K_0402_5% For MEMCLK 900MHz Brand Description Comment PS_3[3:1]R_pu(ohm) R_pd(ohm)
2
skHynix H5TQ2G63DFR-11C 1.5V/900MHz 000 NC 4750
gDDR3-2Gbit 1.35V/900MHz
Micron MT41K128M16JT-107G:K 1.5V/900MHz 001 8450 2000
+3VS Samsung K4W2G1646E-BC11 1.5V/900MHz 111 4750 NC
VGA@
5
UV13
4 2 4
P
<8> PXS_RST# B 4 GPU_RST#

1 Y
<23,25,8> APU_PCIE_RST# A
G
3
MC74VHC1G08DFT2G SC70 5P

PCIE/LVDS
Size Document Number
Rev
Custom 1.0
LA-9868P
A B C D E
A B C D E
UV1B
PART 2 0F 9
MLPS
MUTI GFX Primary Memory Aperture Size MLPS Bit Strap Name Legacy Description Settings
AD29 GENLK_CLK AU24
NC Requested at PCI Configuration
AC29 GENLK_VSYNC AV23
NC
PS_0[1] ROM_CONFIG[0] If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0,
AT25 PS_0[2] ROM_CONFIG[1] GPIO[13:11] ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current 001
NC
AJ21 SWAPLOCKA AR24 Mars MLPS configuration Size of the Primary ROM_CONFIG [2:0]
AK21 DPA NC PS_0[3] ROM_CONFIG[2] databooks for details.
SWAPLOCKB Memory Apertures
AU26
NC
AV25
Bits[5:1] PU(1%) PD(1%) Cap
NC
xx000 NC 4.75k 128 MB 000 PS_0[4] N/A GENLK_VSYNC Reserved for internal use only. Must be 1 at reset. 1
AR8 NC AT27
NC
AU8 NC AR26
AP8
NC xx001 8.45k 2.00k
DBG_CNTL0 256 MB 001 STRAP_BIF_ Re-defined strap to indicate PCIe GEN3 capability.
AW8 NC AR30 PS_1[1] GEN3_EN_A GPIO_2 1 = PCIe GEN3 supported. 0
AR3
NC
AT29
xx010 4.53k 2.00k
NC NC 0 = PCIe GEN3 not supported.
AR1 NC 64 MB 010
+3VGS AU1 AV31
xx011 6.98k 4.99k
DBG_DATA0 NC
1 AU3 DBG_DATA1 AU30 1
AW3 DPB NC xx100 4.53k 4.99k
DBG_DATA2 Reserved 011 Determines whether or not the PCIe reference clock power
AP6 DBG_DATA3 AR32 management capability is reported in the PCI configuration space
AW5
NC
AT31
xx101 3.24k 5.62k
DBG_DATA4 NC PS_1[2] STRAP_BIF_ (otherwise known as CLKREQB).
AU5 DBG_DATA5 512 MB Not supported CLK_PM_EN GPIO_8 0
AR6 AT33
xx110 3.40k 10.0k 0 = The CLKREQB power management capability is disabled
RV12 DBG_DATA6 NC
AW6 AU32 1 = The CLKREQB power management capability is enabled
1 8 JTAG_TRSTB DBG_DATA7 NC xx111 4.75k NC
AU6 DBG_DATA8 1 GB Not supported
2 7 JTAG_TDI AT7 AU14
3 6 JTAG_TMS DBG_DATA9 NC 00xxx 680nF
AV7 DBG_DATA10 AV13
4 5 JTAG_TCK NC
AN7 DBG_DATA11 2 GB Not supported PS_1[3] N/A GENLK_CLK Reserved for internal use only. Must be 0 at reset. 0
AV9 AT15
01xxx 82nF
10K_8P4R_5% DBG_DATA12 NC
AT9 DBG_DATA13 AR14
@ AR10
NC 10xxx 10nF
DBG_DATA14 4 GB Not supported Transmitter (Tx) power savings enable.
AW10 DPC AU16 PS_1[4] TX_PWRS_ENB GPIO_0 1
DBG_DATA15 NC 11xxx NC 0 = 50% Tx output swing.
AU10 DBG_DATA16 AV15
AP10
NC 1 = Full Tx output swing.
RV13 DBG_DATA17
1 8 GPIO_16 AV11 DBG_DATA18 AT17
NC
2 7 GPIO_28_FDO AT11 DBG_DATA19 AR16
NC
3 6 VGA_SMB_CK2 AR12 DBG_DATA20 PCI EXPRESS transmitter, deemphasis enable.
4 5 VGA_SMB_DA2 AW12 DBG_DATA21 AU20 PS_1[5] TX_DEEMPH_EN GPIO_1 0 = Tx deemphasis disabled. 1
+3VGS NC
AU12 DBG_DATA22 AT19
AP12
NC 1 = Tx deemphasis enabled.
10K_8P4R_5% DBG_DATA23
VGA@ AT21
NC
AR20
NC
PS_2[1] N/A N/A Reserved. 0
VGA_SMB_CK2 AJ23 DPD AU22
SMBCLK SMBus NC
VGA_SMB_DA2 AH23 SMBDATA AV21
NC
CHECK VR PS_2[2] N/A N/A Reserved. 0
AT23
IF VR Suport PSI# and DPRSLPVR PU 10K NC
AR22
NC
to +3VGS: AK26 SCL To enable the external BIOS ROM device.
PSI# :Low load current flag AJ26 I2C PS_2[3] BIOS_ROM_EN GPIO_22 0
SDA 0 = Disable the external BIOS ROM device.
DPRSLPVR : Deeper sleep enable flag 1 = Enable the external BIOS ROM device.
AD39
R
GENERAL PURPOSE I/O AD37
AH20 AVSSN
GPU_DPRSLPVR GPIO_0
<39> GPU_DPRSLPVR
AH18 GPIO_1 AE36 VGA disable determines whether or not the card will be recognized as the
G
AN16 GPIO_2 AD35 system's VGA controller.
VGA@ AVSSN
1 2 PS_2[4] BIF_VGA_DIS GPIO_9 0 = VGA controller capacity enabled. 0
RV11 10K_0402_5% AF37
B 1 = The device will not be recognized as the system’s VGA controller.
AH17 GPIO_5_AC_BATT AE38
<29> GPU_DOWN# AVSSN
GPU_VID5 AJ17 GPIO_6_TACH
<39> GPU_VID5 DAC1
AK17 GPIO_7_BLON AC36
TV1 AJ13 HSYNC AC38
2
GPU_GPIO8 GPIO_8_ROMSO VSYNC
PS_2[5] N/A N/A Reserved. 0 2
TV2 GPU_GPIO9 AH15 GPIO_9_ROMSI
TV3 GPU_GPIO10 AJ16 GPIO_10_ROMSCK
AK16 GPIO_11 AB34 PS_3[1] BOARD_CONFIG[0] Base on
AL16 RSET
GPIO_12 PS_3[2] BOARD_CONFIG[1] N/A Board configuration related strapping (such as memory ID). VRAM ID
AM16 GPIO_13 AD34
AM14 AVDD AE34
PS_3[3] BOARD_CONFIG[2]
GPIO_14_HPD2 AVSSQ
GPU_VID1 AM13 GPIO_15_PWRCNTL_0
<39> GPU_VID1
GPIO_16 AK14 GPIO_16 AC33
VDD1DI
AG30 GPIO_17_THERMAL_INT AC34 PS_0[5] AUD_PORT_CONN_ Together with PS_0[5] form the three-bit strap option to indicate the number of
AN14 VSS1DI
RV8 1 @ 2 10K_0402_5% AM17
GPIO_18_HPD3 Pin Name Type PD/PU Description PS_3[4] PINSTRAP[0] audio-capable display outputs. In a given ASIC there are as many endpoints as
GPIO_19_CTF PS_3[5] there are digital display outputs, though not all outputs are audio capable.
GPU_VID2 AL13 GPIO_20_PWRCNTL_1 V13 Power-state indicator.
<39> GPU_VID2 NC AUD_PORT_CONN_ 111 = No usable endpoints.
TV4 GPU_GPIO21 AJ14 GPIO_21 U13 Permits the voltage regulator to activate power-saving
NC PINSTRAP[1] 110 = One usable endpoint.
TV5 GPU_GPIO22 AK13 GPIO_22_ROMCSB AF33 I/O N/A
CLKREQ_PEG# AN13
NC
AF32 features. 101 = Two usable endpoints.
<8> CLKREQ_PEG# CLKREQB NC GPIO_0 3.3 V PD-reset
AA29 IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS. AUD_PORT_CONN_ 100 = Three usable endpoints.
RV14 VGA@ NC (VDDR3)
1 2 10K_0402_5% NC
AG21 PSI# :Low load current flag PINSTRAP[2] 011 = Four usable endpoints. 111
GPU_VID3 AG32 GPIO_29 AC32 DPRSLPVR : Deeper sleep enable flag
<39> GPU_VID3 NC 010 = Five usable endpoints.
GPU_VID4 AG33 GPIO_30
<39> GPU_VID4 001 = Six usable endpoints.
AC31
NC_SVI2
AJ19 GENERICA AD30 (Optional) An input which allows the system to 000 = All endpoints are usable.
NC_SVI2
GENERIC_X AK19 GENERICB AD32 request a fastpower reduction by setting
NC_SVI2
Stereo-sync signal. AJ20 GENERICC
AK20 GPIO_5_AC_BATT to low (0 V). The resulting state
Indicates left/right frame, or top/bottom field. GENERICD I/O
AJ24 GPIO_5_AC_BATT PD-reset transition may disturb the display momentarily.
Can be left unconnected if not used. GENERICE_HPD4 3.3 V
AH26 GENERICF_HPD5 Power reductions that are less time critical
AH24 (VDDR3)
GENERICG_HPD6 should use the standard software methods in order
to prevent display disturbances.
PS_0 AM34 PS_0
AC30 CEC_1
Voltage control signals for the core (VDDC and VDDCI).
AK24 HPD1 PS_1 AD31 PS_1 At reset, these signals will be inputs with weak
MLPS
PX_EN : internal pulldown resistors.
High (3.3 V) switches the regulators GPIO_6
The VBIOS can define all voltage-control signals to be
off (enter BACO mode). AH13 AG31 either 3.3-V or open-drain outputs (all signals must
DBG_VREFG PS_2 PS_2 GPIO_15_PWRCNTL_0 I/O
+3VGS Low (0 V) switches the regulators PD-reset
3.3 V be the same type).
Enable JTAG access on. (Default) GPIO_20_PWRCNTL_1 (VDDR3) The output states (high/low) of these pins are
TV9 BACO programmable for each AMD PowerPlay state when they
PX_EN AL21 PX_EN AD33 PS_3 GPIO_29
PS_3
2
are used as voltage control signals.

RV7 GPIO_30 Note: GPIO_29 and GPIO_30 are only available on 28-nm
5.11K_0402_5% ASICs, and are NC on earlier generation ASICs.
3 @ 3
DEBUG DDC/AUX AM26
DDC1CLK
1
AN26
DDC1DATA
TESTEN AD28 TESTEN I Serial-ROM output from ROM.
AM27 3.3 V General purpose I/O or open-drain output.
AUX1P
Reserved signal, for normal ASIC operation. AL27 GPIO_8_ROMSO PD-reset
AUX1N (VDDR3)
Design: No use external VGA ROM, so use the test point.
JTAG_TRSTB AM23 AM19
JTAG_TRSTB DDC2CLK
MLPS Strap
2
JTAG_TDI AN23 JTAG_TDI AL19 Serial-ROM input to ROM.

DDC2DATA
RV9 JTAG_TCK AK23 JTAG_TCK GPIO_9_ROMSI General purpose I/O or open-drain output.
1K_0402_5% JTAG_TMS AL24 JTAG_TMS AN20
AUX2P
VGA@ TV7 JTAG_TDO AM24 JTAG_TDO AM20 O Serial-ROM clock to ROM. Bits[5:4] Bits[3:1] Capacitor R_pu R_pd
AUX2N
GPIO_10_ROMSCK 3.3 V General purpose I/O or open-drain output.
1
GPIO_28_FDO MLPS AL30 PD-reset

NC
AM30 (VDDR3) 11 001 NC 8.45K 2K
NC BIOS-ROM chip select. PS_0[5:1]
H Disable Used to enable the ROM for ROM read and program
THERMAL AL29 GPIO_22_ROMCSB
L Enable AF29
NC
AM29 operations. PS_1[5:1] 11 001 NC 8.45K 2K
DPLUS NC
AG29 DMINUS Design: No use external VGA ROM, so use the test
AN21 points.
NC
AM21 PS_2[5:1] 00 000 680 nF NC 4.75K
NC
GPIO_28_FDO AK32 GPIO_28_FDO
AK30 I/O Thermal monitor interrupt.
NC
AL31 TS_A AK29 GPIO_17_THERMAL_INT 3.3 V PD-reset An input from an external temperature sensor (ALERTb). PS_3[5:1] 11 XXX NC X X
+1.8VGS +TSVDD NC
(1.8V@13mA TSVDD) (VDDR3)
VGA@ LV3 AJ30
DDCVGACLK
1 2 +TSVDD AJ32 TSVDD AJ31 Critical temperature fault (CTF) (active high) will
DDCVGADATA
BLM15BD121SN1D_0402 AJ33 output 3.3 V if the on-die temperature sensor exceeds
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
TSVSS
CV17
CV18
CV19
1 1 1 a critical temperature so that the motherboard can

O Mapping to VRAM type please refer to page 6 +1.8VGS
TSVDD
120ohm
MarsCRB
1
Design
1 2 2 2
VGA@ SUN-PRO M2_FCBGA962 GPIO_19_CTF 3.3 V
(VDDR3)
PD-reset
The CTF setpoint is 109℃
protect the ASIC from damage by removing power.
by default, and is
programmed during ASIC initialization. See the
1
VGA@
VGA@
VGA@
0.1u 1 1 advisory for AMD PowerPlay states for more details.

@ @ @ VGA@
RV20 RV21 RV22 RV23
1u 1 1 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% +3VGS
10u 1 1 (Optional) Voltage control signal for the
2
I/O memory-voltage regulator. PS_0
GPIO_21 3.3 V PD-reset Note: This signal must be low (0 V) at reset PS_1
PS_2
(VDDR3)
2
(failure to do so will prevent booting). PS_3 VGA@
1
1
1
VGA_SMB_CK2 1 6
EC_SMB_CK2 <25,29,6>
Disable MLPS: PU 10K ohm to 3.3V. @ 1 VGA@ 1 @ 1 @ 1 @ VGA@ VGA@ VGA@
5
4 4
I/O (Do not install for Mars) CV20 CV21 CV22 CV23 RV27 RV28 RV68 RV30 QV1A
GPIO_28_FDO 3.3 V PD-reset 2K_0402_1% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1% DMN66D0LDW-7 2N_SOT363-6
0.68U_0402_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
Enable MLPS: PD 10K ohm to GND. VGA_SMB_DA2 4 3
(VDDR3) EC_SMB_DA2 <25,29,6>
2
2
2
(Install for Mars) 2 2 2 2
QV1B VGA@
DMN66D0LDW-7 2N_SOT363-6
Supports the CLKREQB feature for saving power to turn
CLKREQB O on/off the REFCLK clock on the ASIC.
On/off regulator switch in AMD PowerXpress? (switchable

graphics) BACO mode.
High (3.3 V) switches the regulators off (enter BACO
PX_EN O PD mode). Security Classification Compal Secret Data Compal Electronics, Inc.
Low (0 V) switches the regulators on. (Default) Issued Date 2012/09/27 2015/09/27 Title
Deciphered Date
PX_EN is tri-state before internal TEST_PG is asserted
and PERSTb is deasserted. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Main_MSIC
Custom 1.0
LA-9868P
A B C D E
A B C D E
UV1C
RV31 1 VGA@ 2 1M_0402_5%

PART 9 0F 9
YV1 VGA@
+1.8VGS +MPV18 4 3 XTALOUT
LV7 VGA@ (MPLL_PVDD:1.8V@130mA ) NC OSC
MPLL_PVDD MarsCRB Design 1 2 AV33 XTALIN XTALIN 1 2
XTALIN OSC NC
220ohm 1 1 BLM15BD121SN1D_0402 2 2
1U_0402_6.3V6K
0.1U_0402_16V7K
CV79
CV80
CV78
1 1
2.2U_0402_6.3V6M
27MHZ 10PF +-20PPM X3G027000DA1H
0.1u 1 1 1 1 1 CV24 CV25
15P_0402_50V8J 15P_0402_50V8J
1u 1 1 VGA@ 1 1 VGA@
2.2u 1 1 2 2 2
VGA@
VGA@
VGA@
AU34 XTALOUT
XTALOUT
+MPV18 H7
MPLL_PVDD
H8
MPLL_PVDD
+SPV18 (SPLL_PVDD:1.8V@75mA ) AW34
SPLL_PVDD MarsCRB Design +1.8VGS
LV8 VGA@ XO_IN
120ohm 1 1 1 2 +SPV18 AM10
SPLL_PVDD
PLLS/XTAL
BLM15BD121SN1D_0402
0.1u 1 1
CV81
CV82
CV83
1U_0402_6.3V6K
0.1U_0402_16V7K
2.2U_0402_6.3V6M
1u 1 1 1 1 1
+SPLL_VDDC AN9
SPLL_VDDC
AW35
XO_IN2
2.2u 1 1
2 2 2
VGA@
VGA@
VGA@
AN10
SPLL_PVSS
+0.95VGS AK10 Debug Only, for clock observation

SPLL_VDDC MarsCRB Design LV9 VGA@
+SPLL_VDDC
(SPLL_VDDC:0.95V@100mA ) AF30 CLKTESTA AL10 As short as possible
NC_XTAL_PVDD CLKTESTB
120ohm 1 1 1 2 AF31
NC_XTAL_PVSS
BLM15BD121SN1D_0402
0.1u 1 1
CV92
CV93
CV94
1U_0402_6.3V6K
0.1U_0402_16V7K
2.2U_0402_6.3V6M
1 1 1
2 1u 1 1 2
2.2u 1 1
2 2 2
VGA@
VGA@
VGA@
+0.95VS to +0.95VGS
+0.95VALW +0.95VGS
+3VS to +3VGS
3 +3VGS 3
Vgs=10V,Id=14.5A,Rds=6mohm +3VS
+3VALW
VGA@
2
VGA@
QV3 RV43
470_0805_5%
8 1
D S 470_0805_5%
2
7 2
2
D S VGA@ 2@
6 3 RV45
5 D S 4
RV44 CV103 Vgs=-4.5V,Id=3A,Rds<97mohm
3 1
VGA@ 100K_0402_5% 0.1U_0402_16V7K
D G
VGA@
FDS6676AS_SO8 QV3_GATE 1 RV48 2 1
AO3413_SOT23
B+ VGA@ RV46
3 1
1
220K_0402_5%
3
S
1 QV9B 47K_0402_5%
1
6
820K_0402_5%
VGA@ CV106
VGA@ RV49
0.1U_0402_25V6
VGA@ 2N7002DW-T/R7_SOT363-6 5 PXS_PWREN# 1 2 2

G
VGA@
QV8B +3VGS
VGA@ CV104
0.01U_0402_25V7K
2 2 QV4 D
1
2 PXS_PWREN# 5 2N7002DW-T/R7_SOT363-6 VGA@
2N7002DW-T/R7_SOT363-6
2
VGA@
6
VGA@
1
QV8A QV9A 1
2N7002DW-T/R7_SOT363-6
PXS_PWREN 2
<39,8> PXS_PWREN
1
4 4

BACO POWER
Rev
Custom 1.0
LA-9868P
A B C D E
A B C D E
Only for Kabini +1.8VALW to +1.8VGS

+1.5V to +1.5VGS
1 1
+1.5V VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+1.5VGS
UV3 VGA@ PJ12 @
1 14 +1.5VGS_LS 1 2
2 VIN1 VOUT1 13
VIN1 VOUT1
1 CV96 CV95 180P_0402_50V8J PAD-OPEN 4x4m 2
@ VGA_PWRGD 3 12 1 2 @ CV97
ON1 CT1 VGA@
1U_0402_6.3V6K
0.1U_0402_10V7K
4 11
2 +5VALW VBIAS GND 1
CV99 330P_0402_50V7K
VGA_PWRGD 5 10 1 2
<39,8> VGA_PWRGD ON2 CT2 VGA@ +1.8VGS
6 9 PJ13 @
+1.8VALW 7 VIN2 VOUT2 8 +1.8VGS_LS 1 2
VIN2 VOUT2
15 PAD-OPEN 4x4m 2
GPAD @ CV98
TPS22966DPUR_SON14_2X3
0.1U_0402_10V7K
1 1
@ CV100
1U_0402_6.3V6K
2
2 2
3 3
4 4

BACO POWER
Rev
Custom 1.0
LA-9868P
A B C D E
A B C D E
VDDR1 MarsCRB Design

0.01u 5 0 UV1E
+1.8VGS
+1.5VGS (PCIE_PVDD: 1.80V@100mA)
0.1u 5 0 PART 5 0F 9 +1.8VGS
PCIE_PVDD MarsCRB Design
2.2u 5 5 1u 2 2
(VDDR1:1.5V@1.5A) Maximum Current on +1.8VGS:
CV30
CV31
CV32
MEM I/O
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10u 3 3 +1.5VGS AC7
VDDR1 NC
AA31 1 1 1 "Sun": ~0.5 A 10u 1 1
AD11 VDDR1 AA32
AF7 NC AA33
CV33
CV34
CV35
CV36
CV37
CV38
CV39
CV40
VDDR1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
NC
1 1 1 1 1 1 1 1 AG10 VDDR1 AA34
NC 2 2 2
AJ7 W30
VGA@
VGA@
VGA@
VDDR1 NC
AK8 Y31
VDD_CT MarsCRB Design AL9
VDDR1 NC
V28 PCIE_VDDC:
2 2 2 2 2 2 2 2 VDDR1 NC_BIF_VDDC
120ohm 1 1 G11 W29
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VDDR1 NC_BIF_VDDC 0.95 V @ 1.88 A (PCIe Gen 2.0) +0.95VGS
G14 VDDR1 AB37
1
0.1u 1 1 PCIE_PVDD 0.95 V @ 2.50 A (PCIe Gen 3.0) 1
PCIE
G17
G20
VDDR1
G30 +0.95VGS
PCIE_VDDC MarsCRB Design
1u 1 1 G23
VDDR1
VDDR1
PCIE_VDDC
G31 1u 7 7
G26 PCIE_VDDC H29
10u 1 1
CV43
CV44
CV45
CV46
CV41
CV47
CV48
CV49
CV50
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
PCIE_VDDC 10u 2 2
G29 VDDR1 H30 1 1 1 1 1 1 1 1 1
PCIE_VDDC
H10 J29
VDDR1 PCIE_VDDC
J7 J30
VDDR1 PCIE_VDDC
J9 VDDR1 L28
K11 PCIE_VDDC M28 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VDDR3 Mars check list Design K13
VDDR1 PCIE_VDDC
N28
VDDR1 PCIE_VDDC
120ohm 1 1 K8
L12
VDDR1 PCIE_VDDC
R28
T28
BIF_VDDC Mars check list Design
VDDR1 PCIE_VDDC
1u 3 2 L16 VDDR1 PCIE_VDDC
U28 1u 1 1
L21 +0.95VGS
10u 1 0 L23
VDDR1
VDDR1 (BIF_VDDC: 0.95V@1.4A) 10u 1 1
0.1u 0 1 L26 N27 +0.95VGS
VDDR1 BACO BIF_VDDC
L7 T27
VDDR1 BIF_VDDC
M11 VDDR1
N11
CV67
CV68
CV69
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
P7 VDDR1 AA15 1 1 1 Maximum Current on +0.95VGS:
CORE VDDC
R11 AA17 "Sun": ~4.0 A for PCIe GEN 3.0 designs
+1.8VGS +VDDC_CT VDDR1 VDDC
U11 AA20
VDDR1 VDDC (estimated)
LV4 VGA@ (VDD_CT:1.8V@13mA ) U7 VDDR1 AA22
VDDC 2 2 2
@
1 2 Y11 AA24
VDDR1 VDDC
BLM15BD121SN1D_0402 Y7 VDDR1 AA27
VDDC
AB16
CV51
CV52
CV53
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
VDDC AB18
1 1 1 VDDC
AB21
VDDC AB23
VDDC
LEVEL AB26
2 2 2 VDDC +VGA_CORE
AB28
VGA@
VGA@
VGA@
TRANSLATION VDDC
+VDDC_CT AF26 AC17
VDD_CT VDDC
AF27 VDD_CT AC20
AG26 VDDC AC22
VDD_CT +VGA_CORE
VDDC
AG27 VDD_CT AC24
VDDC
AC27
+3VGS +VDDR3 VDDC AD18
VDDC
2 LV5 VGA@ (VDDR3:3.3V@25mA) I/O AD21 2
1 2 AF23 VDDC AD23
+VDDR3 VDDR3 VDDC
BLM15BD121SN1D_0402 AF24 VDDR3 AD26
VDDC
AG23 AF17
CV42
CV54
CV55
VDDR3
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
AG24 VDDC AF20
1 1 1 VDDR3 VDDC
AF22
VDDC AG16
DVP VDDC
AD12 VDDR4 AG18
2 2 2 VDDC
AF11
VGA@
VGA@
VGA@
VDDR4
AF12 AH22 +VGA_CORE
VDDR4 VDDC
AF13 VDDR4 AH27
VDDC AH28
VDDC
M26
VDDC
AF15 N24
VDDR4 VDDC
AG11 R18
VDDR4 VDDC
AG13 VDDR4 R21
AG15 VDDC R23
VDDR4 VDDC
R26
VDDC
T17
VDDC T20
VDDC
T22
VDDC T24
VDDC
U16
VDDC
U18
VDDC U21
VDDC
U23
VDDC U26
VDDC
V17
VDDC
V20
VDDC V22
VDDC
V24
VDDC V27
VDDC
Y16
VDDC
Y18
VDDC Y21
VDDC
Y23
VDDC Y26
VDDC
Y28
3 VDDC 3
AA13 +VGA_CORE
VDDCI
AB13
VDDCI AC12
VDDCI
AC15
VDDCI
AD13
VDDCI AD16
VDDCI
M15
VDDCI M16
VDDCI
M18
Route as differential pair VOLTAGE VDDCI
M23
CORE I/O
SENESE VDDCI
ISOLATED
N13
VDDCI
AF28 FB_VDDC N15
<39> VCC_GPU_SENSE VDDCI N17
VDDCI
N20
VDDCI
AG28 N22
FB_VDDCI VDDCI
TV44 R12
VDDCI
R13
AH29 VDDCI R16
<39> VSS_GPU_SENSE FB_GND VDDCI
T12
VDDCI
T15
VDDCI V15
VDDCI
Y13
VDDCI
Need check all power current and decoupling capacitors

after got SUN databook and reference schematic.
4 4

Power
C 1.0
LA-9868P
A B C D E
A B C D E
UV1H UV1I
PART 3 0F 9 PART 4 0F 9 MAB[0..15]
MDB[0..63] MAB[0..15] <19>
GDDR5/DDR3 <19> MDB[0..63]
C37 G24 MDB0 C5 GDDR5/DDR3 P8 MAB0 DQMB#[0..7]
DQA0_0 MAA0_0/MAA_0 DQB0_0 MAB0_0/MAB_0 DQMB#[0..7] <19>
C35 J23 MDB1 C3 T9 MAB1
DQA0_1 MAA0_1/MAA_1 DQB0_1 MAB0_1/MAB_1
A35 H24 MDB2 E3 P9 MAB2 QSB[0..7]
DQA0_2 MAA0_2/MAA_2 DQB0_2 MAB0_2/MAB_2 QSB[0..7] <19>
E34 J24 MDB3 E1 N7 MAB3
DQA0_3 MAA0_3/MAA_3 DQB0_3 MAB0_3/MAB_3 QSB#[0..7]
G32 H26 MDB4 F1 N8 MAB4
DQA0_4 MAA0_4/MAA_4 DQB0_4 MAB0_4/MAB_4 QSB#[0..7] <19>
D33 DQA0_5 MAA0_5/MAA_5 J26 MDB5 F3 MAB0_5/MAB_5 N9 MAB5
F32 H21 F5 DQB0_5 U9
DQA0_6 MAA0_6/MAA_6 MDB6 MAB0_6/MAB_6 MAB6
DQB0_6
E32 G21 MDB7 G4 U8 MAB7
MEMORY INTERFACE A
D31 H19 MDB8 H5 Y9 MAB8
F30 H20 MDB9 H6 W9 MAB9
C30 DQA0_10 MAA1_2/MAA_10 L13 MDB10 J4 MAB1_2/MAB_10 AC8 MAB10
A30 G16 K6 DQB0_10 AC9
DQA0_11 MAA1_3/MAA_11 MDB11 MAB1_3/MAB_11 MAB11
DQB0_11
F28 DQA0_12 MAA1_4/MAA_12 J16 MDB12 K5 MAB1_4/MAB_12 AA7 MAB12
1 DQB0_12 1
C28 H16 MDB13 L4 AA8 B_BA2
DQA0_13 MAA1_5/MAA_BA2 DQB0_13 MAB1_5/BA2 B_BA2 <19>
A28 J17 MDB14 M6 Y8 B_BA0
DQA0_14 MAA1_6/MAA_BA0 DQB0_14 MAB1_6/BA0 B_BA0 <19>
E28 DQA0_15 MAA1_7/MAA_BA1 H17 MDB15 M1 MAB1_7/BA1 AA9 B_BA1
DQB0_15 B_BA1 <19>
MEMORY INTERFACE B
D27 MDB16 M3
DQA0_16 DQB0_16
F26 DQA0_17 WCKA0_0/DQMA_0 A32 MDB17 M5 H3 DQMB#0
DQB0_17 WCKB0_0/DQMB_0
C26 C32 MDB18 N4 H1 DQMB#1
DQA0_18 WCKA0B_0/DQMA_1 DQB0_18 WCKB0B_0/DQMB_1
A26 D23 MDB19 P6 T3 DQMB#2
DQA0_19 WCKA0_1/DQMA_2 DQB0_19 WCKB0_1/DQMB_2
F24 DQA0_20 WCKA0B_1/DQMA_3 E22 MDB20 P5 T5 DQMB#3
C24 C14 R4 DQB0_20 WCKB0B_1/DQMB_3 AE4
DQA0_21 WCKA1_0/DQMA_4 MDB21 DQMB#4
DQB0_21 WCKB1_0/DQMB_4
A24 DQA0_22 WCKA1B_0/DQMA_5 A14 MDB22 T6 AF5 DQMB#5
DQB0_22 WCKB1B_0/DQMB_5
E24 E10 MDB23 T1 AK6 DQMB#6
DQA0_23 WCKA1_1/DQMA_6 DQB0_23 WCKB1_1/DQMB_6
C22 D9 MDB24 U4 AK5 DQMB#7
DQA0_24 WCKA1B_1/DQMA_7 DQB0_24 WCKB1B_1/DQMB_7
A22 DQA0_25 MDB25 V6
F22 C34 V1 DQB0_25 F6
DQA0_26 MDB26 QSB0
EDCA0_0/QSA_0 DQB0_26 EDCB0_0/QSB_0
D21 DQA0_27 D29 MDB27 V3 K3 QSB1
A20 D25 MDB28 Y6 P3 QSB2
DQA0_28 EDCA0_2/QSA_2 DQB0_28 EDCB0_2/QSB_2
F20 E20 MDB29 Y1 V5 QSB3
D19 DQA0_30 E16 MDB30 Y3 AB5 QSB4
E18 EDCA1_0/QSA_4 E12 Y5 DQB0_30 EDCB1_0/QSB_4 AH1
DQA0_31 MDB31 QSB5
C18 DQA1_0 J10 MDB32 AA4 AJ9 QSB6
A18 D7 MDB33 AB6 AM5 QSB7
F18 MDB34 AB1
DQA1_2 DQB1_2
D17 DQA1_3 A34 MDB35 AB3 G7 QSB#0
A16 DDBIA0_0/QSA_0B E30 AD6 DQB1_3 DDBIB0_0/QSB_0B K1
DQA1_4 MDB36 QSB#1
DDBIA0_1/QSA_1B DQB1_4 DDBIB0_1/QSB_1B
F16 DQA1_5 E26 MDB37 AD1 P1 QSB#2
D15 C20 Close to pin Y12 and AA12 MDB38 AD3 W4 QSB#3
DQA1_6 DDBIA0_3/QSA_3B DQB1_6 DDBIB0_3/QSB_3B
E14 C16 MDB39 AD5 AC4 QSB#4
DQA1_7 DDBIA1_0/QSA_4B DQB1_7 DDBIB1_0/QSB_4B
F14 DQA1_8 C12 MDB40 AF1 AH3 QSB#5
D13 DDBIA1_1/QSA_5B J11 AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8
DQA1_9 MDB41 QSB#6
DDBIA1_2/QSA_6B +1.5VGS DQB1_9 DDBIB1_2/QSB_6B
F12 DQA1_10 F8 MDB42 AF6 AM3 QSB#7
A12 MDB43 AG4
DQA1_11 DQB1_11
D11 J21 MDB44 AH5 T7 ODTB0
DQA1_12 ADBIA0/ODTA0 DQB1_12 ADBIB0/ODTB0 ODTB0 <19>
1
F10 DQA1_13 G19 MDB45 AH6 W7 ODTB1
A10 ADBIA1/ODTA1 AJ4 DQB1_13 ADBIB1/ODTB1 ODTB1 <19>
DQA1_14 RV72 MDB46
DQB1_14
C10 DQA1_15 CLKA0 H27 40.2_0402_1% MDB47 AK3 L9 CLKB0
DQB1_15 CLKB0 CLKB0 <19>
G13 G27 VGA@ MDB48 AF8 L8 CLKB0#
DQA1_16 CLKA0B DQB1_16 CLKB0B CLKB0# <19>
H13 15mil MDB49 AF9
DQA1_17 DQB1_17
2
2 J13 DQA1_18 CLKA1 J14 MDB50 AG8 AD8 CLKB1 2
H11 H14 AG7 DQB1_18 CLKB1 AD7 CLKB1 <19>
DQA1_19 CLKA1B +MVREFDB_SB MDB51 CLKB1#
DQB1_19 CLKB1B CLKB1# <19>
G10 DQA1_20 MDB52 AK9
DQB1_20
G8 K23 MDB53 AL7 T10 RASB0#
DQA1_21 RASA0B DQB1_21 RASB0B RASB0# <19>
1
K9 K19 1 MDB54 AM8 Y10 RASB1#
DQA1_22 RASA1B DQB1_22 RASB1B RASB1# <19>
K10 DQA1_23 RV73 CV159 MDB55 AM7
G9 K20 AK1 DQB1_23 W10
DQA1_24 100_0402_1% 1U_0402_6.3V6K MDB56 CASB0#
CASA0B DQB1_24 CASB0B CASB0# <19>
A8 DQA1_25 K17 VGA@ VGA@ MDB57 AL4 AA10 CASB1#
CASA1B 2 DQB1_25 CASB1B CASB1# <19>
C8 MDB58 AM6
DQA1_26 DQB1_26
2
E8 CSA0B_0 K24 MDB59 AM1 P10 CSB0#_0
DQA1_27 DQB1_27 CSB0B_0 CSB0#_0 <19>
A6 DQA1_28 CSA0B_1 K27 MDB60 AN4 L10
C6 AP3 DQB1_28 CSB0B_1
DQA1_29 MDB61
DQB1_29
E6 DQA1_30 CSA1B_0 M13 MDB62 AP1 AD10 CSB1#_0
DQB1_30 CSB1B_0 CSB1#_0 <19>
A5 CSA1B_1 K16 MDB63 AP5 AC10
DQA1_31 DQB1_31 CSB1B_1
L18 MVREFDA CKEA0 K21 U10 CKEB0
L20 J20 Y12 CKEB0 AA11 CKEB0 <19>
MVREFSA CKEA1 +MVREFDB_SB CKEB1
MVREFDB CKEB1 CKEB1 <19>
AA12
MVREFSB
L27 WEA0B K26 N10 WEB0#
NC WEB0B WEB0# <19>
N12 WEA1B L15 AB11 WEB1#
NC WEB1B WEB1# <19>
AG12 NC
ZZZ2 ZZZ3 ZZZ4 ZZZ5
MAA0_8/MAA_13 H23 MAB0_8/MAB_13 T8 MAB13
RV34 1 VGA@ 2 120_0402_1% M27
MEM_CALRP0 MAA1_8/MAA_14
J19
MAB1_8/MAB_14
W8 MAB14
M21 S1G H1G S2G H2G U12 MAB15
MAA0_9/MAA_15 MAB0_9/MAB_15
M12 NC MAA1_9/RSVD M20 MAB1_9/RSVD V12
AH12 RV36 VGA@ RV70 VGA@
NC
S1G@ H1G@ S2G@ H2G@ DRAM_RST AH11 DRAM_RST#_R 1 2 1 2
DRAM_RST# <19>
10_0402_1% 51.1_0402_1%
X76xxxxxLx1 X76xxxxxLx2 X76xxxxxLx3 X76xxxxxLx4
1
VGA@ SUN-PRO M2_FCBGA962 VGA@
VGA@ SUN-PRO M2_FCBGA962 VGA@ CV158
RV71 120P_0402_50V9
2
4.99K_0402_1%
Memory clock 900MHz RC99 10K pull down R_pu & R_pd resistor:
1
0402 1% resistors are required.
3 3
GPU Type Memory Bus Width VRAM Vendor Compal P/N Manufacturer P/N X76 P/N Size per part Configuration Total Memory Size/Qty PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1] R_pu R_pd Place all these components close to GPU (Within 25mm)
and keep all component close to each other
64bit Hynix SA00003YO70 H5TQ2G63DFR-11C X7648051L01 2Gbit 128M*16 1GB/4pcs RV20 RV27
SUN PRO-M2 0 0 0
NC 4.75K
RV20 RV27
SUN PRO-M2 64bit Micron SA00005XB00 MT41K128M16JT-107G:K X7648051L03 2Gbit 128M*16 1GB/4pcs 0 0 1
8.45K 2K
64bit Samsung SA00005SH00 K4W2G1646E-BC11 X7648051L04 RV20 RV27

SUN PRO-M2 2Gbit 128M*16 1GB/4pcs 1 1 1 4.75K NC
Memory clock 1GHz RC95 10K pull high
GPU Type Memory Bus Width VRAM Vendor Compal P/N Manufacturer P/N X76 P/N Size per part Configuration Total Memory Size/Qty PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1] R_pu R_pd
RV20 RV27
SUN PRO-M2 64bit Hynix SA000065300 H5TQ2G63DFR-N0C X7648051L02 2Gbit 128M*16 1GB/4pcs 0 1 0 4.53K 2K
SUN PRO-M2 Samsung K4W2G1646E-BC1A X7648051L05 1GB/4pcs RV20 RV27

4
64bit SA000068U20 2Gbit 128M*16 1 1 0 3.4K 10K 4

MEM Interface
C 1.0
LA-9868P
A B C D E
A B C D E
UV1G
PART 6 0F 9 UV1F
AB39 A3 PART 8 0F 9
E39 GND GND A37
F34 GND GND AA16 DP_VDDR DP_VDDC
F39 GND GND AA18 AP31 +0.95VGS
G33 GND GND AA2 DP_VDDC AP32
G34 GND GND AA21 DP_VDDC AN33
H31 GND GND AA23 DP_VDDC AP33
H34 GND GND AA26 AN24 DP_VDDC AL33
H39 GND GND AA28 AP24 NC DP_VDDC AM33
J31 GND GND AA6 AP25 NC DP_VDDC AK33
1 J34 GND GND AB12 AP26 NC DP_VDDC AK34 1
GND GND NC DP_VDDC
(DP_VDDC: 0.95V@20mA)
K31 AB15 AU28 AN31
K34 GND GND AB17 AV29 NC DP_VDDC
K39 GND GND AB20 NC
L31 GND GND AB22
L34 GND GND AB24 AP20 AP13
GND GND NC NC
M34 AB27 AP21 AT13
M39 GND GND AC11 AP22 NC NC AP14
N31 GND GND AC13 AP23 NC NC AP15
N34 GND GND AC16 AU18 NC NC
P31 GND GND AC18 AV19 NC
P34 GND GND AC2 NC DP GND
P39 GND GND AC21 +1.8VGS AN27
R34 GND GND AC23 AH34 DP_VSSR AP27
T31 GND GND AC26 AJ34 DP_VDDR DP_VSSR AP28
T34 GND GND AC28 AF34 DP_VDDR DP_VSSR AW24
T39 GND GND AC6 AG34 DP_VDDR DP_VSSR AW26
U31 GND GND AD15 AM37 DP_VDDR DP_VSSR AN29
U34 GND GND AD17 AL38 DP_VDDR DP_VSSR AP29
GND GND
(DP_VDDR: 1.8V@20mA) DP_VDDR DP_VSSR
V34 AD20 AM32 AP30
V39 GND GND AD22 DP_VDDR DP_VSSR AW30
W31 GND GND AD24 DP_VSSR AW32
W34 GND GND AD27 DP_VSSR AN17
Y34 GND GND AD9 DP_VSSR AP16
Y39 GND GND AE2 DP_VSSR AP17
GND GND AE6 DP_VSSR AW14
GND AF10 DP_VSSR AW16
GND AF16 DP_VSSR AN19
GND AF18 DP_VSSR AP18
GND AF21 DP_VSSR AP19
GND GND DP_VSSR
AG17 AW20
F15 GND AG2 CALIBRATION DP_VSSR AW22
2 F17 GND GND AG20 DP_VSSR AN34 2
F19 GND GND DP_VSSR AP39
F21 GND AG6 AW28 DP_VSSR AR39
F23 GND GND AG9 NC DP_VSSR AU37
F25 GND GND AH21 DP_VSSR AF39
F27 GND GND AJ10 DP_VSSR AH39
F29 GND GND AJ11 AW18 DP_VSSR AK39
F31 GND GND AJ2 NC DP_VSSR AL34
F33 GND GND AJ28 DP_VSSR AV27
F7 GND GND AJ6 DP_VSSR AR28
F9 GND GND AK11 AM39 DP_VSSR AV17
G2 GND GND AK31 DP_CALR DP_VSSR AR18
G6 GND GND AK7 DP_VSSR AN38
H9 GND GND AL11 DP_VSSR AM35
J2 GND GND AL14 DP_VSSR AN32
J27 GND GND AL17 DP_VSSR
J6 GND GND AL2
J8 GND GND AL20
K14 GND GND
K7 GND AL23
L11 GND AL26
L17 GND GND AL32 VGA@ SUN-PRO M2_FCBGA962
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
3 N21 GND GND AP11 3
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND GND
U6 GND
V11 GND AG22
V16 GND NC
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39
Y24 GND VSS_MECH AW1
Y27 GND
GND
VSS_MECH
VSS_MECH
AW39 Security Classification Compal Secret Data Compal Electronics, Inc.
PWR_GND
VGA@ SUN-PRO M2_FCBGA962 Size Document Number Rev
Custom 1.0
LA-9868P
A B C D E
5 4 3 2 1
CHANNEL B: 512MB/1024MB DDR3

UV5 UV6 UV7 UV8
+VREFC_A1_B M8 E3 MDB24 +VREFC_A2_B M8 E3 MDB17 +VREFC_A3_B M8 E3 MDB33 +VREFC_A4_B M8 E3 MDB49

H1 VREFCA DQL0 F7 MDB26 H1 VREFCA DQL0 F7 MDB19 H1 VREFCA DQL0 F7 MDB37 H1 VREFCA DQL0 F7 MDB53
VREFDQ DQL1 F2 MDB30 VREFDQ DQL1 F2 MDB16 VREFDQ DQL1 F2 MDB35 VREFDQ DQL1 F2 MDB51
MAB0 N3 DQL2 F8 MDB31 MAB0 N3 DQL2 F8 MDB22 MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB55
MAB1 P7 A0 DQL3 H3 MDB25 MAB1 P7 A0 DQL3 H3 MDB20 MAB1 P7 A0 DQL3 H3 MDB32 MAB1 P7 A0 DQL3 H3 MDB48
MAB3 N2 A2 DQL5 G2 MDB28 MAB3 N2 A2 DQL5 G2 MDB18 MAB3 N2 A2 DQL5 G2 MDB34 MAB3 N2 A2 DQL5 G2 MDB50
MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
MAB6 R8 A5 MAB6 R8 A5 MAB6 R8 A5 MAB6 R8 A5
MAB7 R2 A6 D7 MDB15 MAB7 R2 A6 D7 MDB1 MAB7 R2 A6 D7 MDB58 MAB7 R2 A6 D7 MDB47
D MDB[0..63] MAB8 T8 A7 DQU0 C3 MDB10 MAB8 T8 A7 DQU0 C3 MDB7 MAB8 T8 A7 DQU0 C3 MDB60 MAB8 T8 A7 DQU0 C3 MDB43 D
<17> MDB[0..63] A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
MAB9 R3 C8 MDB14 MAB9 R3 C8 MDB2 MAB9 R3 C8 MDB56 MAB9 R3 C8 MDB45
MAB10 L7 A9 DQU2 C2 MDB11 MAB10 L7 A9 DQU2 C2 MDB4 MAB10 L7 A9 DQU2 C2 MDB62 MAB10 L7 A9 DQU2 C2 MDB42
MAB11 R7 A10/AP DQU3 A7 MDB13 MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB57 MAB11 R7 A10/AP DQU3 A7 MDB44
MAB12 N7 A11 DQU4 A2 MDB9 MAB12 N7 A11 DQU4 A2 MDB5 MAB12 N7 A11 DQU4 A2 MDB63 MAB12 N7 A11 DQU4 A2 MDB40
MAB13 T3 A12 DQU5 B8 MDB12 MAB13 T3 A12 DQU5 B8 MDB0 MAB13 T3 A12 DQU5 B8 MDB59 MAB13 T3 A12 DQU5 B8 MDB46
MAB[15..0] MAB14 T7 A13 DQU6 A3 MDB8 MAB14 T7 A13 DQU6 A3 MDB6 MAB14 T7 A13 DQU6 A3 MDB61 MAB14 T7 A13 DQU6 A3 MDB41
<17> MAB[15..0] A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
MAB15 M7 MAB15 M7 MAB15 M7 MAB15 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS A15/BA3 +1.5VGS
M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

<17> B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1 B_BA1 B_BA1
<17> B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
DQMB#[7..0] <17> B_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
<17> DQMB#[7..0] VDD VDD VDD VDD
K8 K8 K8 K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 VDD N9 CLKB0 J7 VDD N9 J7 VDD N9 CLKB1 J7 VDD N9
<17> CLKB0 CK VDD CK VDD <17> CLKB1 CK VDD CK VDD
K7 R1 CLKB0# K7 R1 K7 R1 CLKB1# K7 R1
<17> CLKB0# K9 CK VDD R9 K9 CK VDD R9 <17> CLKB1# K9 CK VDD R9 K9 CK VDD R9
CKEB0 CKEB1
QSB[7..0] <17> CKEB0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS <17> CKEB1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
<17> QSB[7..0]
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
<17> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <17> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<17> CSB0#_0 J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1 <17> CSB1#_0 J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1
RASB0# RASB1#
<17> RASB0# RAS VDDQ RAS VDDQ <17> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<17> CASB0# CAS VDDQ CAS VDDQ <17> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
QSB#[7..0] <17> WEB0# WE VDDQ E9 WE VDDQ E9 <17> WEB1# WE VDDQ E9 WE VDDQ E9
<17> QSB#[7..0] VDDQ VDDQ VDDQ VDDQ
F1 F1 F1 F1
QSB3 F3 VDDQ H2 QSB2 F3 VDDQ H2 QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
QSB1 C7 DQSL VDDQ H9 QSB0 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9 QSB5 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9

DQMB#1 D3 DML VSS B3 DQMB#0 D3 DML VSS B3 DQMB#7 D3 DML VSS B3 DQMB#5 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 VSS J2 QSB#2 G3 VSS J2 QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
VGA@ QSB#1 B7 DQSL VSS J8 QSB#0 B7 DQSL VSS J8 QSB#7 B7 DQSL VSS J8 QSB#5 B7 DQSL VSS J8
C C
CLKB0 1 2 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
RV78 40.2_0402_1% VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VGA@ T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<17> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
CLKB0# 1 2 T1 T1 T1 T1
RV79 40.2_0402_1% L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
VGA@ ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
CV160
1
1
0.01U_0402_16V7K J1 B1 J1 B1 J1 B1 J1 B1
RV80 L1 NC/ODT1 VSSQ B9 RV81 L1 NC/ODT1 VSSQ B9 RV82 L1 NC/ODT1 VSSQ B9 RV83 L1 NC/ODT1 VSSQ B9
2
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
VGA@ L9 NC/CE1 VSSQ D8 VGA@ L9 NC/CE1 VSSQ D8 VGA@ L9 NC/CE1 VSSQ D8 VGA@ L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8

VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VGA@ VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
CLKB1 1 2 VSSQ VSSQ VSSQ VSSQ
RV84 40.2_0402_1% 96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
VGA@ K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96 K4W1G1646G-BC11_FBGA96
CLKB1# 1 2 @ @ @ @
RV85 40.2_0402_1% VGA@
1
CV161
0.01U_0402_16V7K
2
Supported Memory Configurations: Up to 4 Gbit/part for DDR3.
+1.5VGS +1.5VGS +1.5VGS +1.5VGS

B B
1
1
1
1
VGA@ VGA@ VGA@ VGA@

RV86 RV87 RV88 RV89
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
15mil 15mil 15mil 15mil
2
2
2
2
+VREFC_A1_B +VREFC_A2_B +VREFC_A3_B +VREFC_A4_B

1
1
1
VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1

RV90 RV91 RV92 RV93
CV164
CV162
CV163
CV165
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2
2
2
2
VGA@ VGA@ VGA@ VGA@
+1.5VGS +1.5VGS close to UV7 UV8

+1.5VGS +1.5VGS close to UV9 UV10
CV179
CV167
CV184
CV186
CV197
CV198
CV168
CV170
CV171
CV172
CV183
CV187
CV194
CV166
CV169
CV173
CV185
CV188
CV193
CV195
CV196
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
close to UV9 UV10
22U_0603_6.3V6M
A 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
close to UV7 UV8 VGA@

VRAM Channel B
C 1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
<6> EDP_LCD_TXOUT0+_R EDP_LCD_TXOUT0+_R

LCD_VDD
<6> EDP_LCD_TXOUT0-_R EDP_LCD_TXOUT0-_R
<6> EDP_LCD_TXOUT1+_R EDP_LCD_TXOUT1+_R
<6> EDP_LCD_TXOUT1-_R EDP_LCD_TXOUT1-_R
D <6> EDP_LCD_TXOUT2+_R EDP_LCD_TXOUT2+_R If it's EPD, they're become Need check eDP&LVDS both 3V power rail. D
<6> EDP_LCD_TXOUT2-_R EDP_LCD_TXOUT2-_R LCD_TXOUT2+_R = EDP_TX0+ +3VS +LCD_VDD

LCD_TXCLK+
LCD_TXOUT2-_R = EDP_TX0-
<6> LCD_TXCLK+
LCD_TXOUT1+_R = EDP_TX1+ W=60mils W=60mils
LCD_TXCLK- U16
<6> LCD_TXCLK- LCD_TXOUT1-_R = EDP_TX1- 1.5A 1
5 VOUT I rush=1.5A
<6> EDP_LVDS_CLK EDP_LVDS_CLK LVDS_CLK = EDP_AUXP VIN
<6> EDP_LVDS_DATA EDP_LVDS_DATA LVDS_DATA = EDP_AUXN GND

2
+LCD_VDD_SS 4
SS
3
EN
1
APL3512ABI-TRG_SOT23-5
C17
1500P_0402_50V7K
2
+5VS <6> LCD_ENVDD
2
JLVDS R112
1 +5VS_LVDS_TOUCH 1 @ 2 20mils 100K_0402_5%
1 2 USB20_N4_R R390 0_0603_5%
2 3 USB20_P4_R
3
1
4 BKOFF#
4 5 INT_MIC_DATA
5 INT_MIC_DATA <26>
6 INT_MIC_CLK
6 INT_MIC_CLK <26>
7
7 8 USB20_P3_R +3VS
C 8 C
9 USB20_N3_R
9 @
10 +3VS_LVDS_CAM 1 2 20mils
10 11 +LCD_VDD R389 0_0603_5%
11 12 +3VS
12 +LCD_VDD Irush=1.5A 60mils
13 +3VS
13 14 EDP_LVDS_CLK
14 15 EDP_LVDS_DATA
15
16
17
18
16
17
18
19
EDP_LCD_TXOUT0-_R
EDP_LCD_TXOUT0+_R
EDP_LCD_TXOUT1-_R
EDP_LCD_TXOUT1+_R
USB20_P3_R 4
D29
4
ESD@
3
3 USB20_N3_R LCD_INV
19 20 EDP_LCD_TXOUT2-_R
20 21 EDP_LCD_TXOUT2+_R
21 22
22 +LCD_INV
23 LCD_TXCLK- B+
23 24 LCD_TXCLK+ +3VS
24 1.5A
25
EDP_LVDS_HPD <6> L2 2 EMI@ 1
25 26 LED_PWM
26 5 2 FBMA-L11-201209-221LMA30T_0805
27 BKOFF#_R Vbus GND
0.1U_0402_25V6
27 1
28 C22
28 29
29 30
30 +LCD_INV Irush=1.5A 60mils @EMI@
2
31
GND 32
GND 33
GND 34
GND INT_MIC_DATA 6 1 INT_MIC_CLK
35 6 1
GND
SC300001400 close to LVDS conn.
B @ pin1-4 Touch function for panel B
STARC_111H30-000000-G4-R
pin5-10 For Webcam with single or dual MIC
pin11-30 For LVDS or EDP panel LCD Control
Carmera & Touch Screen
D6 2 1 LED_PWM Reserve for eDP panel potential issue
<6> LCD_INT_PWM
+3VS
1
RB751V40_SC76-2
CAM_EMI@ L3 R131
3 4 USB20_P3_R 47K_0402_5%
<7> USB20_P3 3 4
EDP@ 1 2
5
R103 0_0402_5% U17 EDP@
2
2 1 USB20_N3_R 1
<7> USB20_N3 2 1
P
IN1 LCD_ENBKL <29,6>
BKOFF#_R 1 2 4
WCM-2012-900T_0805 D15 RB751V40_SC76-2 O 2 BKOFF#
IN2 BKOFF# <29>
G
LVDS@
3
R113 SN74AHC1G08DCKR_SC70-5
10K_0402_5%
Reserve for EMI request
TOUCH_EMI@
2
1 2 1 2
R104 0_0402_5% R147 0_0402_5%
A LVDS@ A
@TOUCH_EMI@ L4
3 4 USB20_N4_R
<7> USB20_N4 3 4
2 1 USB20_P4_R
<7> USB20_P4 2 1
WCM-2012-900T_0805
TOUCH_EMI@
1 2 Issued Date 2012/09/27 Deciphered Date 2015/09/27 Title
R105 0_0402_5%
LVDS/EDP W/ CAMERA
Reserve for EMI request 1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
+HDMI_5V_OUT
RPY2 RY1
1 8 APU_HDMI_CLK
OE# A Y
+3VS HDMI_HPD_U 1 2 HDMI_HPD_C
2 7 APU_HDMI_DATA 1K_0402_5%
3 6 HDMI_SCLK
+HDMI_5V_OUT 2 L L L
2
4 5 HDMI_SDATA RY2 CY4
100K_0402_5% 0.1U_0402_16V4Z L H H
1
4.7K_8P4R_5% UY1
1
H X Z
OE#
2 4 HDMI_HPD
1
A Y
G
74AHCT1G125GW_SOT353-5
D +3VS D
3
+3VS
1
RY3
2.2K_0402_5%
2
HDMI_HPD
HDMI_HPD <6,8>
2
G
APU_HDMI_CLK 3 1 HDMI_SCLK
<6> APU_HDMI_CLK
HDMI POWER CIRCUIT
D
QY1
G
BSH111_SOT23-3
VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m
<6> APU_HDMI_DATA
APU_HDMI_DATA 3 1 HDMI_SDATA Current Limit: TYP=0.8A ; MAX=1A
D
QY2
BSH111_SOT23-3
+HDMI_5V_OUT
UY2
1 5 +5VS
OUT IN
1 2
CY18 GND
C 3 4 C
0.1U_0402_10V7K FLG EN
2 AP2151DWG-7_SOT25-5
SA00006H000
LY1 EMI@
CY2 1 2 0.1U_0402_16V7K HDMI_TXC- 1 2
<6> APU_HDMI_CLK- 1 2
<6> APU_HDMI_CLK+
CY1 1 2 0.1U_0402_16V7K HDMI_TXC+ 4
4 3
3 HDMI Connector
KINGCORE WCM-2012HS-900T JHDMI @
HDMI_HPD_C 19
18 HP_DET
+HDMI_5V_OUT +5V
17
HDMI_SDATA 16 DDC/CEC_GND
HDMI_SCLK 15 SDA
14 SCL
13 Reserved
LY2 EMI@
HDMI_R_CK- 12 CEC
CY5 1 2 0.1U_0402_16V7K HDMI_TXD0- 1 2
<6> APU_HDMI_TX0- 1 2 11 CK-
HDMI_R_CK+ 10 CK_shield
HDMI_R_D0- 9 CK+
CY3 1 2 0.1U_0402_16V7K HDMI_TXD0+ 4 3
<6> APU_HDMI_TX0+ 4 3 8 D0-
HDMI_R_D0+ 7 D0_shield
KINGCORE WCM-2012HS-900T
HDMI_R_D1- 6 D0+
5 D1-
HDMI_R_D1+ 4 D1_shield 23
HDMI_R_D2- 3 D1+ GND 22
B 2 D2- GND 21 B
HDMI_R_D2+ 1 D2_shield GND 20
D2+ GND
LY3 EMI@ TYCO_2041343-1~D
CY7 1 2 0.1U_0402_16V7K HDMI_TXD1- 1 2
<6> APU_HDMI_TX1- 1 2
CY6 1 2 0.1U_0402_16V7K HDMI_TXD1+ 4 3 RPY3

<6> APU_HDMI_TX1+ 4 3 HDMI_R_CK+ 1 8
KINGCORE WCM-2012HS-900T HDMI_R_CK- 2 7
HDMI_R_D0+ 3 6
HDMI_R_D0- 4 5
499_8P4R_1%
RPY4
HDMI_R_D2+ 1 8
LY4 EMI@ HDMI_R_D2- 2 7
CY9 1 2 0.1U_0402_16V7K HDMI_TXD2- 1 2 HDMI_R_D1+ 3 6
<6> APU_HDMI_TX2- 1 2 HDMI_R_D1- 4 5
CY8 1 2 0.1U_0402_16V7K HDMI_TXD2+ 4 3 499_8P4R_1%

<6> APU_HDMI_TX2+ 4 3
KINGCORE WCM-2012HS-900T
1
QY3 D
ZZZ HDMI45@
+5VS
2
HDMI Royalty G
RO0000003HM S
3
A A
2N7002KW_SOT323-3
HDMI W/Logo + HDCP
HDMI W/O Logo: RO0000001HM

HDMI W/Logo: RO0000002HM Security Classification Compal Secret Data Compal Electronics, Inc.
HDMI W/Logo + HDCP: RO0000003HM 2012/09/27 2015/09/27 Title
please manually load HDMI W/O CEC
this virtual material to 45@ BOM AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
D D
CRT_EMI@
<6> APU_CRT_R APU_CRT_R L8 1 2 NBQ100505T-800Y_0402 APU_CRT_R_L
CRT_EMI@
<6> APU_CRT_G APU_CRT_G L9 1 2 NBQ100505T-800Y_0402 APU_CRT_G_L
CRT_EMI@
<6> APU_CRT_B APU_CRT_B L10 1 2 NBQ100505T-800Y_0402 APU_CRT_B_L
CRT@ CRT@
JCRT
6
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
11
2
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1 T65 PAD
C162 C164 C165 C166 C167 APU_CRT_R_L 1
C163
R175
7
1 R173
1 R174
CRT_DDC_DAT 12
2 2 2 2 2 2 APU_CRT_G_L 2
8
1
CRT@ CRT@ CRT@ HSYNC 13
C C
CRT@ CRT@ CRT@ CRT@ APU_CRT_B_L 3
9
+HDMI_5V_OUT
VSYNC 14 G
16
T66 PAD 4 17
G
10
CRT_DDC_CLK 15
5
USE HDMI POWER C-H_13-12201513CP
@
+HDMI_5V_OUT
2
C261
0.1U_0402_10V7K U49 CRT@ CRT@ +HDMI_5V_OUT
1 @ 1 8 1 2
+HDMI_5V_OUT VCC_SYNC BYP C148 0.22U_0402_16V7K
+3VS 2 3 APU_CRT_R_L
VCC_VIDEO VIDEO1
2
2
+3VS 7 4 APU_CRT_G_L R153 R176
VCC_DDC VIDEO2 4.7K_0402_5% 4.7K_0402_5%
CRT@ CRT@
<6> APU_CRT_DATA APU_CRT_DATA 10 5 APU_CRT_B_L
1
1
DDC_IN1 VIDEO3
B B
<6> APU_CRT_CLK APU_CRT_CLK 11 9 CRT_DDC_DAT

DDC_IN2 DDC_OUT1
APU_CRT_VSYNC 13 12 CRT_DDC_CLK
<6> APU_CRT_VSYNC SYNC_IN1 DDC_OUT2
R62 CRT@
APU_CRT_HSYNC 15 14 VSYNC_R 1 2 22_0402_5% VSYNC
<6> APU_CRT_HSYNC SYNC_IN2 SYNC_OUT1
R63 CRT@
6 16 HSYNC_R 1 2 22_0402_5% HSYNC
GND SYNC_OUT2
TPD7S019-15DBQR_SSOP16
A A

CRT
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
Slot 1 Half PCIe Mini Card-WLAN
+3V_WLAN WLAN&BT Combo module circuits

JWLAN
1 2 BT BT
3 1 2 4
3 4 on module on module
BT_ON 1 RM1 2 BT_CTRL_R 5 6
5 6
<8> CLKREQ_WLAN#
@ 0_0402_5% 7
7 8
8 Enable Disable
9 10
PJ11 11 9 10 12
<7> CLK_WLAN# 11 12
D +3V_WLAN
2 1 +3VS <7> CLK_WLAN
13
13 14
14 BT_ON H L D
15 16
17 15 16 18
JUMP_43X39 19 17 18 20
19 20 WL_OFF# <29>
@ 21 22
21 22 APU_PCIE_RST# <12,25,8>
23 24
<5> PCIE_WLANTX_ARX_N2 23 24
25 26
<5> PCIE_WLANTX_ARX_P2 25 26
27 28
29 27 28 30
29 30 APU_SCLK0 <10,11,8>
31 32 APU_SDATA0 <10,11,8>
<5> PCIE_ATX_C_WLANRX_N2 31 32
+3V_WLAN
40 mils <5> PCIE_ATX_C_WLANRX_P2
33
33 34
34
35 36 BT_ON 1 RM2 2 E51_RXD
37 35 36 38
USB20_N1 <7> From EC <29> BT_ON
1K_0402_5%
0.1U_0402_10V7K 37 38 USB20_P1 <7> BT
4.7U_0603_6.3V6K +3V_WLAN 39
39 40
40
1 1 1 41 42 For isolate BT_CTRL and
43 41 42 44
CM1 CM2 CM3 43 44 Compal Debug Card.
45 46
47 45 46 48
2 2 2 47 48
E51_TXD 49 50
0.1U_0402_10V7K <29> E51_TXD 49 50
E51_RXD 51 52
<29> E51_RXD 51 52
53 54
GND1 GND2
Debug card using
LCN_DAN08-52406-0500
@
C C
SATA HDD Conn. SATA ODD Conn
+5VS_ODD
+5VS 1.1A
Place closely JHDD SATA CONN.
1.2A
1 1 1
1 1 1
C185 C186 C187 C189 C192 C193
10U_0805_10V4Z 0.1U_0402_10V7K 0.1U_0402_10V7K 10U_0805_10V4Z 0.1U_0402_10V7K 0.1U_0402_10V7K
2 2 2
2 2 2
Place components closely ODD CONN.
B B
JHDD @ Close to JHDD

1
GND 2 SATA_ATX_C_DRX_P0 C194 1 2 0.01U_0402_25V7K JODD @
A+ SATA_ATX_DRX_P0 <7>
3 SATA_ATX_C_DRX_N0 C195 1 2 0.01U_0402_25V7K
A- SATA_ATX_DRX_N0 <7>
4 1
GND 5 SATA_DTX_ARX_N0 C196 1 2 0.01U_0402_25V7K GND 2 SATA_ATX_C_DRX_P1 C197 1 2 0.01U_0402_25V7K
B- SATA_DTX_C_ARX_N0 <7> A+ SATA_ATX_DRX_P1 <7>
6 SATA_DTX_ARX_P0 C198 1 2 0.01U_0402_25V7K 3 SATA_ATX_C_DRX_N1 C199 1 2 0.01U_0402_25V7K
B+ SATA_DTX_C_ARX_P0 <7> A- SATA_ATX_DRX_N1 <7>
7 4
GND GND 5 SATA_DTX_ARX_N1 C200 1 2 0.01U_0402_25V7K
B- SATA_DTX_C_ARX_N1 <7>
6 SATA_DTX_ARX_P1 C201 1 2 0.01U_0402_25V7K
B+ SATA_DTX_C_ARX_P1 <7>
8 7
V33 +3VS GND
9
V33 10
V33 11 8
GND DP ODD_PLUGIN# <8>
12 9 +5VS_ODD
GND 13 +5V 10
GND 14 +5V 11 ODD_DA#
V5 +5VS MD ODD_DA# <8>
15 15 12
V5 16 14 GND GND 13
V5 17 GND GND
GND 18
DAS/DSS 19 SANTA_202401-1
23 GND 20
24 GND V12 21
GND V12 22
A A
V12
SUYIN_127043FR022G196ZR

WLAN/SATA HDD&ODD
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
USB Sleep & Charge

Right side USB 3.0 x 2/ Sleep&Charge
State table for MAX14641
CB0 CB1 Mode STATUS

2A auto-detection charger mode for Apple device. LR2 EMI@
AM2 LR1 EMI@
0 0 Resistor dividers are connected to DP/DM. Including DCP USB30_RX0N 4 3 USB30_RX0N_L USB20_P8 4 3 USB20_P8_L
<7> USB30_RX0N <7> USB20_P8 4 3
4 3
Forced 1A charger mode for Apple devices.
0 1 AP1 Resistor dividers are connected to DP/DM. USB20_N8 1 2 USB20_N8_L
USB30_RX0P 1 2 USB30_RX0P_L <7> USB20_N8 1 2
<7> USB30_RX0P 1 2
D D
KINGCORE WCM-2012HS-670T WCM-2012-900T_0805
1 0 PM USB pass-through mode.DP/DM are connected to TDP/TDM
USB pass-through mode with CDP emulation.
1 1 CM Auto connects DP/DM to TDP/TDM depending
on CDP detection status.
JUSBR @
USB30_TX0P_C_L 9 13
LR3 EMI@ StdA-SSTX+ GND
@ USB30_TX0N_C_L 8 12
RR6 0_0402_5% EC_CHG_CB0 <29> <7> USB30_TX0N 1 2 USB30_TX0N_C 4 3 USB30_TX0N_C_L 7 StdA-SSTX- GND 11
CR15 0.1U_0402_16V7K 4 3 GND-DRAIN GND
USB30_RX0P_L 6 10
UR4 14641@ USB30_RX0N_L 5 StdA-SSRX+ GND
14641@ 1 2 USB30_TX0P_C 1 2 USB30_TX0P_C_L StdA-SSRX-
1 8 CHG_CB0 RR1 0_0402_5% SLP_CHG_CB0 <8> <7> USB30_TX0P 1 2 4
<29> CHG_PWR_GATE# CEN CB0 CR16 0.1U_0402_16V7K GND
USB20_DN9 2 7 USB20_N9 USB20_N9 <7> USB20_P8_L 3
USB20_DP9 3 DM TDM 6 USB20_P9 KINGCORE WCM-2012HS-670T 2 D+
14641@ USB20_P9 <7> USB20_N8_L
0_0402_5% CHG_CB1 4 DP TDP 5 1 D-
<8> SLP_CHG_CB1 RR2 +5VALW +USB_VCCB
9 CB1 VCC VBUS
PGND 1
CR1 LOTES_AUSB0015-P001A
MAX14641ETA+TGH7_TDFN-EP8_2X2
0.1U_0402_10V7K
@ 0_0402_5% CB0,CB1->VIH=1.4V UR4
<29> EC_CHG_CB1 RR5 2
Address
0x35
MAX14640ETA+TGH7
14640@
Left Side USB Port LR4 EMI@ LR5 EMI@

USB30_RX1N 4 3 USB30_RX1N_L USB20_DN9 4 3 USB20_N9_L
<7> USB30_RX1N 4 3 4 3
C C
USB30_RX1P 1 2 USB30_RX1P_L USB20_DP9 1 2 USB20_P9_L

EMI@ <7> USB30_RX1P 1 2 1 2
LR7
4 3 KINGCORE WCM-2012HS-670T WCM-2012-900T_0805
<7> USB20_P0 4 3 USB20_P0_L <25>
1 2 Sleep & Charge Port

<7> USB20_N0 1 2 USB20_N0_L <25>
JUSBF @
WCM-2012-900T_0805 USB30_TX1P_C_L 9 13
USB30_TX1N_C_L 8 StdA-SSTX+ GND 12
7 StdA-SSTX- GND 11
USB30_RX1P_L 6 GND-DRAIN GND 10
USB30_RX1N_L 5 StdA-SSRX+ GND
LR6 EMI@ StdA-SSRX-
4
<7> USB30_TX1N 1 2 USB30_TX1N_C4 3 USB30_TX1N_C_L USB20_P9_L 3 GND
CR17 0.1U_0402_16V7K 4 3 D+
+5VALW W=80mils USB20_N9_L 2
D-
2.0A
UR3
+USB_VCCC
<7> USB30_TX1P 1
CR18
2 USB30_TX1P_C1
0.1U_0402_16V7K 1 2
2 USB30_TX1P_C_L +USB_VCCA 1
VBUS
LOTES_AUSB0015-P001A
2 6 KINGCORE WCM-2012HS-670T
3 IN OUT 7
4 IN OUT 8
<29> USB_EN#2 EN/ENB OUT 5
1 USB_OC#2 <29,8>
GND OCB
1
SY6288DCAC_MSOP8
SA00003TV00 CR14
4.7U_0805_10V4Z
2@
B
USB POWER SWITH +3VALW +3VALW
B
W=100mils
2
+5VALW
2.5A
UR1
+USB_VCCA RR3
4.7K_0402_5% DR1 @ESD@
2
2 6 14640@ 1 1
IN OUT RR4
USB30_TX0P_C_L 10 9 USB30_TX0P_C_L
3 7
IN OUT 4.7K_0402_5%
1
<29> USB_CHG_EN# 4 8 USB30_TX0N_C_L 2 2 9 8 USB30_TX0N_C_L
EN/ENB OUT 14640@
1 5
2
GND OCB USB_CHG_OC# <29,8> QR1A
1
USB30_RX0P_L 4 4 7 7 USB30_RX0P_L
SY6288DCAC_MSOP8
6 1 CHG_CB1
SA00006DN00 <29,33,34> EC_SMB_CK1 USB30_RX0N_L 5 5 6 6 USB30_RX0N_L
2N7002KDWH_SOT363-6
5
14640@ QR1B 3 3
3 4 CHG_CB0 8
<29,33,34> EC_SMB_DA1
+5VALW W=80mils 2N7002KDWH_SOT363-6
14640@
2.0A
UR2
+USB_VCCB Change ESD Diode for EMI request YSCLAMP0524P_SLP2510P8-10-9
SC300002800
2 6
3 IN OUT 7
4 IN OUT 8
<29> USB_EN#0 EN/ENB OUT
1 5 USB_OC#0 <29,8> DR3 @ESD@
GND OCB
USB30_TX1P_C_L 1 1 10 9 USB30_TX1P_C_L
SY6288DCAC_MSOP8
SA00003TV00 USB30_TX1N_C_L 2 2 9 8 USB30_TX1N_C_L
USB30_RX1P_L 4 4 7 7 USB30_RX1P_L
USB30_RX1N_L 5 5 6 6 USB30_RX1N_L
3 3
+USB_VCCA +USB_VCCB
A A
W=100mils W=80mils 8
1 1 1 1 1 1 Change ESD Diode for EMI request YSCLAMP0524P_SLP2510P8-10-9

CR7 CR2 CR9 CR11 CR3 CR13 SC300002800
47U_0805_6.3V6M
47U_0805_6.3V6M
@
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
@
2 2 2 2 2 2

LUSB/RUSB/S&C
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
Battery Reset LAN Conn +3V_LAN

JLAN
LL1 1
1 2 +3V_LAN 1
+3VALW_APU 2
EMI@ <12,23,8> APU_PCIE_RST# 2 2
LANCLK_REQ# 3
ISOLATE# 4 3
5 4 4
<8> APU_PCIE_WAKE# 5
+3VS 6
+3VS
close to JLAN 7 6 6
RL24 2 1 10K_0402_5% LANCLK_REQ# 7
8
RL4 1 EMI@ 8 8
2 0_0402_5% CLK_LAN#_R 9
<7> CLK_LAN# RL5 1 9
2 0_0402_5% CLK_LAN_R 10
<7> CLK_LAN 10 10
11
1
EMI@ 11
D
<5> PCIE_ATX_C_LANRX_N1 12 D
13 12 12
SW6 1K_0402_5% <5> PCIE_ATX_C_LANRX_P1
14 13
TJG-533-V-T/R_6P RL1 <5> PCIE_LANTX_ARX_N1
3 1 For LAN function @ <5> PCIE_LANTX_ARX_P1
15 14
15
14
2
16
17 16 16
4 2 ISOLATE# 1 @ 2 WOL_EN# <24> USB20_P0_L
<35> ENLDO 18 17
RL2 0_0402_5% WOL_EN# <29> <24> USB20_N0_L 18 18
LAN_EN 19
<8> LAN_EN 19
5
6
2
+USB_VCCC +USB_VCCC 20
G
20 20
W=60mils 21
RL3 G1
CLKREQ_LAN# 1 3 LANCLK_REQ# 15K_0402_5% 22
<8> CLKREQ_LAN# G2 23
G3
S
24
G4
Sx Enable Sx Disable S0
QL1 Wake up Wake up ACES_50559-02001-001
2N7002KW_SOT323-3 @
WOL_EN# LOW HIGH HIGH
LED BATT CHARGE /FULL LED

G-SENSOR UG1 GSENSOR@ D24 R60
+3VS_HDP 2 3 VOUTX CG1 1 2 GSENSOR@ 0.033U_0402_16V7K 390_0402_5%
+5VS +3VS_HDP 12 Vdd1 Voutx 5 VOUTY CG2 1 2 GSENSOR@ 0.033U_0402_16V7K
C Vdd2 Vouty 2 1 1 2 C
7 VOUTZ CG3 1 2 GSENSOR@ 0.033U_0402_16V7K BATT_FULL_LED# <29>
Voutz
+5VALW HT-F196BP5_WHITE
1 1 SELF_TEST 4 10
CG12 UG3 GSENSOR@ CG13 6 ST NC1 11
PD NC2 D23
1U_0402_6.3V6K 1U_0402_6.3V6K 8 14 2 1 1 2
GSENSOR@ 1 5 GSENSOR@ FS NC3 15 BATT_CHG_LOW_LED# <29>
2 VIN VOUT 2 NC4 R3
16 HT-191UD5_AMBER_0603 510_0402_5%
2 NC5
GND
+3VS_HDP 9 1
3 4 Rev GND1 13
SHDN# BP GND2 White LED bright when both AC-adaptor is plugged in and Battery is full charged
TSH352TR LGA 16P Amber LED bright while charging battery from AC-adaptor.
G9191-330T1U_SOT23-5
SA00004GB00 Amber LED blink during Critical Low Battery
SA000022I00
+3VS_HDP POWER LED

RG1
1 8 RESET#
2 7 GXOUT
3 6 GXIN D28 R61
4 5 MODE 390_0402_5%
+5VALW 2 1 1 2
PWR_SUSP_LED# <29>
4.7K_8P4R_5%
GSENSOR@ HT-F196BP5_WHITE
B B
UG2 White LED bright when system is power on.

1 11 White LED blink when system is sleep mode.
<13,29,6> EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 HDPACT <29>
2
SELF_TEST 2 12 RG2
P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 47K_0402_5%
GSENSOR@
RESET# 3 13
WLAN/WiMAX LED (AMD NO WIMAX)
1
RESET# P1_4/TXD0
GXOUT 4 14 HDPLOCK <29>

XOUT/P4_7 P1_3/KI3#/AN11/TZOUT
RG3 47K_0402_5%
5 15 VOUTZ 2 1
VSS/AVSS P1_2/KI2#/AN10/CMP0_2 GSENSOR@
SA00003A600
GXIN 6 16 +3VS_HDP
XIN/P4_6 P4_2/VREF D27
+5VS 2 1 1 2
1 WL_BT_LED# <29>
+3VS_HDP 7 17 VOUTX CG6 R66
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_10V7K HT-191UD5_AMBER_0603 510_0402_5%
GSENSOR@
MODE 8 18 VOUTY 2
MODE P1_0/KI0#/AN8/CMP0_0
HDPINT RG4 2 1 1K_0402_5% 9 19

<29> HDPINT GSENSOR@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 Amber LED bright while Wireless and/or WiMAX turns on.
A A
1 1 10 20
P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 EC_SMB_DA2 <13,29,6>
CG8
CG7 GSENSOR@
0.1U_0402_10V7K 0.1U_0402_10V7K R5F211B4D34SP GSENSOR@
GSENSOR@ 2 2
LAN/G-SENSOR/LED/B_RES
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
20 mil 35mA for 3.3V level 40 mil 650mA for 5V level

UA1 close to pin 25 close to pin 38
+DVDD 1 @ 2 +AVDD 0.1U_0402_10V7K 0.1U_0402_10V7K 1 @ 2
+3VS +5VALW
MIC1_LINE1_R_R 4.7U_0603_6.3V6K CA58 MIC1_LINE1_R_C_R 22 1 +DVDD 1 RA22 0_0402_5% 2 1 2 1 RA18 0_0603_5%
MIC1_LINE1_R_L 4.7U_0603_6.3V6K CA57 MIC1_LINE1_R_C_L 21 MIC1_R DVDD 9 +DVDD_IO CA4
MIC1_L DVDD_IO 1
0.1U_0402_16V4Z CA42 CA47 CA37 CA50
17
MIC2_R AVDD1
25 +AVDD close to pin1 2
CA3
16 38 +AVDD 2.2U_0402_6.3V6M 10U_0603_6.3V6M 1 2 1 2
MIC2_L AVDD2 2 10U_0603_6.3V6M
31 39 +PVDD
+MIC1_VREFO_L MIC1_VREFO_L PVDD1
30 46 +PVDD
+MIC1_VREFO_R
29 MIC1_VREFO_R PVDD2 HDALink is 1.5V
<29> EC_MUTE_INT MIC2_VREFO
D
60 mil D
15 45 SPKR+
LINE2_R SPK_OUT_R+ +DVDD_IO 1 @ 2
14 44 SPKR- +1.5VS +PVDD 1 @ 2
LINE2_L SPK_OUT_R- 1 RA1 0_0402_5% +5VALW
1 2 RA24 0_0603_5%
CA45
CA33
20 40 SPKL+ 0.1U_0402_16V4Z 0.1U_0402_10V7K
MONO_OUT SPK_OUT_L+ 41 SPKL- close to pin9
SPK_OUT_L- 2 close to pin39 CA35
@ESD@ MONO_IN 12 2 1 10U_0603_6.3V6M
0.01U_0402_25V7K PCBEEP 75_0402_1%
CA65 1 2 10 33 HPOUT_R RA19 HP_R <27>
<8> AZ_SYNC_HD SYNC HPOUT_R 32 HPOUT_L RA20
11 HPOUT_L 75_0402_1% HP_L <27>
<8> AZ_RST_HD# RESET# 1
CA32
10 mil 5 0.1U_0402_10V7K
SDATA_OUT AZ_SDOUT_HD <8>
close to pin19 8 AZ_SDIN0_HD_R 2 1 For P/N and footprint close to pin46
2 1 19 SDATA_IN AZ_SDIN0_HD <8> 2
close to pin 28 AC_JDREF RA23 33_0402_5%
1 2 LDO_CAP 28 JDREF 6 AZ_BITCLK_HD
Please place them to ISPD page
RA30 20K_0402_1%
AC_VREF 27 LDO_CAP BCLK AZ_BITCLK_HD <8>
CA60 10U_0603_6.3V6M
1 2 CPVEE 34 VREF UA1
CA54 2.2U_0402_6.3V6M CBN 35 CPVEE 23 LINE1_R_C_L 269@ CA9 1 2 0.1U_0402_10V6K MIC1_LINE1_R_L
1 CBN LINE1_L
1
1 2 CBP 36 24 LINE1_R_C_R 269@ CA10 1 2 0.1U_0402_10V6K MIC1_LINE1_R_R

CA25 CA55 CA53 2.2U_0402_6.3V6M CBP LINE1_R 48
2.2U_0603_10V6K 0.1U_0402_10V7K NC
For S&M
2
2 2
<20> INT_MIC_DATA INT_MIC_CLK_R 3 GPIO0/DMIC_DATA 26 ALC269Q-VB6-CG
GPIO1/DMIC_CLK AVSS1 37 269@
AVSS2 42
SENSE_A 13 PVSS1 43
Sleep and Music
2 @ 1 SENSE_B 18 SENSE_A PVSS2 7
RA34 20K_0402_1% SENSE_B DVSS
47 AGND 259@ No
4 EAPD 49
<29> EC_MUTE# PD# Thermal Pad
C
269@ Yes C
EMI@ CA5 1 2 0.1U_0402_10V7K
For EMI reserve ALC259-VC2-CG_MQFN48_6X6 For EMI reserve
2
RA50 259@
4.7K_0402_5%
close to codec EMI@ CA6 1 2 0.1U_0402_10V7K
RA42 INT_MIC_CLK_R
<20> INT_MIC_CLK
FBMA-10-100505-301T
269@ DGND EMI@ CA51 EMI@ CA7 1 2 0.1U_0402_10V7K
CAM_EMI@ To solve noise issue AZ_BITCLK_HD 2 1 1 2 EMI@
1
10_0402_5% RA41 1 2
Internal AMP 10P_0402_50V8J RA38 EMI@ 0_0603_5%
EC_MUTE# 1 2
Hight Enable RA31 0_0603_5%
@EMI@
LOW Disable
Beep sound SPK MIC/LINE IN

2W 4ohm =40mil For EMI reserve RA47 2 1
+MIC1_VREFO_R
1W 8ohm =20mil close to codec
1K_0402_5% RA48 2.2K_0402_5%
MIC1_LINE1_R_R 2 1 MIC1_R <27>
SPKL+ 1 @ 2 SPK_L1 <27>
RA7 0_0603_5% MIC1_LINE1_R_L 2 1 MIC1_L <27>
1K_0402_5%
SPKL- 1 @ 2 RA45 2 1
PCI Beep CA70 RA8 0_0603_5%
SPK_L2 <27>
RA46 2.2K_0402_5%
+MIC1_VREFO_L
2
1 RA52 2 1 2 MONO_IN
B <8> APU_SPKR CA31 CA30 B
47K_0402_5%
0.1U_0402_10V7K ESD@ ESD@ MIC_SENSE
2
SCV00001K00 SCV00001K00
6
RA49 CA27
4.7K_0402_5% 100P_0402_50V8J RA29 269@
1
QA1A 100K_0402_5%
2
2
2N7002DW-T/R7_SOT363-6
1
269@ RA37
For better sound 0_0402_5%
1
SPKR+ 1 @ 2 SPK_R1 <27>
by customer request RA9 0_0603_5%
@
1
+3VL RA35 100K_0402_5%
SPKR- 1 @ 2 SPK_R2 <27> <29> SM_SENSE#

RA10 0_0603_5%
3
CA34
ESD@
CA36
ESD@ EC QA1B
SCV00001K00 SCV00001K00 2N7002DW-T/R7_SOT363-6 5 JACK_SENSE <27>
1 269@
4
Sense Pin Impedance Codec Signals Function
39.2K PORT-I (PIN 32, 33) Headphone out
place close to chip
20K PORT-B (PIN 21, 22) Ext. MIC MIC_SENSE 2 1 SENSE_A
SENSE A RA32 20K_0402_1%
10K PORT-C (PIN 23, 24)
A A
5.1K (PIN 48)

<27> NBA_PLUG
RA33 39.2K_0402_1%
39.2K PORT-E (PIN 14, 15)
SENSE B 20K PORT-F (PIN 16, 17) Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-H (PIN 20) Cover Sheet
Custom 1.0
5 4 3 2 1
5 4 3 2 1
SPK Conn.
For common design,
pull-high resistor should be placed at connector side.
ACES_50228-0067N-001
@
8 SM_DET BIOS setup Speaker Type BOM
7 GND
GND
6
D
<26> SPK_R1 5 6 1 S&M option Harman/Kardon 269@ D
<26> SPK_R2 4 5
<26> SPK_L1 3 4
<26> SPK_L2 2 3
<8> SPK_DET 1 2 0 Non Harman 259@
1
2
DA1 JSPK
ESD@
SCV00001K00
1
Non-Harman detection
0 ONKYO
SPK_DET
1 Non-Brand
HeadPhone/LINE Out JACK

C C
JLINE @
6
1
1 @ 2 HP_R_L 2
<26> HP_L
RA54 0_0402_5%
1 @ 2 HP_R_R 3
<26> HP_R
RA53 0_0402_5%
4
<26> NBA_PLUG
3
DA6 CA13 CA14

5
YSDA0502C_SOT23-3 @EMI@
100P_0402_50V8J
100P_0402_50V8J
@EMI@
@ESD@ TYCO_2041280-1_3.6D
1
B
MIC/LINE IN JACK B
JEXMIC @
6
1
1 @ 2 MIC1_R_L 2
<26> MIC1_L
RA56 0_0402_5%
1 @ 2 MIC1_R_R 3
<26> MIC1_R
RA55 0_0402_5%
4
<26> JACK_SENSE
CA11 CA12
3
DA7 RA40 5
@EMI@ +3VL
100P_0402_50V8J
100P_0402_50V8J
@EMI@
YSDA0502C_SOT23-3 4.7K_0402_5% TYCO_2041280-1_3.6D
2
@ESD@
269@ RA36
0_0402_5%
@
1
1
A A

Conn
Custom 1.0
5 4 3 2 1
5 4 3 2 1
LW1
SD_DATA0 2 1 2 SD_DATA0_L
BLM15BB121SN1D_0402
1 EMI@ CW11 EMI@
CW8 4.7P_0402_50V8J
1
0.1U_0402_16V4Z UW1
D 2 LW2 D
22 SD_DATA1 2 1 2 SD_DATA1_L
RSTZ BLM15BB121SN1D_0402
For power consumption measurement EMI@ CW12 EMI@
and remove it after Pre-MP phase 5
2 MS_INS 17 SD_DATA2 4.7P_0402_50V8J
<7> USB20_N2 1
3 DM SD_D2/MS_D5/SB13 16 SD_DATA3
<7> USB20_P2
DP SD_D3/MS_D4/SB12 15 SDCMD LW3
30mils SD CMD/SD_CMD 14 SDCLK SD_DATA2 2 1 2 SD_DATA2_L
1 @ 2 +3VS_CR 1 SD CLK/SD_CLK 21 SDCD# BLM15BB121SN1D_0402
+3VS DVDD SD_CDZ EMI@ CW13 EMI@
RW1 0_0402_5% +VCC_3IN1 24 13 SD_DATA0
PMOS SD_D0/MS_D6/SB9 12 SD_DATA1 4.7P_0402_50V8J
1 CW1 1
30mils SD_D1/MS_D7/SB8 11
2.2U_0402_6.3V6M +3VS_CR 19 MS BS/MS_BS 10 SDWP
+3VS_CR 23 DVDD SD_W P/MS_D1/SB5 9 LW4
2 20 DVDD SD_D4/MS_D0/SB4 8 SD_DATA3 2 1 2 SD_DATA3_L
GPIO0 SD_D5/MS_D2/SB3 7 BLM15BB121SN1D_0402
4 SD_D6/MS_D3/SB1 6 CW14 EMI@
please close the pin19 of UW1 +3VS_CR
AVDD SD_D7/MS_CLK/SB0 EMI@
+VDD18 18 4.7P_0402_50V8J
VDD18 1
12mils
+3VS_CR +3VS_CR 1 25
Thermal pad LW5
30mils CW5 GL834L-OGY01_QFN24_4X4
NC (default) 10K pull down SDCLK 2 1 2 SDCLK_L
1 BLM15BB121SN1D_0402
0.1U_0402_16V4Z
CW2 2 GPIO0 Power saving mode Normal mode EMI@ CW15 EMI@
0.1U_0402_16V4Z 4.7P_0402_50V8J
2 1
LW6
De-coupling and Bulk capacitor should place near to Cardreader chip and Combo Socket SDCMD 2 1 2 SDCMD_L
BLM15BB121SN1D_0402
C EMI@ CW10 @EMI@ C
please close the pin4 of UW1
4.7P_0402_50V8J
1
< 2 in 1 Card Reader >
+3VS_CR
+3VS_CR Close to connector Close to IC
@ JCARD
@JCARD 30mil
30mils 1 1
5 +VCC_3IN1
CW3 CW4 VDD 3 SDCMD_L
CMD 1
1
2.2U_0402_6.3V6M 0.1U_0402_16V4Z 6 SDCLK_L CW6
2 2 CLK 7 CW7
VSS 0.1U_0402_16V4Z 4.7U_0402_6.3V6M
4
2
VSS 2
8 SD_DATA0_L
DAT0 9 SD_DATA1_L
DAT1 1 SD_DATA2_L
DAT2 2 SD_DATA3_L
CD/DAT3
12 10 SDWP#
13 GND_SW W P_SW 11 SDCD
GND_SW CD_SW
T-SOL_156-2000302604
"Normal Close" type connector
B
CD_SW WP_SW B
Protect disable Protect Enable

Card Uninsertion Close
Close Close
For normal close type connector invert circuit
Card Insertion Open Open Close
+3VS_CR +3VS_CR
1
1
SDCD#
RW3 SDWP
100K_0402_5% RW4
100K_0402_5%
2
2
6
QW1A D
3
SDCD 2 QW1B D
G SDWP# 5
2N7002KDWH_SOT363-6 G
S 2N7002KDWH_SOT363-6
1
4
A A

CardReader GL834L
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
+3VL +3VL
0.1U_0402_10V7K 0.1U_0402_10V7K CB3

1 1 1 1 0.1U_0402_10V7K
CB1 CB2 CB5 1 2
0.1U_0402_10V7K
For EMI 2 2
CB4
2 2
111
125
0.1U_0402_10V7K
22
33
96
67
9
CLK_PCI_EC UB1
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
1
RB3
10_0402_5%
@EMI@ 1 21
D <8> GATEA20 GATEA20/GPIO00 GPIO0F WL_BT_LED# <25> D
2 23
<8> KB_RST# USB_EN#0 <24>
2
3 KBRST#/GPIO01 BEEP#/GPIO10 26
1 <7> SERIRQ SERIRQ GPIO12 FANPWM <5>
CB11 4 27
<7,8> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13
22P_0402_50V8J
<7> LPC_AD3 7 LPC_AD3
@EMI@ PWM Output
2 <7> LPC_AD2 8 LPC_AD2 63
<7> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_PRES <33>
10 LPC & MISC 64
<7> LPC_AD0 LPC_AD0 GPIO39 65 USB_OC#0 <24,8>
ADP_I/GPIO3A ADP_I <33,34>
12 AD Input 66
<7,8> CLK_PCI_EC CLK_PCI_EC GPIO3B ADP_V <34>
13 75
<8> LPC_RST# PCIRST#/GPIO05 GPIO42 HDPLOCK <25>
EC_RST# 37 76
+3VL RB2 20 EC_RST# IMON/GPIO43
<8> EC_SCI# 38 EC_SCII#/GPIO0E
47K_0402_5%
1 2 <31> 0.95VS_PWREN# GPIO1D 68
EC_RST#
DAC_BRIG/GPIO3C 70 HDPINT <25>
885_EC_ON
1 2 EN_DFAN1/GPIO3D 71
DA Output IREF/GPIO3E
CB12 0.1U_0402_10V7K KSI0 55 72
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F +3VL
KSI2 57 KSI1/GPIO31
KSI3 58 KSI2/GPIO32 83
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <26>
KSI4 59 84 LID_SW# 1 2
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 RB35 47K_0402_5%
KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <30>
KSO0 39 88 TP_DATA TP_DATA <30>
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE <38>
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 GPU_DOWN# <13>
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 POK <35>
VCIN0_PH connect to
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <33>
C KSO7/GPIO27 SPI Device Interface power portion (9012 only) RPB2
C
KSO8 47 VR_ON 1 8
KSO9 48 KSO8/GPIO28 119 SYSON 2 7
KSI[0..7] 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SPIDI <7> 3 6
KSO10 TP_DATA
<30> KSI[0..7] 50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPIDO <7> 4 5
KSO11 SPI Flash ROM Nuvoton EC share ROM TP_CLK +3VS
KSO[0..15] KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 EC_SPICLK <7>
<30> KSO[0..15] KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A EC_SPICS# <7>
4.7K_0804_8P4R_5%
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73
1 2 CHG_PWR_GATE# 81 KSO15/GPIO2F ENBKL/GPIO40 74 LCD_ENBKL <20,6>
+3VL KSO16/GPIO48 PECI_KB930/GPIO41 WOL_EN# <25>
RB23 10K_0402_5% CHG_PWR_GATE# 82 89
<24> CHG_PWR_GATE# KSO17/GPIO49 FSTCHG/GPIO50 HDPACT <25>
90
BATT_CHG_LED#/GPIO52 91 BATT_FULL_LED# <25>
SMBUS1->BATT, Smart Charger EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 CAPS_LED# <30> 1 2
SMBUS2->G-Sensor,GPU Thermal Sensor, <24,33,34> EC_SMB_CK1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54
@
PWR_SUSP_LED# <25>
EC_SMB_DA1 78 93 RB14 0_0402_5%
APU Thermal Sensor <24,33,34> EC_SMB_DA1 EC_SMB_CK2 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_CHG_LOW_LED# <25>
<13,25,6> EC_SMB_CK2 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 SYSON <31,36>
EC_SMB_DA2 80 121 VR_ON
EC SMBus2 for S0 , SMBus1 for S5 <13,25,6> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VR_ON <38>
PM_SLP_S4#/GPIO59 3VALW_APU_PWREN <31,35>
RPB1
1 8 EC_SMB_CK1 VCOUT0_PH_L 1 @ 2
+3VL 6 100 VS_ON <35>
2 7 EC_SMB_DA1 <8> SLP_S3# RB34 0_0402_5%
14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <8>
3 6 EC_SMB_CK2 <8> SLP_S5# VCOUT0_PH connect to power portion (9012 only)
+3VS 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# <8> H_PROCHOT_EC
4 5 EC_SMB_DA2 <8> EC_SMI# PROCHOT_IN <33>
16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PROCHOT_EC
<24,8> USB_OC#2 GPIO0A H_PROCHOT#_EC/GPXIOA06
H/L, no PU/PD
2.2K_0804_8P4R_5% 17 104 VCOUT0_PH_L
<24,8> USB_CHG_OC# GPIO0B VCOUT0_PH/GPXIOA07 PBTN_OUT#
18 GPO 105
<24> USB_CHG_EN# GPIO0C BKOFF#/GPXIOA08 BKOFF# <20> H/L, no PU/PD
19 GPIO 106
<24> USB_EN#2 GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <8>
25 107
<30> KB_LED EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 1.8_0.95VALW_PWREN <37>
28 108
<5> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 EC_PXCONTROL <8>
29
<23> WL_OFF# EC_PME#/GPIO15
<23> E51_TXD E51_TXD 30
31 EC_TX/GPIO16 110
<23> E51_RXD EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <34>
32 112 EC_ON_R
B <8> SYS_PWRGD PCH_PWROK/GPIO18 EC_ON/GPXIOD02 B
34 114
<23> BT_ON SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# <30>
36 GPI 115 LID_SW#
<26> SM_SENSE# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <30>
116 SUSP#
SUSP#/GPXIOD05 117 SUSP# <31,36>
GPXIOD06 118 EC_CHG_CB0 <24>
PECI_KB9012/GPXIOD07 EC_CHG_CB1 <24>
AGND/AGND
1 @ 2 EC_MUTE_INT_R 122 SUSP# 1 2

<26> EC_MUTE_INT XCLKI/GPIO5D
RB25 1 @ 2 0_0402_5%
XCLKO 123 124 +EC_V18R RB21 10K_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND
<8> RTC_CLK XCLKO/GPIO5E V18R

RB20 0_0402_5% 1
GND0
ESD@ 1 2 SYS_PWRGD CB15

1
CB6 0.1U_0402_10V7K P.32_SYS_PWRGD OD/L 1 2

4.7U_0805_10V4Z
RB22 CB16 KB9012QF-A3_LQFP128_14X14
for 1.8V PU APU
11
24
35
94
113
69
@ESD@ 1 2 SUSP# 100K_0402_5% 20P_0402_50V8 DB1

CB14 180P_0402_50V8J 2 1 APU_PROCHOT#
2
2
@ESD@
Close to EC SCV00001K00 close to APU
APU_PROCHOT# APU_PROCHOT# <38,6>

885@ Voltage Comparator Pins FOR 9012 A3
RB27 2 1 Low Active (+3.3V)
1
+3VL D
100K_0402_5% RB19 330K_0402_5% 2
H_PROCHOT_EC
1 2 E51_TXD VCIN0 pin109 2N7002KW_SOT323-3
EC_ON_R 1 @ 2 >1.2V <1.2V G
EC_ON <35> VCIN1 pin102 High Active QB1
RB36 0_0402_5%
RB28 S
3
1
4.7K_0402_5% VCOUT0 pin104 HIGH LOW
1 2 EC_MUTE_INT_R 1U_0402_6.3V6K
1 3 CB50
S
D
A 2 @ A
QB2 VCOUT1 pin103 LOW HIGH
2N7002KW_SOT323-3
885@
G
2
885_EC_ON
2
RB24 Security Classification Compal Secret Data Compal Electronics, Inc.

10K_0402_5% 2012/09/27 2015/09/27 Title
885@
LPC-EC-KB9012
1
1.0
For KB9012 EC_ON low pulse work around DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-9868P
5 4 3 2 1
5 4 3 2 1
Power Button Touchpad Connector +3VS
+3VS
2
+3VL R298 R299
4.7K_0402_5% 4.7K_0402_5%
2
JTP @
2
R202 15 16
1
100K_0402_5% 13 15 16 14 +3VS
13 14 TP_DATA <29> TP_SCLK1 1 6
11 12 APU_SCLK1 <8>
11 12 TP_CLK <29>
9 10
5
ON/OFFBTN# 7 9 10 8 Q8A
D ON/OFFBTN# <29> 7 8 D
5 6 TP_SDATA1 DMN66D0LDW-7 2N_SOT363-6
5 6
0.1U_0402_25V6
3 4 TP_SCLK1 TP_SDATA1 4 3
1 3 4 APU_SDATA1 <8>
C24 1 2
JPWR @ 1 2 Q8B
1 2 ON/OFFBTN# E-T_6900-G08N-00R DMN66D0LDW-7 2N_SOT363-6
ESD@ 1 2
3 4
2 5 3 4 6
7 5 6 8
7 8 +5VS
ACES_50611-0040N-001
Keyboard LED Lid SW U19

APX9132ATI-TRL_SOT23-3
JBLG @ 2 3
GND
+3VL VDD VOUT LID_SW# <29>
1
2 1
3 2
1 1
1
4 3
Q9 +5VS_LED 4
5 C218 C219
+5VS AO3413_SOT23 6 GND 0.1U_0402_16V4Z 10P_0402_50V8J
GND 2 2
3 1
S
+5VS_LED ACES_50578-0040N-001
KBL@
1
C C
R204
G
2
10K_0402_5%
KBL@
2
CPU
Screw Hole VGA FCH WLAN
1
D H5 H4
H1 H2 H3 H21 H29
2 Q10 H_4P2 H_4P6 H_4P2x4P6 H_3P3 H_3P3 H_7P0 H_3P3
<29> KB_LED G 2N7002KW_SOT323-3 @ @ @ @ @ @ @
KBL@
1
1
1
S
3
PTH NPTH
H7 H10 H11 H12 H13 H9 H6
NEW KEYBOARD CONN. H_4P0

@
H_3P0
@
H_3P0
@
H_3P0
@
H_3P0
@
H_3P2x3P7
@
H_3P2N
@
1
1
1
KSI[0..7]
KSI[0..7] <29>
KSO[0..15] H16
KSO[0..15] <29> H8 H18 H14 H15
B H_3P2 H_3P0 H_3P0 H_3P2 B
H_3P0
@ @ @ @
JKB @
1
1
1
1
1
2 1
3 2
<29> CAPS_LED#
+3VS 2 1
R4 300_0402_5% KSI1
4
5
3
4
5
PCB Fedical Mark PAD
KSI6 6
KSI5 7 6
FD1 FD2 FD3 FD4
KSI0 8 7
KSI4 9 8
@ @ @ @
KSI3 10 9
10
1
1
1
KSI2 11
KSI7 12 11
KSO15 13 12
KSO12
KSO11
KSO10
KSO9
14
15
16
17
13
14
15
16
ISPD
ZZZ1
UC1 X4@ UC1 X4NPI@ UC1 X4R1@
17
KSO8 18
18
UC1 @ SA00006R430 SA00006R400 SA00006R410
KSO13 19
KSO7 20 19 DAZ0WJ00100 SA00006KR40
KSO6 21 20 A4-5000 15W 4C CPU A4-5000 15W 4C CPU A4-5000 15W 4C
21 CPU A4-5000 15W 4C
KSO14 22
KSO5 23 22 PCB LA-9868P
X5@ UC1 X5NPI@ UC1 X5R1@
KSO3 24 23 UC1
KSO4 25 24
KSO0 26 25
KSO1 27 26 SA00006R330 SA00006R300 SA00006R310
KSO2 28 27
A A
29 28
29 CPU A6-5200 25W 4C CPU A6-5200 25W 4C CPU A6-5200 25W 4C
30
31 30
32 31
33 32
34 33
34
GND1
35 Security Classification Compal Secret Data Compal Electronics, Inc.
36 2012/09/27 2015/09/27 Title
GND2 Issued Date Deciphered Date
CVILU_CF17341U0R0-NH
KB/TP/LED/LID/DEBUG/ISPD
@ Size Document Number Rev
1.0
LA-9868P
5 4 3 2 1
5 4 3 2 1
+5VS VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+5VS_ODD
+5VALW U2 PJ8 @
VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
+5VS 1 14 +5VS_ODD_LS 1 2
PJ6 @ 2 VIN1 VOUT1 13
U1 VIN1 VOUT1
1 14 +5VS_LS 1 2 1 C14 C12 180P_0402_50V8J JUMP_43X79 2
2 VIN1 VOUT1 13 @ 3 12 1 2 @ C15
VIN1 VOUT1 <8> ODD_PWR ON1 CT1
1 C6 C5 180P_0402_50V8J JUMP_43X118 2
1U_0402_6.3V6K
0.1U_0402_10V7K
@ SUSP# 3 12 1 2 @ C7 +5VALW
4 11
ON1 CT1 2 VBIAS GND C11 330P_0402_50V7K 1
SUSP# 5 10 1 2
1U_0402_6.3V6K
0.1U_0402_10V7K
+5VALW 4 11 ON2 CT2
2 VBIAS GND C9 330P_0402_50V7K 1 +1.8VS
SUSP# 5 10 1 2 6 9 PJ9 @
D ON2 CT2 +3VS +1.8VALW 7 VIN2 VOUT2 8 +1.8VS_LS 1 2 D
PJ7 @ VIN2 VOUT2
6 9
+3VALW 7 VIN2 VOUT2 8 +3VS_LS 1 2 15 JUMP_43X79
GPAD 2
VIN2 VOUT2 @ C16
15 JUMP_43X118 TPS22966DPUR_SON14_2X3
GPAD 2
0.1U_0402_10V7K
@ C8 1
@ C13 1
TPS22966DPUR_SON14_2X3
0.1U_0402_10V7K
1
1U_0402_6.3V6K
@ C10 1
+5VALW TO +5VS 2
1U_0402_6.3V6K
2
+3VALW TO +3VS +1.8VALW TO +1.8VS
Load switch +5VS TO +5VS_ODD
Load switch
+0.95VALW to +0.95VS
+0.75VS
C +0.95VALW C
+0.95VS +3VALW_APU
+1.5V
Vgs=10V,Id=14.5A,Rds=6mohm
2
+5VALW
2
+5VALW R213
+5VALW
2
Q11 R221 470_0805_5%
8 1
470_0805_5%
2
R211 470_0805_5%
2
D S
2
7 2 470_0805_5%
2
R215
1
6 D S 3 R214 R212
R219 100K_0402_5%
1
5 D S 4 100K_0402_5%
100K_0402_5%
6
6 1
D G
1
FDS6676AS_SO8 Q11_GATE 1 R216 2 Q4A 2N7002KDWH_SOT363-6 SUSP
B+
1
3 1
SYSON#
1
1 220K_0402_5% Q3A Q5A
1
2 SUSP
3
0.1U_0402_25V6
3
C250 R217 2N7002KDWH_SOT363-6 2SYSON# 2
3
820K_0402_5% Q4B
Q2A Q2B Q3B 2N7002KDWH_SOT363-6 Q5B
1
2 2 5 2N7002DW-T/R7_SOT363-6 SUSP# 5
1
1
2N7002DW-T/R7_SOT363-6 5 <29,36> SUSP#
<29,36> SYSON 3VALW_APU_PWREN 5
2
2N7002KDWH_SOT363-6
1
4
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
4
<29> 0.95VS_PWREN#
B B
EMI Cap.
+1.5V to +1.5VS Please check location
+3VALW to +3VALW_FCH
B+ +3VALW
+1.5VS +3VALW
2
C18 C19 C20 C21 C23 @ C251 Vgs=-4.5V,Id=3A,Rds<97mohm
+1.5V +3VL
1U_0402_6.3V6K
0.1U_0402_25V6
2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
R218
R222 1 1 1 1 1 10K_0402_5% 0.1U_0402_10V7K
1
470_0805_5% 1
@
3
S
Q1 @ PJ4
3
1
R224
G
2 2 2 1 2 2 JUMP_43X39
2 2
1
S 10K_0402_5% R220 47K_0402_5%

885@ Q12 @ +3VALW_APU
2 AO3413_SOT23 D
1
1
3
@EMI@ @EMI@ @EMI@ @EMI@ @ESD@ @
1
2
2 SUSP 2 Q6 QC1B C252
1 G 2N7002KW_SOT323-3
0.01U_0402_25V7K
G
C253 1
0.1U_0402_25V6
AO3419L_SOT23-3 3VALW_APU_PWREN 5 2N7002KDWH_SOT363-6

<29,35> 3VALW_APU_PWREN
D
S
3
1
1
4
A +1.5VS R223 A
100K_0402_5%
9012@
2

DC TO DC INTERFACE
1.0
LA-9868P
5 4 3 2 1
A B C D
EMI Part (47.1)

Other component (37.1)
A51 need add fuse EMI@ PL1
HCB2012KF-121T50_0805
1 2
VIN
1 1
EMI@ PL3
@PJP1
@ PJP1 PF1 HCB2012KF-121T50_0805
1 1 2 DC_IN_S1 1 2
1 2
2 3 7A_32V_S1206-H-7.0A
3 4
4
ACES_50299-00401-001
1
PC102 EMI@ PC103 EMI@ PC101 EMI@ PC104 EMI@
1000P_0603_50V7K 100P_0603_50V8 100P_0603_50V8 1000P_0603_50V7K
2
For RTC (38.2)
+RTC_APU_R
PU1
3
Vout 1
2 Vin +RTC
GND
1U_0402_6.3V6K
2 For ML1220 RTC (38.2) 2
1U_0402_6.3V6K
AP2138N-1.5TRG1_SOT23-3
PC9
- PBJ101 @ + PR101
PR102
1
560_0603_5%
560_0603_5%
PC10
2
2 1 1 2+RTC_R
1 2
+RTC
2
ML1220T13RE
3 3
4 4

DCIN/PRECHARGE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
LA-9868P
Date: Sheet 32 of 42
A B C D
A B C D
PL4 EMI@
HCB2012KF-121T50_0805
1 2 EMI Part (47.1)
Other component (37.1)
VMB
@ PL5 EMI@
ACES_50299-01001-W01 PF2 HCB2012KF-121T50_0805
1 BATT_S1 1 2 1 2
1 2 BATT+
2 3 10A_125V_TR2/6125FF10-R
3 4 BATT_P4
4 5 BATT_P5
5 6 OTP (39.7)
1
EC_SMDA PC8 EMI@
6 7 PC7 EMI@
1
EC_SMCA
7 8 PR14 1000P_0402_50V7K 0.01U_0402_25V7K
2
1
8 9 1K_0402_1%
1
9 10
10
2
PJP2
+3VL
<29,34> ADP_I
12.1K_0402_1%
2
1
1K_0402_1%
PR4
PR1
PR16
2
6.49K_0402_1% @PR2
@ PR2 @ PR5
2 1 0_0402_5% 0_0402_5%
+3VL 1 2 1 2
100K_0402_1%_TSM0B104F4251RZ
PR19 <29> PROCHOT_IN <29> VCIN0_PH
1 2
BATT_PRES <29>
1
20K_0402_1%
1K_0402_1%
1
@ PC11
PR3
PH1
0.1U_0402_10V7K
2
2
PR20 PR21
2
100_0402_1% 100_0402_1%
1
EC_SMB_DA1 <24,29,34>
2 2
EC_SMB_CK1 <24,29,34>
3 3
4 4

BATTERY CONN / OTP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9868P 1.0
A B C D
A B C D
for reverse input protection
Charger controller (40.1), Support component (40.2)
1
D
2 PQ209
G 2N7002FU_SOT23
S
3
PR225 PR226
1 2 1 2
10U_0805_25V6K
1
1M_0402_5% 3M_0402_5%
EMI Part (47.1) 1
PC211
TPCA 8057 PQ205
VIN P1 P2 B+ S TR SI7716ADN
2
PQ203 SI7716ADN-T1-GE3_POWERPAK8-5 PR211 EMI@ PL201
PQ207
0.01_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 1 1 4 1 2 1
2200P_0402_25V7K
2 2 2
10U_0805_25V6K
5 3 3 5 2 3 5 3
0.1U_0402_25V6
1
PC213
@EMI@ PC214
2200P_0402_50V7K
0.01U_0402_50V7K
PC207 @
1
PC231 VIN
1U_0603_25V6K
4
1
2
PC234
2
2
1 2
PC230
2
1
2
3
2
PC236
0.1U_0402_25V6 PD230
2
BQ24725_ACDRV_1 BAS40CW_SOT323-3
BQ24725_BATDRV 1 2 BQ24725_BATDRV_1
0.1U_0402_25V6
0.1U_0402_25V6
0.047U_0402_25V7K PR233
1 1
10_1206_1%
4.12K_0603_1%
PC237
1
PC238
PC235
PR228
1 2
5
2
1
2.2_0603_5%
PR229
PD231
BQ24725_VCC
2
RB751V-40_SOD323-2 PQ201
AON7408L
DH_CHG 1 2 4
BQ24725_BST 2
BQ24725_REGN2
@ PR210
4.12K_0603_1%
4.12K_0603_1%
2
PC239 2
BQ24725_LX
1
1
1 2 0_0603_5% BATT+
PR235
PR234
DH_CHG
PL202
3
2
1
1U_0603_25V6K PC205 4.7UH_ETQP3W4R7WFN_5.5A_20% PR227
BQ24725_ACP
BQ24725_ACN
1 2 0.01_1206_1%
BQ24725_LX 1 2 CHG 1 4
2
2
1U_0603_25V6K
5
2 3
20
19
18
17
16
4.7_1206_5%
PU200
CSON1
CSOP1
1
@EMI@ PR206
BTST
PHASE
HIDRV
VCC
REGN
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
21 PQ202
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC221
PC222
PC223
1
1
1 15 DL_CHG 4 AON7406L
ACN LODRV
PC240
PC241
2
2
2 14
680P_0603_50V8J
@
ACP GND PR236
3
2
1
2
1
10_0603_1%
3 13 SRP1 2 CSOP1
@EMI@ PC206
BQ24725_CMSRC
CMSRC SRP
1
PR237
2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN1 2 CSON1
2
ACDRV SRN
5 11 BQ24725_BATDRV PC242
ACOK BATDRV 0.1U_0603_16V7K
EMI Part (35.33)
ACDET
IOUT
SDA
SCL
ILIM
1 2 BQ24725_ACOK +5VALW
+3VL
6
10
PR239 10K_0402_1% BQ24725RGRR_QFN20_3P5X3P5
3 3
BQ24725_ILIM 1 2
PR241
0.01U_0402_25V7K
<29> ACIN VIN
100K_0402_1%
590K_0402_1%
1
PC243
PR242
1
BQ24725_ACDET
VIN
1
422K_0402_1%
2
1
PR244
PR247
309K_0402_1%
PR248
2
10K_0402_1%
2
1 2
ADP_V <29>
Vin Dectector
0.1U_0402_25V6
1
66.5K_0402_1%
EC_SMB_CK1 <24,29,33>
1
1
@ PC247
Min. Typ Max. PR249
1
PR245
0.1U_0402_10V7K
PC244
47K_0402_1%
H-->L 17.23V
2
EC_SMB_DA1 <24,29,33>
2
2
L--> H 17.63V
2
@ PR246
PC245 0_0402_5%
2 1 1 2
ILIM and external DPM ADP_I <29,33>
100P_0402_50V8J
3.97A For A51 ADP_V function
1
@ PC246
@PC246
0.1U_0402_10V7K
2
4 4
Please locate the RC

Near EC chip
2011-02-22
CHARGER
Custom 1.0
LA-9868P
A B C D
A B C D
3/5VALW controller (35.1), Support component (35.2)
0_0402_5%
PQ333
3
S
PR339
2N7002FU_SOT23 G
2
1 <29,31> 3VALW_APU_PWREN 1
D @
1
PR350
EMI Part (47.1) 30K_0402_1%
1 2
B+ PR330
EMI@ PL331 3/5V_B+
14K_0402_1%
1 2 3/5V_B+
HCB2012KF-121T50_0805
56K_0402_1%
210K_0402_1%
174K_0402_1%
2
2
1 2 PR331
PR337
PR342
PR357
20K_0402_1%
1 2 FB_3V PR351
10U_0805_25V6K
2200P_0402_50V7K
10U_0805_25V6K
19.1K_0402_1%
<29> POK VL FB_5V 1 2
1
PC340
1
1
1
@EMI@ PC339
PC361
100K_0402_1%
1
2
2
5
PR335
AON7408L
1
PQ331
PQ351
4
FB2
ENTRIP2
ENTRIP1
FB1
TON
21 AON7408L
PAD
2
6
PC335 @ P333 PGOOD 20 4
0.1U_0402_10V7K 0_0402_5% BYP1 @ P355 PC355
1
2
3
1 2 BST1_3V 1 2 BST_3V 7 0_0402_5% 0.1U_0402_10V7K
BOOT2 19 BST_5V 1 2 BST1_5V 1 2
BOOT1
3
2
1
UG_3V 8
2
PL332 UGATE2 18 UG_5V 2
4.7UH_ETQP3W4R7WFN_5.5A_20% UGATE1 PL352

2 1 LX_3V 9 2.2UH_MMD-06CZ-2R2M-V1_8A_20%
+3VALWP PHASE2 17 LX_5V 1 2
PHASE1 +5VALWP
5
LG_3V 10
LGATE2
1
16 EMI Part (47.1)

4.7_1206_5%
LG_5V
150U_D2_6.3VY_R15M
ENLDO
SECFB
LGATE1
1
@EMI@ PR336
4.7_1206_5%
LDO5
LDO3
1
VIN
@EMI@ PR356
150U_D2_6.3VY_R15M
+
PC354
1
4 PU330
1 SNUB_3V 2
11
12
13
14
15
+
PC353
RT8243AZQW_WQFN20_3X3
2
SNUB_5V
2 4
AON7406L PR334 +3VLP 2

1
2
3
PQ352
680P_0603_50V8J
680P_0603_50V8J
PQ332 499K_0402_1%
1
1 2 VL PC341 FDMC7692S_MLP8-5
3/5V_B+
3
2
1
@EMI@ PC336
4.7U_0603_10V6K
1
100K_0402_1%
@EMI@ PC356
1U_0603_10V6K
0.1U_0603_25V7K
2
1
1
2
1
PC344
PC360
PR338
PC342
2
4.7U_0603_10V6K
2
2
2
<25> ENLDO
2
EMI Part (35.33)
PR340 5V
2.2K_0402_1%
1 2 Peak Current 12A
<29> EC_ON OCP current 14A
3
@ PR341 3
0_0402_5%
3.3V 1 2 FSW=390kHz
Peak Current 8A <29> VS_ON Delta I=2.791A,ripple=2.791*15m=41.865mV
4.7U_0805_25V6-K
100K_0402_5%
DCR 18~20mohm
1
OCP current 10A
PC343
@ PR332
Delta I=1.160A ,ripple=1.160 x17m=19.27mV 2 TYP MAX
FSW=455kHz H/S Rds(on) ::27mohm , 34mohm
1
@
DCR 35mohm +/-15% L/S Rds(on) :10.8mohm , 13.6mohm
TYP MAX
H/S Rds(on) :27mohm , 34mohm @ PJ332 @ PJ331
2 1 1 2
L/S Rds(on) :19mohm , 23.5mohm +3VLP 2 1 +3VL +3VALWP 1 2 +3VALW
JUMP_43X39 JUMP_43X118
(100mA,20mils ,Via NO.= 1) (8A,160mils ,Via NO.= 16)
@ PJ351
1 2
+5VALWP 1 2 +5VALW
JUMP_43X118
(12A,240mils ,Via NO.= 24)
4 4

3VALW/5VALW
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
A B C D
A
DDR controller (35.3), Support component (35.4)
EMI@ PL151
HCB2012KF-121T50_0805
EMI Part (47.1)
B+ 1 2 1.5V_B+ PR155
2.2_0603_5%
BST_1.5V-1 1 2 BST_1.5V +1.5V
PC152@EMI@
2200P_0402_50V7K
10U_0805_25V6K
DH_1.5V 1 @ 2 +0.75VSP
1
PR157 0_0603_5%
0.1U_0603_25V7K
PC154
2
PC155
10U_0603_6.3V6M
10U_0603_6.3V6M
SW_1.5V
1
PC159
PC160
1
5
DL_1.5V
16
17
18
19
20
PU150
2
BOOT
VTT
PHASE
UGATE
VLDOIN
21
AON7408L
PAD
PQ151
4 15 1
LGATE VTTGND
PR158 14 2
PL152 17.4K_0402_1% PGND VTTSNS
1
2
3
1UH_VMPI0703AR-1R0M-Z01_11A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC162 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
FDMC7692S_MLP8-5
VDDP VTTREF
220U_6.3V_M
PR159
1
1 5.1_0603_5%
+1.5VP
PQ152
1 2 VDD_1.5V 11 5
+ VDD VDDQ
PC157
PR156 EMI@ 4
PGOOD
1
4.7_1206_5%
TON
+5VALW PC163
FB
S5
S3
SNUB_+1.5VP 2
1
0.033U_0402_16V7K
2
PC164
1
2
3
10
6
1U_0603_10V6K
+5VALW
2
PR160
10.2K_0402_1%
FB_1.5V 2 1 +1.5VP
TON_1.5V
1
PC156 EMI@
680P_0402_50V7K
2
2
PR161
887K_0402_1% PR162
@ PR163 1.5V_B+ 1 2 10K_0402_1%
0_0402_5%
1 2 EN_1.5V
<29,31> SYSON
1
1 1
EN_0.75VSP
1
@ PC166 PR164
@PR164
@
@ PJ151 0.1U_0402_10V7K 0_0402_5%
2 1 1 2
2
2 1 <29,31> SUSP#
JUMP_43X118
@ PJ750 @ PJ152
1
2 1 2 1
+0.75VSP 2 1 +0.75VS +1.5VP 2 1 +1.5V @ PC167
JUMP_43X79 JUMP_43X118 0.1U_0402_10V7K
2
(0.5A,40mils ,Via NO.= 1) (12A, 480mils ,Via NO.= 24)
OCP=13.8A
1.5V
Peak Current 12A
OCP current 13.82A
FSW=500kHz
DCR 8.3 ~ 10mohm
TYP MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :10.8mohm , 13.6mohm
STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0 Hi Hi On On On
Off
S3 Lo Hi On On (Hi-Z)
S4/S5 Lo Lo Off Off Off

(Discharge) (Discharge) (Discharge) Security Classification Compal Secret Data Compal Electronics, Inc.
Note: S3 - sleep ; S5 - power off THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP/0.75VSP/1.8VSP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9869P 1.0
A
A B C D
1.8V controller (35.15), Support component (35.16)

1 1
+3VALW Need create Symbol.

Note:Iload(max)=3A 1.8V
PU450 PL451
Peak Current 2.5A
4
1UH_NRS4018T1R0NDGJ_3.2A_30%
3 1 2
OCP current 3.5A
22P_0402_50V8J
22U_0603_6.3V6M
IN LX +1.8VALWP FSW=800kHz
1
5 2
PG GND
PC458
1
6 1
PC450
PR451
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN 100K_0402_1% H/S Rds(on) :100mohm ,
2
SY8032ABC_SOT23-6 L/S Rds(on) :80mohm ,
1
PC452
PC451
FB=0.6V
@ PR452
2
0_0402_5%
1
<29> 1.8_0.95VALW_PWREN 1 2 +1.8_EN
PR453
49.9K_0402_1%
2
@ PC453
@ PJ451 0.1U_0402_16V7K
2
1 2
+1.8VALWP 1 2 +1.8VALW
2
JUMP_43X79 2
(2.5A,100mils ,Via NO.=5)
0.95V controller (35.5), Support component (35.6)

@ PR404
0_0402_5%
1 2 1.8_0.95VALW _PW REN
0.95V
2
Peak Current 11.1A
1
PR405
10K_0402_1% @ PC454 OCP current 16A
3 0.01U_0402_16V7K 3
FSW=800kHz
2
1
EMI Part (47.1)
@EMI@ PR401 @EMI@PC403 H/S Rds(on) :22mohm ,
PL402 EMI@
4.7_1206_5%
1
680P_0603_50V7K
2SNB_0.95V1 2
EMI Part (47.1) L/S Rds(on) :11mohm ,
HCB2012KF-121T50_0805 PU400
2 1 B+_0.95V 8 1 PC405
B+ IN EN 0.1U_0603_25V7K
10U_0805_25V6K
2200P_0402_50V7K
6 1 2 PL401
BS
1
1
PC410
1UH_PCMB063T-1R0MS_12A_20%
PC404
9 10 1 2
GND LX
LX_0.953V
+0.95VALWP
2
66.5K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
4700P_0402_50V7K
@EMI@
1
1
1
1
PR402
4
FB
PC409
PC408
PC407
PC406
PC412
PC401
3 7 +3VALW
+3VALW
1 2
2
2
2
ILMT BYP
2
2
2 5 FB=0.6V @
4.7U_0603_6.3V6K
2.2U_0603_6.3V6K
PG LDO
1
PC411
@ PJ1
1
PC402
SY8208DQNC_QFN10_3X3
2 1
+0.95VALW P 2 1 +0.95VALW
2
1K_0402_1%
PR403
2
JUMP_43X118
2
(11A,440mils ,Via NO.=22)
1
PR406
OCP=
100K_0402_1%
4 4
2

+1.8VALWP/+0.95VALWP
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9868P
A B C D
A B C D E
EMI Part (47.1)

<6> APU_VDD_SEN_L APU_VDD_SEN_H <6>
CPU controller (36.1),Driver (36.2) Support component (36.3)
1
0.01U_0402_50V7K
S TR MDU1516URH 1N POWERDFN56-8
PC503 PL501 EMI@
10_0402_5% 10_0402_5% HCB2012KF-121T50_0805
2
1 2 1 2
+APU_CORE
APU_B+ 1 2
B+
1
1
PR504 PR505
10U_0805_25V6K
10U_0805_25V6K
33U_D2_25VM_R60M @
@ PR506 @ PR507
PQ501
2200P_0402_50V7K
1 1
100U_25V_M
0_0402_5% 0_0402_5%
1
1
PC505
PC506
PC507
PC508
+ +
@EMI@PC534
PC534
PR569
2
2
2.2_0603_5%
1 UGATE_NB1 1 2 4 1
2
2
@EMI@
1 2 2 2
PC509 @ PR512 PL502

330P_0402_50V 2.2_0603_5% PC510 0.36UH_PDME064T-R36MS_24A_20%
3
2
1
PR513 PR515 BOOT_NB11 1 2
2 BOOT_NB1-1 4 1
+APU_CORE_NB
10K_0402_1% 82K_0402_1%
4.7_1206_5%
1 2 1 2 PR501 0.22U_0603_25V7K 3 2
APU_B+
1
EMI@ PR517
1 2 PR516
PQ502
PHASE_NB1 2.8K_0402_1%
MDU1512RH 1N POWERDFN56-8
PC513 PC511 110K_0402_1% 1 2 2 1
560P_0402_50V7K 68P_0402_50V8J
1 2 1 2 PC512
2
LGATE_NB1 4 .1U_0402_16V7K
SNB_APU_NB
680P_0603_50V7K
EMI@ PC514
PR518 @
VCC VCC 0_0402_5%
VCC VCC
3
2
1
2
1 2
TONSET
COMP
VSEN
ISEN1N
ISEN1P
FB
VCC
ISENA1N-1
ISENA1P
PR519
PU500 910_0402_1%
13
12
11
10
1
RT8880AGQW_QFN52_6X6 ISENA1N 1 2
PWM3
BOOT2
UGATE2
TONSET
COMP
FB
ISEN3P
ISEN1P
ISEN2P
VSEN
ISEN3N
ISEN1N
ISEN2N
0.1U_0402_25V6
1
PC515
RGND 53
GND
14 52 @PR502
@ PR502
APU_CORE_NB
2
RGND PHASE2
2
IMON 15 51 PVCC
0_0402_5%
1 2
TDC 13A(A) 12A(B) @ 2
+5VS
IMON LGATE2 Peak Current 17A(A) 15A(B)
VREF 16 50 PVCC
V064 PVCC VCC 1 2 OCP current > 22.5A
PC516 IMONA 17 49 LGATE1
IMONA LGATE1 Load line -4mV/A
2.2U_0603_10V7K
2.2U_0603_10V7K
1U_0402_6.3V6K+1.8VS PR520
1
1 2 VDDIO 18
VDDIO PHASE1
48 PHASE1 10_0603_5% FSW=400kHz
PC501
PC502
@ PR521 0_0402_5%
<6> APU_PWRGD
1 2 19 47 UGATE1 DCR 1.4mohm +/-5%
2
PWROK UGATE1
@ PR522 0_0402_5%
1 2 SVC 20 46 BOOT1 TYP MAX
<6> APU_SVC SVC BOOT1 EMI Part (47.1)
<6> APU_SVD
@
1
PR523 0_0402_5%
2 SVD 21 45 LGATE_NB1 H/S Rds(on) :11.7mohm , 14.5mohm
SVD LGATEA1
@
1
PR524 0_0402_5%
2 SVT 22 44 PHASE_NB1
L/S Rds(on) :4.2mohm , 5mohm
<6> APU_SVT
1000P_0402_50V7K
1000P_0402_50V7K
SVT PHASEA1
22K_0402_1%
APU_B+
35.7K_0402_1%
MDU1512RH 1N POWERDFN56-8 S TR MDU1516URH 1N POWERDFN56-8

1
1
OFS 23 43 UGATE_NB1
OFS UGATEA1
PR526
PR525
1000P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
OFSA 24 42 BOOT_NB1
OFSA BOOTA1
2200P_0402_50V7K
PC517
PC518
1
PQ503
SET1 25 41
VCC
PC526
2
2
SET1 PWMA2
1
PC519
PC520
@EMI@ PC522
PR527
PGOODA
ISENA2N
ISENA1N
ISENA2P
SET2 26 ISENA1P 40 1 2 APU_B+
PGOOD
PR570
COMPA
VSENA
OCP_L
2
@ @ SET2 TONSETA 2.2_0603_5%

IBIAS
VCC
2
FBA
EN 110K_0402_1% UGATE1 1 2 4
PR530 PR531 PHASE1

27
28
29
100K_0402_5% COMPA 30
31
32
33
34
35
36
37
38
1.58K_0402_1% 5.23K_0402_1% 39 PR533 PL503

100K_0402_1%_TSM0B104F4251RZ
22.6K_0402_1%
2 1 2 1 @PR532
@ PR532 2.2_0603_5% 0.36UH_PDME064T-R36MS_24A_20%
VGATE <29>
3
2
1
ISENA1N
100K_0402_1%_TSM0B104F4251RZ
ISENA1P
18.7K_0402_1%
0_0402_5% BOOT1 1 1
2 BOOT1-1 2 4 1
2 IBIAS
+APU_CORE
VSENA
1
1
VCC
FBA
1 2 VR_HOT
PR540 EMI@
PR537
PH501
PR534
PR535
4.7_1206_5%
3 PC523 3 2 3
5
5
<29,6> APU_PROCHOT#
PH502
1 2 0.22U_0603_25V7K
+3VS
PQ506
1
PQ504
PR536
PR541
VCC 2.8K_0402_1%
2
2
VREF 100K_0402_5% 1 2 2 1
0_0402_5% @ PR542 VR_ON <29>
@PR542 @
1
1 2 LGATE1 4 4 PC524
1 2
0.47U_0402_16V4Z
SNB_APU .1U_0402_16V7K
1
680P_0603_50V7K
PC525
EMI@ PC527
1
PC521
3
2
1
2
3
2
1
2
PC528 PC529 0.1U_0402_25V6 ISEN1P
2
68P_0402_50V8J 560P_0402_50V7K
ISEN1N-1
1 2 1 2
PR547
PR544 PR546 @ PC531 910_0402_1%
115K_0402_1% 10K_0402_1% 330P_0402_50V 1
ISEN1N 2
2 1 2 1 2 1
0.1U_0402_25V6
OFS
APU_core
1
PR548 PR550
1
PC530
C530
6.34K_0402_1%
1 2
20K_0402_5%
1 2 PR558
TDC 15A(A) 13A(B)
@ PR557
2
Peak Current 21A(A) 18A(B)
@
0_0402_5%
P
PR553 PR554 PR555 0_0402_5%
+5VS
6.34K_0402_1% 120_0402_1% 20K_0402_5% OCP current > 31.5A
2
1 2 1 2 1 2 PR559
RGND
2 1 Load line -4mV/A

OFSA
+APU_CORE_NB
FSW=400kHz
2
10_0402_5%
PC533 DCR 1.4mohm +/-5%
0.01U_0402_50V7K
1
4 TYP MAX 4
SET1
PR561 PR563 H/S Rds(on) :11.7mohm , 14.5mohm

53.6K_0402_1% 124K_0402_1%
1 2 1 2 L/S Rds(on) :4.2mohm , 5mohm
PR565 PR567 +5VS <6> APU_VDDNB_SEN_H
470_0402_1% 124K_0402_1%
1 2 1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/27 Title
SET2
Deciphered Date
+CPU_CORE/VDDNBP
Custom LA9868P 1.0
A B C D E
5 4 3 2 1
D D
VGA controller (43.1),Driver (43.2) Support component (43.3)

EMI Part (47.1)
PL801 VGA@
HCB2012KF-121T50_0805
+VGA_CORE
B+
1 2 GPU_B+ TDC 21A
EDC 31.5A
1
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
PR802
@EMI@ PC802 VGA@ PR801 1_0603_5% OCP current ??A
VGA@ PC803
VGA@ PC804
0.22U_0603_25V7K
1
1
1_0603_5%
FSW=??kHz
VGA@ PC807
+5VALW 1 2
1 2
DCR 1.4m ohm +-5%
2
1
VGA@ PC806
1U_0603_6.3V6M TYP MAX
H/S Rds(on) :11.7mohm , 14mohm
2
VGA@
PR804
10_0402_5% +5VALW L/S Rds(on) :2.7mohm , 3.3mohm
S TR MDU1516URH 1N POWERDFN56-8
2 1 GPU_ISUM+
5
VGA@ PC809 VGA@ PR805 VGA@PC810
VGA@ PC810
1000P_0402_50V7K GPU_ISUM- 2.2_0603_5% 0.1U_0603_25V7K
1
2 1 BST_GPU 2 1 2 1
VGA@ PQ801
<16> VSS_GPU_SENSE PR841 VGA@
VGA@ PC812
2
C 0_0402_1% C
330P_0402_50V7K 4
<16> VCC_GPU_SENSE 2 1
29
10
11
12
13
14
1
2
8
9
+VGA_CORE VGA@
PC811
AGND
RTN
ISUM+
VDD
VIN
IMON
BOOT
ISUM-
1 2 330P_0402_50V7K VGA@
3
2
1
VGA@ PR806 VGA@ PL802
10_0402_5%
7 15 DH_GPU 0.36UH_PDME064T-R36MS_24A_20%
VSEN UGATE
6 16 LX_GPU 1 4
FB PHASE +VGA_CORE
5
5 17 2 3
COMP VSSP
1
@EMI@
4 VGA@ PU801 18 DL_GPU PR808
PQ802
VGA@ PQ803
VW LGATE
1
ISL62881CHRTZ-T_TQFN28_4X4 4.7_1206_5%
VGA@ 2 1 3 19 VGA@ PR810
PR813 @ PR811
390U_2.5V_M
1
390U_2.5V_M
VGA@ PR812 VGA@ VGA@PR809 RBIAS VCCP 1
226K_0402_1% PC815 4 4 3.65K_0805_1% 0_0402_5%
VGA@
2
2.37K_0402_1% 1000P_0402_50V7K 47K_0402_1% 2 20 + +
VGA@ PC899
VGA@ PC900
1 2 1 2 1 2 2 1 PGOOD VID0 2 1
+5VALW @EMI@
2
147K for CPU 1 21 PR814 VGA@ PR815 VGA@ PH7
VGA@
DPRSLPVR
CLK_EN# VID1
2
PC814 1_0603_5% PC816 1 2 1 2 2 2
47K for GPU
3
2
1
3
2
1
1
390P_0402_50V7K 680P_0603_50V7K
VR_ON
+3VS VGA@
2.61K_0402_1% 10KB_0402_5%_ERTJ1VR103J
VID6
VID5
VID4
VID3
VID2
1
VGA@ PC819 PC817
2
56P_0402_50V8 2.2U_0603_6.3V6K B value:4250K±2%
1 2 1 2 1 2 2 1
28
27
26
25
24
23
22
1 2
VGA@PR816 VGA@ PR817 VGA@ VGA@PR818
VGA@PR818
VGA@ Rds(on):2.7mΩ~3.3mΩ
1
PC818 715_0402_1% 8.06K_0402_1% 11K_0402_1%

VGA@ +3VGS
1000P_0402_50V7K PR835 Layout Note:
VGA@ PR718
0.1U_0402_16V7K
120K_0402_1%
1.8K_0402_1% Place near Choke 1 2
PR829 0_0402_5%
2
1
1
1
VGA@ PC820
VGA@ PR832
VGA@ PR823
@ PR830
VGA@ PR831
@ PR833
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
0.047U_0402_16V7K
2
B <15,8> VGA_PWRGD B
1 2
2
2
1
VGA@ PC823
VGA@ PC821
0.1U_0402_16V7K
1
2
1
@
GPIO6 GPIO30 GPIO29 GPIO20 GPIO15 VGA@ PR822
VID5 VID4 VID3 VID2 VID1 VDDC
1.2K_0402_1%
0 1 1 1 0 1.15V GPU_ISUM+
2
0 1 1 1 1 1.125V
<13>
GPU_ISUM-
GPU_DPRSLPVR
VGA@ 1PC822 0.1U_0402_16V7K
1 0 0 0 0 1.100V
1
1
0_0402_5%
1 0 0 0 1 1.075V
0_0402_5%
0_0402_5%
@ PR836
VGA@ PR837
@ PR838
PR839
VGA@ PR840
0_0402_5%
0_0402_5%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
1 0 0 1 0 1.050V
PR828
@
2
2
2
2
2
1
1 0 0 1 1 1.025V
2
2
1
PR824
PR826
PR821
0 0 0 1.000V
VGA@ 47K_0402_1%
PR827
PR825
1 1
1 0 1 0 1 0.975V
1
1
1
1
2
2
@ @ @
1 0 1 1 0 0.950V Default @ @
1 0 1 1 1 0.925V
1 1 0 0 0 0.900V
<14,8>
<13>
PXS_PWREN
GPU_VID1
<13>
<13>
<13>
<13>
GPU_VID4
GPU_VID2
GPU_VID3
1 1 0 0 1 0.875V
GPU_VID5
1 1 0 1 0 0.850V
1 1 0 1 1 0.825V
A 1 1 1 0 0 0.800V A
1 1 1 0 1 0.775V

+VPU_COREP
C 1.0
LA-9868P
5 4 3 2 1
A
B
C
D
@
PC1006
0.22U_0402_16V7K
2 1
2
1
+
PC1019 2 1 2 1 2 1
PC1100 180P_0402_50V8J
560U_D2_2VM_R4.5M 2 1 1U_0402_6.3V6K 1U_0402_6.3V6K PC1000
PC1014 PC1004 10U_0603_6.3V6M
+APU_CORE
5
5
+APU_CORE
2 1 2 1 2 1
2
1
+
1U_0402_6.3V6K 1U_0402_6.3V6K PC1001
PC1101
330U_D2_2V_Y PC1015 PC1010 10U_0603_6.3V6M
Local
2 1 2 1 2 1
1U_0402_6.3V6K 1U_0402_6.3V6K
2
1
+
PC1016 PC1002
PC1011
@
PC1102 10U_0603_6.3V6M
330U_D2_2V_Y
2 1 2 1
+APU_CORE
1U_0402_6.3V6K 1U_0402_6.3V6K
PC1017 PC1012
2 1 2 1 2 1
4
4
1U_0402_6.3V6K 1U_0402_6.3V6K
1U_0402_6.3V6K
PC1018 PC1013
PC1003
CPU_Core output CAP (Including MLCC) 36.4
VGA@ PC1069 VGA@ PC1050 VGA@PC1076

VGA@ PC1076 VGA@PC1043
VGA@ PC1043
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1
VGA@ PC1060 VGA@ PC1051 VGA@ PC1077 VGA@PC1042

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M PC1036
2 1 2 1 2 1 2 1 180P_0402_50V8J
2 1
+VGA_CORE
VGA@ PC1068 VGA@PC1052

VGA@ PC1052 VGA@ PC1078 VGA@PC1040
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 2 1
2 1 2 1 2 1 2 1
PC1005
10U_0603_6.3V6M
VGA@
PC1061 VGA@ PC1053 VGA@ PC1044 VGA@ PC1041
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1 2 1 2 1 2 1
Issued Date
+VGA_CORE
2 1
VGA@ PC1062 VGA@ PC1054 VGA@ PC1045
Security Classification
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K PC1007
+VDDC
+APU_CORE_NB
2 1 2 1 2 1 10U_0603_6.3V6M
2 1
3
3
VGA@ PC1063 VGA@ PC1055 VGA@ PC1079 PC1008

+APU_CORE_NB
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M

2 1 2 1 2 1
VGA@PC1064
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 2 1
2012/09/27
2 1 2 1 2 1
PC1009
10U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1 2 1

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2 1 2 1 2 1 560U_D2_2VM_R4.5M
Local
PC1032
VDD
kabini

VDD_NB
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

2
1
+
2 1 2 1 2 1
Compal Secret Data

Deciphered Date
PC1033
@
330U_D2_2V_Y
2
1
+
2 1 2 1
2
2
1
2
1U_0402_6.3V6K 1U_0402_6.3V6K
PC1025 PC1020
+APU_CORE_NB
560uF*4.5m
2 1 2 1
1U_0402_6.3V6K 1U_0402_6.3V6K
PC1026 PC1021
10uF
A3
4
3
Size
Title
Date:
(0603)
2 1 2 1
1U_0402_6.3V6K 1U_0402_6.3V6K
1u
PC1027 PC1022
GFX output CAP (Including MLCC) 36.5
Document Number
11
(0402)
Thursday, May 16, 2013
2 1 2 1
VGA_Core output CAP (Including MLCC 43.9)
LA-9868P
1U_0402_6.3V6K 1U_0402_6.3V6K
PC1023
1
1
PC1028
Sheet
0.22uF
40
2 1 2 1
of
1U_0402_6.3V6K 1U_0402_6.3V6K
Compal Electronics, Inc.
1
1
PC1024
@
PC1029
180P
42
(0402)
PROCESSOR DECOUPLING
Rev
1.0
A
B
C
D
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
D D
PIR_VNKAE_DIS-UMA1226.xlsx (命令列)
C C
B B
A A

PIR (PWR)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VCUAA 1.0
5 4 3 2 1
5 4 3 2 1
HW PIR (Product Improve Record)

VNKAE LA-9868P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3 TO 1.0
-----------------------------------------------------------------------------------------------------------------------------------
Item Page Date Request Solution
-----------------------------------------------------------------------------------------------------------------------------------
D 1 2013/03/5a Change APU to PR sample PR sample PN SA00006R300, SKU 4519NL51L03 D
2 P30 2013/03/5a PCB cut outline Remove SW1

3 P06 2013/03/5a co-lay eDP & LVDS Due to common eDP cable, swap Lane0 and Lane2 to follow common design; replace CC106, CC102 with RC75, RC76; add RC77, RC78, CC109, CC110.
4 P30 2013/03/06a no need power button Remove SW2
5 P30 2013/03/06a Add C24(0.1uF) to ON/OFFBTN# and set to ESD@
6 P06 2013/03/06a Add CC99(1000pF) to APU_RST# and set to ESD@
7 2013/03/06a Change CC93, CC94, CC97, CB6 to ESD@
8 P07 2013/03/06a BIOS ROM Change UC5 to always mount on 43-level
9 P07 2013/03/06a For vendor recommand Change CC22, CC23 from 5.6pF to 4.7pF(SE07147AC80)
10 P28 2013/03/07a co-lay card reader for EMI request Update card reader schematic for co-lay GL834L and RT5117
11 P09 2013/03/07b Remove 0ohm res Change RC116, RC117, RC119, RC120 to short pad symbol
12 P26 2013/03/07b Remove 0ohm res Change RA18, RA24, RA22, RA36, RA37 to short pad symbol
13 P05 2013/03/07b Remove 0ohm res Change R2 to short pad symbol
14 P20 2013/03/07b Remove 0ohm res Remove R106
15 P29 2013/03/07b Remove 0ohm res Change RB36 to short pad symbol
16 2013/03/11a Update power schematic
17 P28 2013/03/12a Remove co-lay RT5117 Update card reader schematic
18 P30 2013/03/18a Change PCB PN Change PCB PN to DAZ0WJ00100
19 P30 2013/03/18a Remove DC-IN JACK PN due to BOM structure changed
20 P24 2013/03/18a Remove 0ohm res Change RR1, RR2 to short pad symbol
C 21 P08 2013/03/18a For power consumption improve Change VRAM_SEL to TOUCH_SEL for BTO to improve battery life. C
22 P26 2013/03/25a ESD request Change DA1, CA30, CA31, CA34, CA36 to varistor(SCV00001K00)
23 P08 2013/03/25a vendor recommand Change CC31 to 8pF(SE00000DB80)
24 P24 2013/03/25a Remove 0ohm res Change RR1, RR2 to 0 ohm
B B
A A
Title
HW PIR

B LA-9868P 1.0

5 4 3 2 1
www.s-manuals.com

La 9868P

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La 9868P

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A B C D E

LA-9868P REV 1.0 Schematic

AMD KABINI Quad Core 15W for DIS&UMA

Security Classification Compal Secret Data Compal Electronics, Inc.

AMD Sun Pro M2, 64bit with 2GB DDR3(4Gbit)

CRT Conn DAC

SATA port 0 SATA HDD

RTL8106E 10/100M PCIe Gen1 X1

SPI ROM APU SMBus

DC/DC Interface CKT. Touch Pad Int.KBD G-Sensor

Power Circuit DC/DC USB2.0&LAN/B

DESIGN CURRENT 0.15A +3VL

N-CHANNEL DESIGN CURRENT 4A +5VS

N-CHANNEL DESIGN CURRENT 2A +5VS_ODD

P-CHANNEL DESIGN CURRENT 330mA +3VALW_APU

N-CHANNEL DESIGN CURRENT 4A

P-CHANNEL DESIGN CURRENT 1.5A

DESIGN CURRENT 2A +3V_WLAN

Ipeak=12A, Imax=8.4A, Iocp min=13.8A +1.5V

N-CHANNEL DESIGN CURRENT 2A

N-CHANNEL DESIGN CURRENT 2A

Voltage Rails ( O MEANS ON X MEANS OFF )

S1(Power On Suspend) HIGH HIGH

S3 (Suspend to RAM) LOW HIGH

S4 (Suspend to Disk) LOW HIGH

APU SM Bus Address (SCL0/SDA0)

Security Classification Compal Secret Data Compal Electronics, Inc.

<10,11> DDR_AB_DQS#[0..7] DDR_AB_D[0..63] <10,11>

+MEM_VREF RC7 1 2 1K_0402_5% MEM_MAB_EVENT#

EDP_LCD_TXOUT0+_R 1 2 0.1U_0402_16V7K EDP_LCD_TXOUT2+

Security Classification Compal Secret Data

SW said ROM can change to 4MB

RC96 1 @ 2 10K_0402_5% HDA_BITCLK 32K_X1 AJ2 X32K_X1 +3VS

CC30 1 2 10P_0402_50V8J 32K_X1

CC31 1 2 32.768KHZ_7PF_Q13MC1461000100 32K_X2 RPC6 Control by X76

<29,7> CLK_PCI_EC ODD_DA#_APU 1 2 ESD@ CC32 QC1A

AMD CKL v1.01 10uF 0.1uF 180pF

VSS_36 VSS_98 VSS_160 VSS_222

VDD_095_USB3_DUAL_3 VDD_095_3 VSS_60 VSS_122 VSS_184

+0.95VALW_APU FT3 REV 0.51 FT3 REV 0.51

1 1 AJ13 VDD_095_ALW_4 VDD_095_9 AM25

FT3 REV 0.51

CH751H-40PT_SOD323-2 route to 20mil

2 +0.75VS VTT VTT +0.75VS

207 GND1 GND2 208

DDR_AB_D0 5 VSS DQ4 6 DDR_AB_D5

2 +0.75VS VTT VTT +0.75VS

PCIE_ATX_C_GRX_P[3..0] UV1A PCIE_GTX_C_ARX_P[3..0]

PCIE_ATX_C_GRX_P2 W38 U33 PCIE_GTX_ARX_P2 .1U_0402_16V7K CV5 1 2 VGA@ PCIE_GTX_C_ARX_P2 AK35

K35 L30 VGA@ SUN-PRO M2_FCBGA962

VGA@ SUN-PRO M2_FCBGA962

skHynix H5TQ2G63DFR-11C 1.5V/900MHz 000 NC 4750

+3VS Samsung K4W2G1646E-BC11 1.5V/900MHz 111 4750 NC

<8> PXS_RST# B 4 GPU_RST#

Security Classification Compal Secret Data Compal Electronics, Inc.

are used as voltage control signals.

JTAG_TDI AN23 JTAG_TDI AL19 Serial-ROM input to ROM.

GPIO_28_FDO MLPS AL30 PD-reset

1 1 1 a critical temperature so that the motherboard can

0.1u 1 1 advisory for AMD PowerPlay states for more details.

On/off regulator switch in AMD PowerXpress? (switchable

RV31 1 VGA@ 2 1M_0402_5%

+0.95VGS AK10 Debug Only, for clock observation