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Computer Language and Assembly

Research work for Midterms

Submitted by: Bernie Joshua San Pablo

Submitted to: Lilibeth Calpito
DATA TRANSFER INSTRUCTION
XCHG – Exchange Instruction
DESCRIPTION: The XCHG Instruction – The exchange (XCHG) instruction can be used to swap data
between two general-purpose registers or between a general purpose register and a storage
location in memory. This does not accept immediate operands.
SYNTAX: XCHG reg, reg
XCHG reg, mem
XCHG mem, reg

XCHG AX, VAR

Is equivalent to:

MOV DX, AX ; DX is a temporary register

MOV AX, VAR
MOV VAR, DX

SAMPLE INSTRUCTION:
1.) XCHG AH, BL
Before After
AH= 1A, AL= 00 AH=05, AL=00
BH=00, BL =05 BH=00, BL=1A

What is the result of executing the following instruction?

XCHG [SUM], BX
where SUM = 123416, (DS)=120016
Solution:
((DS)0+SUM) (BX)
PA = 1200016 + 123416=1323416
Execution of the instruction performs the following 16-bit swap:
(1323416) (BL)
(1323516) (BH)
So we get (BX) = 00FF16, (SUM) = 11AA16

PUSH and POP INSTRUCTION

DESCRIPTION: The PUSH and POP instructions are used for data transfer to and from a stack. The
stack is a memory location used for temporary data storage. The top of the stack address is
managed automatically, by hardware, through a register that points to the top of the stack,
namely SP register.
SYNTAX:
• PUSH syntax:
– PUSH r/m16
– PUSH r/m32
– PUSH imm32
• POP syntax:
– POP r/m16
– POP r/m32

SAMPLE INSTRUCTION:
PUSHFD and POPFD
– push and pop the EFLAGS register
– LAHF, SAHF are other ways to save flags
• PUSHAD pushes the 32-bit general-purpose
registers on the stack in the following order
– EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI
• POPAD pp g o s the same registers off the stack in
reverse order
– PUSHA and POPA do the same for 16-bit registers
Example:

; Save the AX and BX registers in the stack

PUSH AX
PUSH BX

; Use the registers for other purpose

MOV AX, VALUE1
MOV BX, VALUE2
...
MOV VALUE1, AX
MOV VALUE2, BX

; Restore the original values

POP AX
POP BX
PUSH AX
Before Execution After Execution
SP= 000Ah SP= 0008h

POP AX
Before Execution After Execution
SP= 0008h SP= 000Ah
ARITHMETIC INSTRUCTIONS
ADC – Add with carry.
Description: The basic purpose of this instruction is to add two 16-bit operands. One of the
operands must first be loaded into the accumulator, such as by means of execution of a load-
accumulator instruction. The add instruction then provides the address of the other operand,
which must be in main storage. Addition takes place, and the result is placed in the accumulator:

ADC destination ,source

Destination= destination + source + carry flag value
Syntax:
ADC AX
ADD AX
ADD BX
SAMPLE INSTRUCTION:
This instruction performs the same operation as ADD instruction, but adds the carry
flag to the result.

1.)
ADC 0100H
ADC AX, BX
ADC AX, [SI]
ADC AX, [5000]
ADC [5000], 0100H
Example:
0 000 0000 1001 1101 = Contents of accumulator
+0 000 0010 0011 0101 = Contents of storage location addressed by add
0 000 0010 1101 0010 = Result loaded into accumulator

2.)
DX= 6125h, BX= 3745h
ADC DX, BX
Convert into binary first to get the carry flag
DX = 0110 0001 0010 0101 = equivalent value of 6125h in binary
+ BX = 0011 0111 0100 0101 = equivalent value of 375h in binary
1001 1000 0110 1010
+ 0 = since Carry Flag is zero.
1001 1000 0110 1010
DX = 986Ah
DAA – Decimal Adjust for Addition.
DESRIPTION: DAA (Decimal Adjust after Addition) adjusts the result of adding two valid packed
decimal operands in AL. DAA must always follow the addition of two pairs of packed decimal
numbers (one digit in each half-byte) to obtain a pair of valid packed decimal digits as results. The
carry flag is set if carry was needed.
SYNTAX:
ADD CL
ADD DL
SIMPLE INSTRUCTION: This instruction is used to convert the result of the addition of two packed
BCD numbers to a valid BCD number. The result has to be only in AL.
EXAMPLE:
AL = 53 CL = 29
ADD AL, CL ; AL <– (AL) + (CL)
; AL 53 + 29
; AL 7C
DAA ; AL 7C + 06 (as C>9)
; AL 82
AAA – ASCII ADJUST FOR ADDITION
DESCRIPTION: Numerical data coming into a computer from a terminal is usually in ASCII code. In
this code, the numbers 0 to 9 are represented by the ASCII codes 30H to 39H. The 8086 allows
you to add the ASCII codes for two decimal digits without masking off the “3” in the upper nibble
of each. After the addition, the AAA instruction is used to make sure the result is the correct
unpacked BCD.
SYNTAX:
ADD CL
ADD DL
SIMPLE INSTRUCTION: The AAA instruction is executed after an ADD instruction that adds two ASCII
coded operand to give a byte of result in AL. The AAA instruction converts the resulting contents
of Al to a unpacked decimal digits.
EXAMPLE:
ADD CL, DL ; [CL] = 32H = ASCII for 2
; [DL] = 35H = ASCII for 5
; Result [CL] = 67H
MOV AL, CL ; Move ASCII result into AL since
; AAA adjust only [AL]
AAA ; [AL]=07, unpacked BCD for 7
SBB – SUBTRACT WITH BORROW
DESCRIPTION: These instructions subtract the number in some source from the number in some
destination and put the result in the destination. The SBB instruction also subtracts the content of
carry flag from the destination. The source may be an immediate number, a register or memory
location. The destination can also be a register or a memory location. However, the source and
the destination cannot both be memory location.
SYNTAX: SBB Destination
SIMPLE INSTRUCTION: The subtract with borrow instruction subtracts the source operand and the
borrow flag (CF) which may reflect the result of the previous calculations, from the destination
operand
EXAMPLE:
SBB AX, 0100H
SBB AX, BX
SBB AX, [5000H]
SBB [5000H], 0100H
DAS – DECIMAL ADJUST FOR SUBTRACTION
DESCRIPTION: This instruction is used after subtracting one packed BCD number from another
packed BCD number, to make sure the result is correct packed BCD. The result of the subtraction
must be in AL for DAS to work correctly.
SYNTAX: AAA instruction
SIMPLE INSTRUCTION: This instruction converts the result of the subtraction of two packed BCD
numbers to a valid BCD number. The subtraction has to be in AL only.
EXAMPLE:
AL = 75, BH = 46
SUB AL, BH ; AL 2F = (AL) – (BH)
; AF = 1
DAS ; AL 29 (as F>9, F – 6 = 9)
AAS - ASCII ADJUST FOR SUBTRACTION
DESCRIPTION: Numerical data coming into a computer from a terminal is usually in an ASCII code.
In this code the numbers 0 to 9 are represented by the ASCII codes 30H to 39H. The 8086 allows
you to subtract the ASCII codes for two decimal digits without masking the “3” in the upper
nibble of each. The AAS instruction is then used to make sure the result is the correct unpacked
BCD.
SYNTAX: AAS
SAMPLE INSTRUCTION: This instruction corrects the result in AL register after subtracting two
unpacked ASCII operands. The result is in unpacked decimal format.
The procedure is similar to AAA instruction except for the subtraction of 06 from AL.
MUL- UNSIGNED MULTIPLY
DESCRIPTION: This instruction multiplies an unsigned byte in some source with an unsigned byte
in AL register or an unsigned word in some source with an unsigned word in AX register. The source
can be register or a memory location. When a byte is multiplied by the content of AL, the result
(product) is put in AX. When a word is multiplied by the content of AX, the result is put in DX and
AX registers. If the most significant byte of a 16 bit- result or the most significant word of a 32-bit
is 0, CF and OF will both 0’s AF, PF, SF and ZF are undefined after a MUL instruction.
If you want to multiply a byte with a word, you must first move the byte to a word location such
as an extended register and fill the upper byte of the word with all 0’s. You cannot use the CBW
instruction for this, because the CBW instruction fills the upper byte with copies of the most
significant bit of the lower byte.

 MUL BH Multiply AL with BH; result in AX

 MUL CX Multiply AX with CX; result high word in DX, low word in AX
 MUL BYTE PTR [BX] Multiply AL with byte in DS pointed to by [BX]
 MUL FACTOR [BX] Multiply AL with byte at effective address FACTOR [BX], if it is
declared as type byte with DB. Multiply AX with
word at effective address FACTOR [BX], if it is declared as
type word with DW.
 MOV AX, MCAND_16 Load 16-bit multiplicand into AX
MOV CL, MPLIER_8 Load 8-bit multiplier into
CL MOV CH, 00H Set upper byte of CX to
all 0’s
MUL CX AX times CX; 32-bit result in DX and AX
IMUL – Integer Multiplication

This instruction multiplies a signed byte from source with a signed byte in AL or a signed word
from some source with a signed word in AX. The source can be a register or a memory location.
When a byte from source is multiplied with content of AL, the signed result (product) will be put
in AX. When a word from source is multiplied by AX, the result is put in DX and AX. If the
magnitude of the product does not require all the bits of the destination, the unused byte / word
will be filled with copies of the sign bit. If the upper byte of a 16-bit result or the upper word of a
32-bit result contains only copies of the sign bit (all 0’s or all 1’s), then CF and the OF will both be
0; If it contains a part of the product, CF and OF will both be 1. AF, PF, SF and ZF are undefined
after IMUL.

If you want to multiply a signed byte with a signed word, you must first move the byte into a
word location and fill the upper byte of the word with copies of the sign bit. If you move the byte
into AL, you can use the CBW instruction to do this.

IMUL BH Multiply signed byte in AL with signed byte in

BH; result in AX.
IMUL AX Multiply AX times AX; result in DX and AX
MOV CX, MULTIPLIER Load signed word in CX
MOV AL, MULTIPLICAND Load signed byte in AL
CBW Extend sign of AL into AH
 IMUL CX Multiply CX with AX; Result in DX and AX

DIV – Unsigned Divide

This instruction is used to divide an unsigned word by a byte or to divide an unsigned double
word (32 bits) by a word. When a word is divided by a byte, the word must be in the AX register.
The divisor can be in a register or a memory location. After the division, AL will contain the 8-bit
quotient, and AH will contain the 8-bit remainder. When a double word is divided by a word, the
most significant word of the double word must be in DX, and the least significant word of the
double word must be in AX. After the division, AX will contain the 16-bit quotient and DX will
contain the 16-bit remainder. If an attempt is made to divide by 0 or if the quotient is too large
to fit in the destination (greater than FFH / FFFFH), the 8086 will generate a type 0 interrupt. All
flags are undefined after a DIV instruction.

If you want to divide a byte by a byte, you must first put the dividend byte in AL and fill AH with
all 0’s. Likewise, if you want to divide a word by another word, then put the dividend word in AX
and fill DX with all 0’s.

DIV BL Divide word in AX by byte in BL; Quotient in AL, remainder in AH

 DIV CX Divide down word in DX and AX by word in CX;
Quotient in AX, and remainder in DX.
DIV SCALE [BX] AX / (byte at effective address SCALE [BX]) if SCALE [BX] is of type
byte; or (DX and AX) / (word at effective address SCALE[BX] if
SCALE[BX] is of type word

IDIV – Integer Division

This instruction is used to divide a signed word by a signed byte, or to divide a signed double
word by a signed word.

When dividing a signed word by a signed byte, the word must be in the AX register. The divisor
can be in an 8-bit register or a memory location. After the division, AL will contain the signed
quotient, and AH will contain the signed remainder. The sign of the remainder will be the same
as the sign of the dividend. If an attempt is made to divide by 0, the quotient is greater than 127
(7FH) or less than –127 (81H), the 8086 will automatically generate a type 0 interrupt.
When dividing a signed double word by a signed word, the most significant word of the dividend
(numerator) must be in the DX register, and the least significant word of the dividend must be in
the AX register. The divisor can be in any other 16-bit register or memory location. After the
division, AX will contain a signed 16-bit quotient, and DX will contain a signed 16-bit remainder.
The sign of the remainder will be the same as the sign of the dividend. Again, if an attempt is
made to divide by 0, the quotient is greater than +32,767 (7FFFH) or less than –32,767 (8001H),
the 8086 will automatically generate a type 0 interrupt.

All flags are undefined after an IDIV.

If you want to divide a signed byte by a signed byte, you must first put the dividend byte in AL
and signextend AL into AH. The CBW instruction can be used for this purpose. Likewise, if you
want to divide a signed word by a signed word, you must put the dividend word in AX and extend
the sign of AX to all the bits of DX. The CWD instruction can be used for this purpose.

 IDIV BL Signed word in AX/signed byte in BL

 IDIV BP Signed double word in DX and AX/signed word in BP
 IDIV BYTE PTR [BX] AX / byte at offset [BX] in DS

LOGIC INSTRUCTION
NEG – NEGATE INSTRUCTION
DESCRIPTION: This instruction replaces the number in a destination with its 2’s complement. The
destination can be a register or a memory location. It gives the same result as the invert each bit
and add one algorithm. The NEG instruction updates AF, AF, PF, ZF, and OF.
SYNTAX: : NEG Destination

SIMPLE INSTRUCTION:
Negate. Makes operand negative (two's complement).
Algorithm:
Invert all bits of the operand
Add 1 to inverted operand
EXAMPLE:
MOV AL, 5 ; AL = 05h
NEG AL ; AL = 0FBh (-5)
NEG AL ; AL = 05h (5)

AND – LOGICAL AND

DESCRIPTION: This instruction ANDs each bit in a source byte or word with the same numbered
bit in a destination byte or word. The result is put in the specified destination. The content of the
specified source is not changed.
SYNTAX: AND Destination
SIMPLE INSTRUCTION:
Logical AND between all bits of two operands. Result is stored in operand1.
These rules apply:
1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0
EXAMPLE:
MOV AL, 'a' ; AL = 01100001b
AND AL, 11011111b ; AL = 01000001b ('A')
RET

OR – LOGICAL OR
DESCRIPTION: This instruction ORs each bit in a source byte or word with the same numbered bit
in a destination byte or word. The result is put in the specified destination. The content of the
specified source is not changed. The source can be an immediate number, the content of a
register, or the content of a memory location. The destination can be a register or a memory
location.
SYNTAX: OR Destination
SIMPLE INSTRUCTION:
Logical OR between all bits of two operands. Result is stored in first operand.
These rules apply:
1 OR 1 = 1
1 OR 0 = 1
0 OR 1 = 1
0 OR 0 = 0
EXAMPLE:
MOV AL, 'A' ; AL = 01000001b
OR AL, 00100000b ; AL = 01100001b ('a')
RET

XOR – LOGICAL XOR

DESCRIPTION: This instruction Exclusive-ORs each bit in a source byte or word with the same
numbered bit in a destination byte or word. The result is put in the specified destination. The
content of the specified source is not changed. The source can be an immediate number, the
content of a register, or the content of a memory location.
SYNTAX: XOR Destination
XOR CL, BH
XOR BP, DI
XOR WORD PTR [BX], 00FFH
SIMPLE INSTRUCTION:
Logical XOR (Exclusive OR) between all bits of two operands. Result is stored in first operand.
These rules apply:
1 XOR 1 = 0
1 XOR 0 = 1
0 XOR 1 = 1
0 XOR 0 = 0
EXAMPLE:
Operand1: 0101
Operand2: 0011
After XOR -> Operand1: 0110

NOT – LOGICAL NOT

DESCRIPTION: Logical NOT results in a true if the operand is false and vice versa.
SYNTAX: NOT Destination
SAMPLE INSTRUCTION:
The NOT instruction implements the bitwise NOT operation. NOT operation reverses the bits in an
operand. The operand could be either in a register or in the memory.
EXAMPLE:
Operand1: 0101 0011
After NOT -> Operand1: 1010 1100

TEST – TEST INSTRUCTION

DESCRIPTION: Computes the bit-wise logical AND of first operand (source 1 operand) and the
second operand (source 2 operand) and sets the SF, ZF, and PF status flags according to the result.
The result is then discarded.
SYNTAX: TEST Destination
SAMPLE INSTRUCTION:
Logical AND between all bits of two operands for flags only. These flags are effected: ZF, SF, PF.
Result is not stored anywhere.
These rules apply:
1 AND 1 = 1
1 AND 0 = 0
0 AND 1 = 0
0 AND 0 = 0
EXAMPLE:
TEST AL, 01H
JZ EVEN_NUMBER

SHIFT INSTRUCTION
SHL – SHIFT LOGICAL LEFT
DESCRIPTION: A shift left logical of one position moves each bit to the left by one. The low-order
bit (the right-most bit) is replaced by a zero bit and the high-order bit (the left-most bit) is
discarded. Shifting by two positions is the same as performing a one-position shift two times.
SYNTAX: SHL destination,
SAMPLE INSTRUCTION:
Shift operand1 Left. The number of shifts is set by operand2.
Algorithm:
Shift all bits left, the bit that goes off is set to CF.
Zero bit is inserted to the right-most position.
EXAMPLE:
dh contains 8Ah and cl contains 03h
dh = 10001010, cl = 00000011
after shl dh,cl
dh = 01010000, cf = 0

SAL – SHIFT ARITHMETHIC LEFT

DESCRIPTION: The content of the register specified by R are shifted to the left depending on the
rightmost six bits of the calculated D(B) address.An arithmetic left shift is equivalent to multiplying
by a power of 2. The power of 2 to multiply by is specified by the second operand.
The first (or sign) bit (bit 0) does not participate in the shift.
If the bit shifted out of position 1 does not match the sign bit, overflow will occur. Therefore, a
valid arithmetic shift will never alter the sign bit.
SYNTAX:

SIMPLE INSTRUCTION:
Shift operand1 Left. The number of shifts is set by operand2.
Algorithm:
Shift all bits left, the bit that goes off is set to CF.
Zero bit is inserted to the right-most position.
Code Meaning
0 Result is 0
1 Result is less than 0
2 Result is greater than 0
3 Overflow
EXAMPLE:
0 0 0 0 0 0 0 5
BEFORE: 0000 0000 0000 0000 0000 0000 0000 0101
AFTER: 0000 0000 0000 0000 0000 0000 0001 0100
0 0 0 0 0 0 1 4
will change the contents of register 7 to 00 00 00 14.

SHR – SHIFT LOGICAL RIGHT

DESCRIPTION: The content of the register specified by R are shifted to the right depending on the
rightmost six bits of the calculated D(B) address. The condition code is not altered. The digits that
are shifted off are lost.
SYNTAX:
SIMPLE INSTRUCTION:
Shift operand1 Right. The number of shifts is set by operand2.
Algorithm:
Shift all bits right, the bit that goes off is set to CF.
Zero bit is inserted to the left-most position.
EXAMPLE:
Suppose that register 7 has the value 0F 0F 0F 0F. Execution of: SRL R7,6
0 F 0 F 0 F 0 F
BEFORE: 0000 1111 0000 1111 0000 1111 0000 1111
AFTER: 0000 0000 0011 1100 0011 1100 0011 1100
0 0 3 C 3 C 3 C

SAR – SHIFT ARITHMETHIC RIGHT

DESCRIPTION: The content of the register specified by R are shifted to the right depending on the
rightmost six bits of the calculated D(B) address. An arithmetic right shift is equivalent to dividing
by a power of 2. The power of 2 to divide by is specified by the second operand. The value of bits
that are filled in on the left are equal to the sign bit. If the number is positive, the leftmost bits will
be filled with zero. If the number is negative, the leftmost bits will be filled with ones.
SYNTAX:

SIMPLE INSTRUCTION: Code Meaning

0 Result is 0
1 Result is less than 0
2 Result is greater than 0
Suppose that register 7 has the value FF FF FF FF. Execution of:
SRA R7,2
EXAMPLE:
F F F F F F F F
BEFORE: 1111 1111 1111 1111 1111 1111 1111 1111
AFTER: 1111 1111 1111 1111 1111 1111 1111 1111
F F F F F F F F