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Compal Confidential

 

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QBL50 Schematics Document

 

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AMD Sabine APU Llano / Hudson M2_M3 / Vancouver Whistler UMA only / PX Muxless

AMD Sabine APU Llano / Hudson M2_M3 / Vancouver Whistler UMA only / PX Muxless with BACO

 
AMD Sabine APU Llano / Hudson M2_M3 / Vancouver Whistler UMA only / PX Muxless with
   

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2010-02-16

 

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LA-7552P REV: 0.03

   

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Security Classification

Security Classification

Security Classification

 

Compal Secret Data

Compal Secret Data

Compal Secret Data

   

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

 

Issued Date

Issued Date

Issued Date

2010/08/04

2010/08/04

2010/08/04

Deciphered Date

Deciphered Date

Deciphered Date

 

2010/08/04

2010/08/04

2010/08/04

Title

Title

Title

Cover Page

Cover Page

Cover Page

 
 

http://hobi-elektronika.net

 

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

Size

Size

B

B

B

Document Number

Document Number

Document Number

QBL60 LA-7552P

QBL60 LA-7552P

QBL60 LA-7552P

 

Rev

Rev

Rev

0.03

0.03

0.03

Date:

Date:

Date:

Tuesday, February 22, 2011

Tuesday, February 22, 2011

Tuesday, February 22, 2011

Sheet

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Sheet

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A B C D E Compal Confidential Model Name : QBL60 VRAM 1G/2G Sabine 1
A
B
C
D
E
Compal Confidential
Model Name : QBL60
VRAM 1G/2G
Sabine
1
1
128M16 x 4/8
page 23, 24
DDR3
Thermal Sensor
Vancuver Whistler
ATI
GFX x 8
Gen2
ADM1032
page 19
uFCBGA-962
Memory BUS(DDR3)
GFX x 4
204pin DDRIII-SO-DIMM X2
Page 18~22
APU HDMI
(UMA / Muxless)
AMD FS1 APU
Llano
Dual Channel
BANK 0, 1, 2, 3
Page 11,12
1.5V DDRIII 800~1333MHz
DP x1 (DP0 TXP/N0)
uPGA-722 Package
HDMI Conn.
page 28
Travis LVDS
Page 6~10
LVDS
Translator
LVDS Conn.
2
2
P_GPP x 2
page 26
DP x 4
(DP1 TXP/N 0~4)
UMI
Reserve eDP
GEN1
USB2
USB2
USB2
CMOS
Mini Card
Card Reader
page 27
(LS-7322P)
Camera
(with BT)
RTS5137
page 34
page 34
page 30
page 27
page 32
page 31
CRT Conn.
FCH CRT (VGA DAC)
Port 0
Port 1
Port 5
Port2
Port 3
Port 4
page 27
FCH
USB
3.3V 48MHz
Hudson-M2/M3
GPP1
GPP0
HD Audio
3.3V 24.576MHz/48Mhz
uFCBGA-656
MINI Card 1
WLAN
LAN(GbE)
S-ATA
Gen2
Page 13~17
BCM57785
page 32
page 29
LPC BUS
port 0
port 1
3
3
SATA HDD1
ODD
HDA Codec
Conn.
RJ45 page 29
ALC269
page 33
Conn. page 33
page 30
ENE KB930
page 36
Touch Pad
Int.KBD
LED
page 38
page 38
page 37
RTC CKT.
External board
page 25
4
4
LS-7326P
BIOS ROM
page 35
DC/DC
Interface CKT. page 39
Power/B
SYS BIOS (2M)
page 15
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
LS-7322P
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Block Diagrams
Block Diagrams
Block Diagrams
Power Circuit
EC BIOS (128K)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio BD
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
page 40~48
page 30
page 35
B
B
B
0.03
0.03
0.03
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
http://hobi-elektronika.net
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
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5 4 3 2 1 DISPLAY DISTRIBUTION CLOCK DISTRIBUTION : LVDS PATH : APU HDMI
5
4
3
2
1
DISPLAY DISTRIBUTION
CLOCK DISTRIBUTION
: LVDS PATH
: APU HDMI PATH
LVDS CONN
D
D
TXOUT[0:2]+/-
TXCLK+/-
TZOUT[0:2]+/-
TZCLK+/-
I2CC_SCL/DA
AMD
R
ATI VGA
Whistler
APU_TXOUT[0:2]+/-
APU_TXOUT_CLK+/-
APU_TZOUT[0:2]+/-
CLK_PEG_VGAP/N
APU_TZOUT_CLK+/-
100MHz
APU_LVDS_CLK/DATA
AMD
C
AMD
APU_DISP_CLKP/N
100MHz
C
LVDS_OUT
RTD2132
FCH
CPU FS1 SOCKET
DP_IN
APU_CLKP/N
Hudson-M2/M3
100MHz
Internal CLK GEN
DP0_AUX
GPP_CLK
100MHz
LVDS Transtator
32.768KHz 25MHz
C
DP0_TXP/N[0:1]
DP0_AUXP/N
B
B
GPP1
GPP0
DP0
WLAN
Mini PCI Socket
GbE LAN
APU
VGA
PCIE_GFX[0:7]
C
PCIE_GFX[0:7]
DP1
PCIE_GFX[12:15]
C
25MHz
FCH
LS
R
MEM_MA_CLK1_P/N
A
A
MEM_MA_CLK7_P/N
A_SODIMM
1066~1600MHz
CRT CONN
HDMI CONN
MEM_MB_CLK1_P/N
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
MEM_MB_CLK7_P/N
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
B_SODIMM
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
1066~1600MHz
CLOCK / DISPLAY DISTRIBUTION
CLOCK / DISPLAY DISTRIBUTION
CLOCK / DISPLAY DISTRIBUTION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
0.03
0.03
0.03
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
Sheet
Sheet
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http://hobi-elektronika.net
5
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A B C D E Voltage Rails SIGNAL Power Plane Description S1 S3 S5 STATE
A
B
C
D
E
Voltage Rails
SIGNAL
Power Plane
Description
S1
S3
S5
STATE
SLP_S3#
SLP_S4#
SLP_S5#
+VALW
+V
+VS
Clock
VIN
Adapter power supply (19V)
N/A
N/A
N/A
Full ON
HIGH
HIGH
HIGH
ON
ON
ON
ON
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
S1(Power On Suspend)
HIGH
HIGH
HIGH
ON
ON
ON
LOW
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
S3 (Suspend to RAM)
LOW
HIGH
HIGH
ON
ON
OFF
OFF
1
1
+CPU_CORE_NB
Voltage for On-die VGA of APU
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+VGA_CORE
0.95-1.2V switched power rail
ON
OFF
OFF
+0.75VS
0.75V switched power rail for DDR terminator
ON
ON
OFF
S5 (Soft OFF)
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.0VSG
1.0V switched power rail for VGA
ON
OFF
OFF
+1.1ALW
1.1V switched power rail for FCH
ON
ON
ON*
+1.1VS
1.1V switched power rail for FCH
ON
OFF
OFF
+1.2VS
1.2V switched power rail for APU
ON
OFF
OFF
+1.5V
1.5V power rail for CPU VDDIO and DDR
ON
ON
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
+1.8VSG
1.8V switched power rail
ON
OFF
OFF
+2.5VS
2.5V for CPU_VDDA
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+LAN_IO
3.3V power rail for LAN
ON
ON
ON
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
2
2
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
BTO Option Table
M3@
M3@
U25
U25
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOM Structure
BTO Item
VGA@
Use VGA (Mux)
X76@
VRAM ID Table
FCH M3
FCH M3
Part Number = SA000043I90
Part Number = SA000043I90
M2@
Use Hudson-M2
BOM Config
M3@
Use Hudson-M3
USB30@
USB30 on M/B
USB20@
USB20 on M/B
x = 1 is read cmd, x= 0 is writee cmd.
External PCI Devices
Device
IDSEL#
REQ#/GNT#
Interrupts
3
3
EC SM Bus1 address
EC SM Bus2 address
Device
Address
HEX
Device
Address
HEX
Smart Battery
0001
011X b
16H
ADI ADM1032 (VGA)
1001 101X b
9AH
(APU)
RTD2132S (TL)
FCH
FCH
SM Bus 0 address
SM Bus 1 address
4
4
Device
Address
HEX
Device
Address
HEX
DDR DIMM1
1101
000X b
D0
DDR DIMM2
1101
001X b
D2
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Notes List
Notes List
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
B
B
0.03
0.03
0.03
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
http://hobi-elektronika.net
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
Sheet
Sheet
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5 4 3 2 1 AMD APU FS1 BATTERY BATT+ PU101 PU201 +CPU_CORE +CPU_CORE 0.7~1.475V
5
4
3
2
1
AMD APU FS1
BATTERY
BATT+
PU101
PU201
+CPU_CORE
+CPU_CORE
0.7~1.475V
VDD CORE 54A
12.6V
CHARGER
ISL6267HRZ-T
+CPU_CORE_NB
+CPU_CORE_NB
0.7~1.475V
VDDNB 27.5A
+2.5VS
+2.5VS
+2.5VS
VDDA 500mA
+1.5V
+1.5V
+1.5V
VDDIO 4.6A
PU501
AC ADAPTOR
VIN
+1.2VS
+1.2VS
VDDR 6.7A
D
RT8209MGQW
D
PU603
19V 90W
APL5508-25DC
RAM DDRIII SODIMMX2
PU801
+1.2VS
+1.5V
VDD_MEM 4A
RT8209MGQW
B+
+0.75VS
VTT_MEM 0.5A
PU601
+0.75VS +0.75VS
APL5336KAI
VGA ATI
Whistler/Seymour/Granville
PU901
+VGA_CORE
+VGA_CORE
0.85~1.1V
VDDC 47A
RT8237CZQW
+VDDCI
0.9~1.0V
VDDCI 4.6A
DPLL_VDDC: 125 mA
PU602
+1.0VSG
+1.0VSG
SPV10: 120 mA
+1.0VSG
APL5930KAI
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
U41
+1.5VSG
+1.5VSG
VRAM 1GB/2GB
64M / 128Mx16 * 4 / 8
+1.5VSG
VDDR1: 3400 mA
AO4430L
PU701
+1.1VALW
C
PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
+1.5VSG
2.4 A
RT8209MGQW
C
PU301
+3VALW
VDD_CT: 110 mA
PU401
+1.8VSG
+1.8VSG
RT8205LZQW
U40
+1.8VSG
SY8033BDBC
+5VALW
SI4800
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
+3VS
PJ14
+3VSG
+3VSG
A2VDD: 130 mA
+3VSG
VDDR3: 60 mA
U33
SI4800
FCH AMD Hudson M2/M3
LCD
panel
15.6"
U39
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
B+ 300mA
AO4430L
VDDCR_11: 1007 mA
+1.1VS
+1.1VS
+1.1VS
+3.3 350mA
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
FAN Control
+1.1VALW
B
APL5607
B
+1.1VALW
+5VS 500mA
VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA
+5VALW
U54/U55
+USB_VCCA
AP2301MPG
+USB_VCCB
+3VS
+3VS
+3VS
USB X3
VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA
+5V
Dual+1
2.5A
+3VALW
+3VALW
+3VALW
SATA
Audio Codec
EC
LAN
VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA
Mini Card
HDD*2
ALC269-GR
ENE KB930
RTL8111E
ODD*1
VDDIO_33_GBE_S
+5V 3A
+5V 45mA
+3.3VALW 30mA
+3.3VALW 201mA
+1.5VS 500mA
VDDCR_11_GBE_S
+3.3VS 3mA
+3.3VS 1A
GND
VDDIO_GBE_S
+3.3V
+3.3VS 25mA
+3.3VALW 330mA
RTC
A
RTC BAT
VDDBT_RTC_G
A
Bettary
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
POWER DELIVERY CHART
POWER DELIVERY CHART
POWER DELIVERY CHART
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
http://hobi-elektronika.net
Custom
Custom
Custom
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
0.03
0.03
0.03
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
Sheet
Sheet
5
5
5
of
of
of
49
49
49
5
4
3
2
1
+INVPWR_B+
+5VS
+1.5VS
D D D D G G G G S S S S A B C
D
D
D
D
G G
G G
S
S
S
S
A
B
C
D
E
18
PCIE_GTX_C_FRX_P[0 7]
PCIE_FTX_C_GRX_P[0
7]
18
APU To HDMI
18
PCIE_GTX_C_FRX_N[0
7]
PCIE_FTX_C_GRX_N[0
7]
18
PCIE_FTX_GRX_P[12
15]
28
JCPU1A
JCPU1A
CONN@
CONN@
PCIE_FTX_GRX_N[12
15]
28
PCI EXPRESS
PCI EXPRESS
PCIE_GTX_C_FRX_P0
PCIE_FTX_GRX_P0
AA8
AA2
C917 VGA@
C917VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_P0
P_GFX_RXP0
P_GFX_TXP0
PCIE_GTX_C_FRX_N0
PCIE_FTX_GRX_N0
C918 VGA@
C918VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_N0
AA9
AA3
1
2
P_GFX_RXN0
P_GFX_TXN0
PCIE_GTX_C_FRX_P1
PCIE_FTX_GRX_P1
Y7
Y2
C919 VGA@
C919VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_P1
P_GFX_RXP1
P_GFX_TXP1
1
PCIE_GTX_C_FRX_N1
PCIE_FTX_GRX_N1
1
Y8
Y1
C920 VGA@
C920VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_N1
P_GFX_RXN1
P_GFX_TXN1
PCIE_GTX_C_FRX_P2
PCIE_FTX_GRX_P2
PCIE_FTX_C_GRX_P2
W5
Y4
C921 VGA@
C921VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
P_GFX_RXP2
P_GFX_TXP2
PCIE_GTX_C_FRX_N2
PCIE_FTX_GRX_N2
W6
Y5
C922VGA@
C922 VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_N2
P_GFX_RXN2
P_GFX_TXN2
PCIE_GTX_C_FRX_P3
PCIE_FTX_GRX_P3
W8
W2
C923 VGA@
C923VGA@
PCIE_FTX_C_GRX_P3
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
P_GFX_RXP3
P_GFX_TXP3
For UMA Mux.
PCIE_GTX_C_FRX_N3
PCIE_FTX_GRX_N3
W9
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_N3
W3
C924VGA@
C924 VGA@
1
2
P_GFX_RXN3
P_GFX_TXN3
PCIE_GTX_C_FRX_P4
PCIE_FTX_GRX_P4
PCIE_FTX_C_GRX_P4
V7
V2
C925VGA@
C925 VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
P_GFX_RXP4
P_GFX_TXP4
PCIE_GTX_C_FRX_N4
PCIE_FTX_GRX_N4
PCIE_FTX_C_GRX_N4
V8
V1
C926 VGA@
C926VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
P_GFX_RXN4
P_GFX_TXN4
PCIE_GTX_C_FRX_P5
PCIE_FTX_GRX_P5
U5
V4
C927 VGA@
C927VGA@
PCIE_FTX_C_GRX_P5
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
P_GFX_RXP5
P_GFX_TXP5
PCIE_GTX_C_FRX_N5
PCIE_FTX_GRX_N5
U6
V5
C928VGA@
C928 VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_N5
1
2
P_GFX_RXN5
P_GFX_TXN5
PCIE_GTX_C_FRX_P6
PCIE_FTX_GRX_P6
U8
U2
C929 VGA@
C929VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_P6
1
2
P_GFX_RXP6
P_GFX_TXP6
PCIE_GTX_C_FRX_N6
PCIE_FTX_GRX_N6
PCIE_FTX_C_GRX_N6
U9
U3
C930VGA@
C930 VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
P_GFX_RXN6
P_GFX_TXN6
PCIE_GTX_C_FRX_P7
PCIE_FTX_GRX_P7
PCIE_FTX_C_GRX_P7
T7
T2
C931 VGA@
C931VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
P_GFX_RXP7
P_GFX_TXP7
PCIE_GTX_C_FRX_N7
PCIE_FTX_GRX_N7
T8
T1
C932VGA@
C932 VGA@
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_FTX_C_GRX_N7
P_GFX_RXN7
P_GFX_TXN7
R5
T4
P_GFX_RXP8
P_GFX_TXP8
R6
T5
P_GFX_RXN8
P_GFX_TXN8
CPU TSI interface level shift
R8
R2
BSH111, the Vgs is:
P_GFX_RXP9
P_GFX_TXP9
min = 0.4V
2
2
R9
R3
C935
C935
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P_GFX_RXN9
P_GFX_TXN9
Max = 1.3V
P7
P2
P_GFX_RXP10
P_GFX_TXP10
1
R535
R535
2
1
R536
R536
2
+3VS
P8
P1
P_GFX_RXN10
P_GFX_TXN10
31.6K_0402_1%
31.6K_0402_1%
30K_0402_1%
30K_0402_1%
N5
P4
P_GFX_RXP11
P_GFX_TXP11
N6
P5
P_GFX_RXN11
P_GFX_TXN11
Q9
Q9
PCIE_FTX_GRX_P12
N8
N2
P_GFX_RXP12
P_GFX_TXP12
2
APU_SID
EC_SMB_DA
3
1
1
2
8,14
APU_SID
EC_SMB_DA2 19,26,36
PCIE_FTX_GRX_N12
N9
N3
R537
R537
0_0402_5%
0_0402_5%
P_GFX_RXN12
P_GFX_TXN12
PCIE_FTX_GRX_P13
M7
M2
BSH111 1N_SOT23-3
BSH111 1N_SOT23-3
P_GFX_RXP13
P_GFX_TXP13
1
To EC
PCIE_FTX_GRX_N13
M8
M1
P_GFX_RXN13
P_GFX_TXN13
To HDMI
PCIE_FTX_GRX_P14
L5
M4
Q10
Q10
P_GFX_RXP14
P_GFX_TXP14
0
PCIE_FTX_GRX_N14
APU_SIC
EC_SMB_CK
L6
M5
3
1
1
2
P_GFX_RXN14
P_GFX_TXN14
8,14
APU_SIC
EC_SMB_CK2 19,26,36
R538
R538
0_0402_5%
0_0402_5%
PCIE_FTX_GRX_P15
L8
L2
P_GFX_RXP15
P_GFX_TXP15
CK
BSH111 1N_SOT23-3
BSH111 1N_SOT23-3
PCIE_FTX_GRX_N15
L9
L3
P_GFX_RXN15
P_GFX_TXN15
PCIE_FTX_DRX_P0
AC5
AD4
C950
C950
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
29
PCIE_DTX_C_FRX_P0
P_GPP_RXP0
P_GPP_TXP0
PCIE_FTX_C_DRX_P0 29
GLAN
PCIE_FTX_DRX_N0
AC6
AD5
C951
C951
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
29
PCIE_DTX_C_FRX_N0
P_GPP_RXN0
P_GPP_TXN0
PCIE_FTX_C_DRX_N0 29
3
PCIE_FTX_DRX_P1
3
AC8
AC2
C952
C952
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
32
PCIE_DTX_C_FRX_P1
P_GPP_RXP1
P_GPP_TXP1
PCIE_FTX_C_DRX_P1 32
WLAN
PCIE_FTX_DRX_N1
AC9
AC3
C953
C953
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
32
PCIE_DTX_C_FRX_N1
P_GPP_RXN1
P_GPP_TXN1
PCIE_FTX_C_DRX_N1 32
AB7
AB2
P_GPP_RXP2
P_GPP_TXP2
AB8
AB1
P_GPP_RXN2
P_GPP_TXN2
AA5
AB4
P_GPP_RXP3
P_GPP_TXP3
AA6
AB5
P_GPP_RXN3
P_GPP_TXN3
Power Sequence of APU
+1.5V
UMI_FTX_MRX_P0
AF8
AF1
C956
C956
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
13
UMI_MTX_C_FRX_P0
P_UMI_RXP0
P_UMI_TXP0
UMI_FTX_C_MRX_P0 13
UMI_FTX_MRX_N0
AF7
AF2
C957
C957
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
13
UMI_MTX_C_FRX_N0
P_UMI_RXN0
P_UMI_TXN0
UMI_FTX_C_MRX_N0 13
+2.5VS
Group A
UMI_FTX_MRX_P1
AE6
AF5
C958
C958
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
13
UMI_MTX_C_FRX_P1
P_UMI_RXP1
P_UMI_TXP1
UMI_FTX_C_MRX_P1 13
UMI_FTX_MRX_N1
AE5
AF4
C959
C959
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
13
UMI_MTX_C_FRX_N1
P_UMI_RXN1
P_UMI_TXN1
UMI_FTX_C_MRX_N1 13
+1.5VS
UMI_FTX_MRX_P2
AE9
AE3
C960
C960
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
13
UMI_MTX_C_FRX_P2
P_UMI_RXP2
P_UMI_TXP2
UMI_FTX_C_MRX_P2 13
UMI_FTX_MRX_N2
AE8
AE2
C961
C961
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
13
UMI_MTX_C_FRX_N2
P_UMI_RXN2
P_UMI_TXN2
UMI_FTX_C_MRX_N2 13
+CPU_CORE
UMI_FTX_MRX_P3
AD8
AD1
C962
C962
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
13
UMI_MTX_C_FRX_P3
P_UMI_RXP3
P_UMI_TXP3
UMI_FTX_C_MRX_P3 13
UMI_FTX_MRX_N3
AD7
AD2
C963
C963
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
13
UMI_MTX_C_FRX_N3
P_UMI_RXN3
P_UMI_TXN3
UMI_FTX_C_MRX_N3 13
Group B
+CPU_CORE_NB
P_ZVDDP
P_ZVSS
1
2
K5
K4
1
2
+1.2VS
P_ZVDDP
P_ZVSS
4
4
R539
R539
196_0402_1%
196_0402_1%
R540
R540
196_0402_1%
196_0402_1%
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
+1.2VS
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
AMD FS1 PCIE / UMI / TSI
AMD FS1 PCIE / UMI / TSI
AMD FS1 PCIE / UMI / TSI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.03
0.03
0.03
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
http://hobi-elektronika.net
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
Sheet
Sheet
6
6
6
of
of
of
49
49
49
A
B
C
D
E
GPPUMI-LINK
GPPUMI-LINK
GRAPHICS
GRAPHICS
2
2
A B C D E 1 1 JCPU1B JCPU1B CONN@ CONN@ JCPU1C JCPU1C CONN@ CONN@
A
B
C
D
E
1
1
JCPU1B
JCPU1B
CONN@
CONN@
JCPU1C
JCPU1C
CONN@
CONN@
MEMORY CHANNEL A
MEMORY CHANNEL A
MEMORY CHANNEL B
MEMORY CHANNEL B
11
DDRA_SMA[15 0]
DDRA_SDQ[63
0]
11
12
DDRB_SMA[15
0]
DDRB_SDQ[63
0]
12
DDRA_SMA0
DDRA_SDQ0
DDRB_SMA0
DDRB_SDQ0
U20
E13
T27
A14
MA_ADD0
MA_DATA0
MB_ADD0
MB_DATA0
DDRA_SMA1
DDRA_SDQ1
DDRB_SMA1
DDRB_SDQ1
R20
J13
P24
B14
MA_ADD1
MA_DATA1
MB_ADD1
MB_DATA1
DDRA_SMA2
DDRA_SDQ2
DDRB_SMA2
DDRB_SDQ2
R21
H15
P25
D16
MA_ADD2
MA_DATA2
MB_ADD2
MB_DATA2
DDRA_SMA3
DDRA_SDQ3
DDRB_SMA3
DDRB_SDQ3
P22
J15
N27
E16
MA_ADD3
MA_DATA3
MB_ADD3
MB_DATA3
DDRA_SMA4
DDRA_SDQ4
DDRB_SMA4
DDRB_SDQ4
P21
H13
N26
B13
MA_ADD4
MA_DATA4
MB_ADD4
MB_DATA4
DDRA_SMA5
DDRA_SDQ5
DDRB_SMA5
DDRB_SDQ5
N24
F13
M28
C13
MA_ADD5
MA_DATA5
MB_ADD5
MB_DATA5
DDRA_SMA6
DDRA_SDQ6
DDRB_SMA6
DDRB_SDQ6
N23
F15
M27
B16
MA_ADD6
MA_DATA6
MB_ADD6
MB_DATA6
DDRA_SMA7
DDRA_SDQ7
DDRB_SMA7
DDRB_SDQ7
N20
E15
M24
A16
MA_ADD7
MA_DATA7
MB_ADD7
MB_DATA7
DDRA_SMA8
DDRB_SMA8
N21
M25
MA_ADD8
MB_ADD8
DDRA_SMA9
DDRA_SDQ8
DDRB_SMA9
DDRB_SDQ8
M21
H17
L26
C17
MA_ADD9
MA_DATA8
MB_ADD9
MB_DATA8
DDRA_SMA10
DDRA_SDQ9
DDRB_SMA10
DDRB_SDQ9
U23
F17
U26
B18
MA_ADD10
MA_DATA9
MB_ADD10
MB_DATA9
DDRA_SMA11
DDRA_SDQ10
DDRB_SMA11
DDRB_SDQ10
M22
E19
L27
B20
MA_ADD11
MA_DATA10
MB_ADD11
MB_DATA10
DDRA_SMA12
DDRA_SDQ11
DDRB_SMA12
DDRB_SDQ11
L24
J19
K27
A20
MA_ADD12
MA_DATA11
MB_ADD12
MB_DATA11
DDRA_SMA13
DDRA_SDQ12
DDRB_SMA13
DDRB_SDQ12
AA25
G16
W26
E17
MA_ADD13
MA_DATA12
MB_ADD13
MB_DATA12
DDRA_SMA14
DDRA_SDQ13
DDRB_SMA14
DDRB_SDQ13
L21
H16
K25
B17
MA_ADD14
MA_DATA13
MB_ADD14
MB_DATA13
DDRA_SMA15
DDRA_SDQ14
DDRB_SMA15
DDRB_SDQ14
L20
H19
K24
B19
MA_ADD15
MA_DATA14
MB_ADD15
MB_DATA14
DDRA_SDQ15
DDRB_SDQ15
F19
C19
MA_DATA15
MB_DATA15
DDRA_SBS0#
DDRB_SBS0#
U24
U27
11
DDRA_SBS0#
MA_BANK0
12
DDRB_SBS0#
MB_BANK0
DDRA_SBS1#
DDRA_SDQ16
DDRB_SBS1#
DDRB_SDQ16
U21
H20
T28
C21
11
DDRA_SBS1#
MA_BANK1
MA_DATA16
12
DDRB_SBS1#
MB_BANK1
MB_DATA16
DDRA_SBS2#
DDRA_SDQ17
DDRB_SBS2#
DDRB_SDQ17
L23
F21
K28
B22
11
DDRA_SBS2#
MA_BANK2
MA_DATA17
12
DDRB_SBS2#
MB_BANK2
MB_DATA17
DDRA_SDQ18
DDRB_SDQ18
J23
C23
11
DDRA_SDM[7 0]
MA_DATA18
12
DDRB_SDM[7 0]
MB_DATA18
DDRA_SDM0
DDRA_SDQ19
DDRB_SDM0
DDRB_SDQ19
E14
H23
D14
A24
MA_DM0
MA_DATA19
MB_DM0
MB_DATA19
DDRA_SDM1
DDRA_SDQ20
DDRB_SDM1
DDRB_SDQ20
J17
G20
A18
D20
MA_DM1
MA_DATA20
MB_DM1
MB_DATA20
DDRA_SDM2
DDRA_SDQ21
DDRB_SDM2
DDRB_SDQ21
E21
E20
A22
B21
MA_DM2
MA_DATA21
MB_DM2
MB_DATA21
DDRA_SDM3
DDRA_SDQ22
DDRB_SDM3
DDRB_SDQ22
F25
G22
C25
E23
MA_DM3
MA_DATA22
MB_DM3
MB_DATA22
DDRA_SDM4
DDRA_SDQ23
DDRB_SDM4
DDRB_SDQ23
AD27
H22
AF25
B23
MA_DM4
MA_DATA23
MB_DM4
MB_DATA23
DDRA_SDM5
DDRB_SDM5
AC23
AG22
MA_DM5
MB_DM5
2
DDRA_SDM6
DDRA_SDQ24
DDRB_SDM6
DDRB_SDQ24
2
AD19
G24
AH18
E24
MA_DM6
MA_DATA24
MB_DM6
MB_DATA24
DDRA_SDM7
DDRA_SDQ25
DDRB_SDM7
DDRB_SDQ25
AC15
E25
AD14
B25
MA_DM7
MA_DATA25
MB_DM7
MB_DATA25
DDRA_SDQ26
DDRB_SDQ26
G27
B27
MA_DATA26
MB_DATA26
DDRA_SDQS0
DDRA_SDQ27
DDRB_SDQS0
DDRB_SDQ27
G14
G26
C15
D28
11
DDRA_SDQS0
MA_DQS_H0
MA_DATA27
12
DDRB_SDQS0
MB_DQS_H0
MB_DATA27
DDRA_SDQS0#
DDRA_SDQ28
DDRB_SDQS0#
DDRB_SDQ28
H14
F23
B15
B24
11
DDRA_SDQS0#
MA_DQS_L0
MA_DATA28
12
DDRB_SDQS0#
MB_DQS_L0
MB_DATA28
DDRA_SDQS1
DDRA_SDQ29
DDRB_SDQS1
DDRB_SDQ29
G18
H24
E18
D24
11
DDRA_SDQS1
MA_DQS_H1
MA_DATA29
12
DDRB_SDQS1
MB_DQS_H1
MB_DATA29
DDRA_SDQS1#
DDRA_SDQ30
DDRB_SDQS1#
DDRB_SDQ30
H18
E28
D18
D26
11
DDRA_SDQS1#
MA_DQS_L1
MA_DATA30
12
DDRB_SDQS1#
MB_DQS_L1
MB_DATA30
DDRA_SDQS2
DDRA_SDQ31
DDRB_SDQS2
DDRB_SDQ31
J21
F27
E22
C27
11
DDRA_SDQS2
MA_DQS_H2
MA_DATA31
12
DDRB_SDQS2
MB_DQS_H2
MB_DATA31
DDRA_SDQS2#
DDRB_SDQS2#
H21
D22
11
DDRA_SDQS2#
MA_DQS_L2
12
DDRB_SDQS2#
MB_DQS_L2
DDRA_SDQS3
DDRA_SDQ32
DDRB_SDQS3
DDRB_SDQ32
E27
AB28
B26
AG26
11
DDRA_SDQS3
MA_DQS_H3
MA_DATA32
12
DDRB_SDQS3
MB_DQS_H3
MB_DATA32
DDRA_SDQS3#
DDRA_SDQ33
DDRB_SDQS3#
DDRB_SDQ33
E26
AC27
A26
AH26
11
DDRA_SDQS3#
MA_DQS_L3
MA_DATA33
12
DDRB_SDQS3#
MB_DQS_L3
MB_DATA33
DDRA_SDQS4
DDRA_SDQ34
DDRB_SDQS4
DDRB_SDQ34
AE26
AD25
AG24
AF23
11
DDRA_SDQS4
MA_DQS_H4
MA_DATA34
12
DDRB_SDQS4
MB_DQS_H4
MB_DATA34
DDRA_SDQS4#
DDRA_SDQ35
DDRB_SDQS4#
DDRB_SDQ35
AD26
AA24
AG25
AG23
11
DDRA_SDQS4#
MA_DQS_L4
MA_DATA35
12
DDRB_SDQS4#
MB_DQS_L4
MB_DATA35
DDRA_SDQS5
DDRA_SDQ36
DDRB_SDQS5
DDRB_SDQ36
AB22
AE28
AG21
AG27
11
DDRA_SDQS5
MA_DQS_H5
MA_DATA36
12
DDRB_SDQS5
MB_DQS_H5
MB_DATA36
DDRA_SDQS5#
DDRA_SDQ37
DDRB_SDQS5#
DDRB_SDQ37
AA22
AD28
AF21
AF27
11
DDRA_SDQS5#
MA_DQS_L5
MA_DATA37
12
DDRB_SDQS5#
MB_DQS_L5
MB_DATA37
DDRA_SDQS6
DDRA_SDQ38
DDRB_SDQS6
DDRB_SDQ38
AB18
AB26
AG17
AH24
11
DDRA_SDQS6
MA_DQS_H6
MA_DATA38
12
DDRB_SDQS6
MB_DQS_H6
MB_DATA38
DDRA_SDQS6#
DDRA_SDQ39
DDRB_SDQS6#
DDRB_SDQ39
AA18
AC25
AG18
AE24
11
DDRA_SDQS6#
MA_DQS_L6
MA_DATA39
12
DDRB_SDQS6#
MB_DQS_L6
MB_DATA39
DDRA_SDQS7
DDRB_SDQS7
AA14
AH14
11
DDRA_SDQS7
MA_DQS_H7
12
DDRB_SDQS7
MB_DQS_H7
DDRA_SDQS7#
DDRA_SDQ40
DDRB_SDQS7#
DDRB_SDQ40
AA15
Y23
AG14
AE22
11
DDRA_SDQS7#
MA_DQS_L7
MA_DATA40
12
DDRB_SDQS7#
MB_DQS_L7
MB_DATA40
DDRA_SDQ41
DDRB_SDQ41
AA23
AH22
MA_DATA41
MB_DATA41
DDRA_CLK0
DDRA_SDQ42
DDRB_CLK0
DDRB_SDQ42
T21
Y21
R26
AE20
11
DDRA_CLK0
MA_CLK_H0
MA_DATA42
12
DDRB_CLK0
MB_CLK_H0
MB_DATA42
DDRA_CLK0#
DDRA_SDQ43
DDRB_CLK0#
DDRB_SDQ43
T22
AA20
R27
AH20
11
DDRA_CLK0#
MA_CLK_L0
MA_DATA43
12
DDRB_CLK0#
MB_CLK_L0
MB_DATA43
DDRA_CLK1
DDRA_SDQ44
DDRB_CLK1
DDRB_SDQ44
R23
AB24
P27
AD23
11
DDRA_CLK1
MA_CLK_H1
MA_DATA44
12
DDRB_CLK1
MB_CLK_H1
MB_DATA44
DDRA_CLK1#
DDRA_SDQ45
DDRB_CLK1#
DDRB_SDQ45
R24
AD24
P28
AD22
11
DDRA_CLK1#
MA_CLK_L1
MA_DATA45
12
DDRB_CLK1#
MB_CLK_L1
MB_DATA45
DDRA_SDQ46
DDRB_SDQ46
AA21
AD21
MA_DATA46
MB_DATA46
DDRA_CKE0
DDRA_SDQ47
DDRB_CKE0
DDRB_SDQ47
H28
AC21
J26
AD20
11
DDRA_CKE0
MA_CKE0
MA_DATA47
12
DDRB_CKE0
MB_CKE0
MB_DATA47
DDRA_CKE1
DDRB_CKE1
H27
J27
11
DDRA_CKE1
MA_CKE1
12
DDRB_CKE1
MB_CKE1
DDRA_SDQ48
DDRB_SDQ48
AA19
AF19
MA_DATA48
MB_DATA48
DDRA_ODT0
DDRA_SDQ49
DDRB_ODT0
DDRB_SDQ49
Y25
AC19
W27
AE18
11
DDRA_ODT0
MA_ODT0
MA_DATA49
12
DDRB_ODT0
MB_ODT0
MB_DATA49
DDRA_ODT1
DDRA_SDQ50
DDRB_ODT1
DDRB_SDQ50
AA27
AC17
Y28
AE16
11
DDRA_ODT1
MA_ODT1
MA_DATA50
12
DDRB_ODT1
MB_ODT1
MB_DATA50
DDRA_SDQ51
DDRB_SDQ51
AA17
AH16
MA_DATA51
MB_DATA51
DDRA_SCS0#
DDRA_SDQ52
DDRB_SCS0#
DDRB_SDQ52
V22
AB20
V25
AG20
11
DDRA_SCS0#
MA_CS_L0
MA_DATA52
12
DDRB_SCS0#
MB_CS_L0
MB_DATA52
3
DDRA_SCS1#
DDRA_SDQ53
DDRB_SCS1#
DDRB_SDQ53
3
AA26
Y19
Y27
AG19
11
DDRA_SCS1#
MA_CS_L1
MA_DATA53
12
DDRB_SCS1#
MB_CS_L1
MB_DATA53
DDRA_SDQ54
DDRB_SDQ54
AD18
AF17
MA_DATA54
MB_DATA54
DDRA_SRAS#
DDRA_SDQ55
DDRB_SRAS#
DDRB_SDQ55
V21
AD17
V24
AD16
11
DDRA_SRAS#
MA_RAS_L
MA_DATA55
12
DDRB_SRAS#
MB_RAS_L
MB_DATA55
DDRA_SCAS#
DDRB_SCAS#
W24
V27
11
DDRA_SCAS#
MA_CAS_L
12
DDRB_SCAS#
MB_CAS_L
DDRA_SWE#
DDRA_SDQ56
DDRB_SWE#
DDRB_SDQ56
W23
AA16
V28
AG15
11
DDRA_SWE#
MA_WE_L
MA_DATA56
12
DDRB_SWE#
MB_WE_L
MB_DATA56
DDRA_SDQ57
DDRB_SDQ57
Y15
AD15
MA_DATA57
MB_DATA57
MEM_MA_RST#
DDRA_SDQ58
MEM_MB_RST#
DDRB_SDQ58
H25
AA13
J25
AG13
11
MEM_MA_RST#
MA_RESET_L
MA_DATA58
12
MEM_MB_RST#
MB_RESET_L
MB_DATA58
MEM_MA_EVENT#
DDRA_SDQ59
MEM_MB_EVENT#
DDRB_SDQ59
T24
AC13
T25
AD13
11
MEM_MA_EVENT#
MA_EVENT_L
MA_DATA59
12
MEM_MB_EVENT#
MB_EVENT_L
MB_DATA59
DDRA_SDQ60
DDRB_SDQ60
Y17
AG16
MA_DATA60
MB_DATA60
15mil
DDRA_SDQ61
DDRB_SDQ61
AB16
AF15
MA_DATA61
MB_DATA61
DDRA_SDQ62
DDRB_SDQ62
W20
AB14
AE14
+MEM_VREF
M_VREF
MA_DATA62
MB_DATA62
DDRA_SDQ63
DDRB_SDQ63
Y13
AF13
MA_DATA63
MB_DATA63
M_ZVDDIO
1
2
W21
+1.5V
M_ZVDDIO
R541
R541
39.2_0402_1%
39.2_0402_1%
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
EVENT# pull high
0.75V reference voltage
+1.5V
+1.5V
4
4
R542
R542
1K_0402_1%
1K_0402_1%
R544
R544
1 MEM_MA_EVENT#
2
1K_0402_5%
1K_0402_5%
15mil
R545
R545
1 MEM_MB_EVENT#
2
1K_0402_5%
1K_0402_5%
+MEM_VREF
1
2
R543
R543
C964
C964
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1K_0402_1%
1K_0402_1%
C965
C965
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
2
1
AMD FS1 DDRIII I/F
AMD FS1 DDRIII I/F
AMD FS1 DDRIII I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.03
0.03
0.03
http://hobi-elektronika.net
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
Sheet
Sheet
7
7
7
of
of
of
49
49
49
A
B
C
D
E
1
2
1
2
C C B B E E A B C D E Place near APU JCPU1D
C C
B B
E E
A
B
C
D
E
Place near APU
JCPU1D
JCPU1D
CONN@
CONN@
Place near APU
If not used, pins are left unconnected (DG ref.)
To LVDS
C971
C971
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
DP0_TXP0
DP0_AUXP
F2
D4
C972
C972
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
To LVDS
20101111
26
DP0_TXP0_C
DP0_TXP0
DP0_AUXP
DP0_AUXP_C 26
Translator
Translator
C973
C973
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
DP0_TXN0
DP0_AUXN
F1
D5
C974
C974
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
26
DP0_TXN0_C
DP0_TXN0
DP0_AUXN
DP0_AUXN_C
26
DP0_AUXP
R554
R554
2
1 1.8K_0402_5%
1.8K_0402_5%
DP0_TXP1
ML_VGA_AUXP C975
C975
0.1U_0402_16V7K
0.1U_0402_16V7K
DP0_AUXN
E3
E5
1
2
R555
R555
2
1 1.8K_0402_5%
1.8K_0402_5%
T25T25
DP0_TXP1
DP1_AUXP
ML_VGA_AUXP_C 15
To FCH
DP0_TXN1
ML_VGA_AUXN C976
ML_VGA_AUXP
E2
E6
C976
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
R547
R547
2
1 1.8K_0402_5%
1.8K_0402_5%
T26T26
DP0_TXN1
DP1_AUXN
ML_VGA_AUXN_C 15
ML_VGA_AUXN
R556
R556
2
1 1.8K_0402_5%
1.8K_0402_5%
J5
T19T19
DP0_TXP2
D2
DP0_TXP2
DP2_AUXP
AUX 2~5 are for GFX interface
D1
T20T20
DP0_TXN2
J6
DP0_TXN2
DP2_AUXN
1
use, they could be selected to I2C
or AUX logic
1
+1.2VS
DP0_TXP3
C2
H4
T21T21
DP0_TXP3
DP3_AUXP
VDDIO level
TEST25_L
R548
R548
1
2
510_0402_1%
510_0402_1%
C3
H5
T22T22
DP0_TXN3
Need Level shift
DP0_TXN3
DP3_AUXN
TEST25_H
R557
R557
1
2
510_0402_1%
510_0402_1%
Place near APU
G5
DP4_AUXP
C977
C977
DP1_TXP0
+1.5V
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
K2
15
ML_VGA_TXP0
DP1_TXP0
G6
DP4_AUXN
C968
C968
DP1_TXN0
TEST35
1 2
0.1U_0402_16V7K
0.1U_0402_16V7K
K1
R558
R558
1
2
300_0402_5%
300_0402_5%
15
ML_VGA_TXN0
DP1_TXN0
APU_HDMI_CLK
F4
R559
R559
1
2
300_0402_5%
300_0402_5%
DP5_AUXP
APU_HDMI_CLK
28
C969
C969
1 2
0.1U_0402_16V7K
0.1U_0402_16V7K
DP1_TXP1
J3
15
ML_VGA_TXP1
DP1_TXP1
APU_HDMI_DATA
F5
@
@
DP5_AUXN
APU_HDMI_DATA
28
C970
C970
0.1U_0402_16V7K
0.1U_0402_16V7K
DP1_TXN1
+1.5V
1
2
J2
15
ML_VGA_TXN1
DP1_TXN1
To FCH VGA ML
DP0_HPD
LVDS
M_TEST
D7
R564
R564
1 @
@
2
39.2_0402_1%
39.2_0402_1%
DP0_HPD
DP0_HPD
10
C978
C978
DP1_TXP2
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
H2
15
ML_VGA_TXP2
VDDIO level
Need Level shift
DP1_TXP2
DP1_HPD
E7
CRT
R567
R567
1 2
39.2_0402_1%
39.2_0402_1%
DP1_HPD
DP1_HPD
10
C979
C979
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
DP1_TXN2
H1
15
ML_VGA_TXN2
DP1_TXN2
J7
DP2_HPD
+3VALW
System DP
C980
C980
DP1_TXP3
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
G2
H7
15
ML_VGA_TXP3
DP1_TXP3
DP3_HPD
FS1R1
R571
R571
1 2
10K_0402_5%
10K_0402_5%
C981
C981
DP1_TXN3
1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
G3
G7
15
ML_VGA_TXN3
DP1_TXN3
DP4_HPD
DP5_HPD
F7
FS1R1 : Control S5 Dual PWR plane
In laptop, seems no use
DP5_HPD
DP5_HPD
10
HDMI
APU_CLKP
+1.5V
AH7
13
APU_CLKP
CLKIN_H
100MHz
DP_ENBKL
C6
DP_BLON
DP_ENBKL 10
APU_CLKN
AH6
13
APU_CLKN
VDDIO level
Need Level shift
CLKIN_L
2
DP_ENVDD
2
C5
DP_DIGON
DP_ENVDD
10
+1.5VS
R612
R612
1
2
1K_0402_5%
1K_0402_5%
APU_DISP_CLKP
DP_INT_PWM
AH4
C7
13
APU_DISP_CLKP
DISP_CLKIN_H
DP_VARY_BL
DP_INT_PWM 10
100MHz_NSS
ALLOW_STOP
R577
R577
1
2
1K_0402_5%
1K_0402_5%
APU_DISP_CLKN
AH3
@
@
13
APU_DISP_CLKN
DISP_CLKIN_L
DP_AUX_ZVSS
D8
R569
R569
APU_RST#
1
2
150_0402_1%
150_0402_1%
R578
R578
1
2
300_0402_5%
300_0402_5%
DP_AUX_ZVSS
MISC
APU_PWRGD
R580
R580
1
2
300_0402_5%
300_0402_5%
APU_SVC
B8
Chang to unpop (DG ref.)
47
APU_SVC
SVC
AA10
20101111
TEST6
APU_SVD
A8
47
APU_SVD
SVD
+1.5V
+3VS
G10
R573
R573
1 @
@
2
0_0402_5%
0_0402_5%
TEST9
APU_SIC
AH11
H10
Asserted as an input to force the
processor into the HTC-active state
6,14
APU_SIC
SIC
TEST10
TSI
APU_SID
AG11
H12
R574
R574
1 2
1K_0402_5%
1K_0402_5%
6,14
APU_SID
SID
TEST12
R587
R587
R588
R588
D9
R586
R586
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
T6T6
TEST14
1K_0402_5%
1K_0402_5%
APU_RST#
AF10
E9
13
APU_RST#
RESET_L
TEST15
T7T7
Chang to PU +1.5VS (DG ref.)
APU_PWRGD
AE10
G9
13
APU_PWRGD
T8T8
PWROK
TEST16
+1.5V
20101111
Q11
Q11
APU_PROCHOT#
H9
1
2
1
3
T9T9
TEST17
EC_THERM# 13,36,47
APU_PROCHOT#
AD10
R591
R591
0_0402_5%
0_0402_5%
PROCHOT_L
R575
R575
2
1K_0402_5%
1K_0402_5%
APU_SVC
APU_TEST18
1
H11
R582
R582
1 2
1K_0402_5%
1K_0402_5%
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
TEST18
APU_THERMTRIP#
+1.5V
Serial VID
AG12
THERMTRIP_L
R576
R576
1
2
1K_0402_5%
1K_0402_5%
APU_SVD
APU_TEST19
G11
R583
R583
1 2
1K_0402_5%
1K_0402_5%
TEST19
ALERT_L
AH12
ALERT_L
APU_TEST20
F12
R584
R584
1 2
1K_0402_5%
1K_0402_5%
Indicates to the FCH that a thermal trip
TEST20
+1.5V
THERMTRIP shutdown
temperature: 125 degree
APU_TEST21
E11
R585
R585
1 2
1K_0402_5%
1K_0402_5%
has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately
TEST21
3
3
R579
R579
1K_0402_5%
APU_SIC
1 2
1K_0402_5%
APU_TDI
C12
TDI
APU_TEST22
D11
R589
R589
1 2
1K_0402_5%
1K_0402_5%
R610
R610
TEST22
R581
R581
1 2
1K_0402_5%
1K_0402_5%
APU_SID
APU_TDO
A12
R609
R609
TDO
F10
1K_0402_5%
1K_0402_5%
10K_0402_5%
10K_0402_5%
TEST23
T10T10
R791
R791
1 2
1K_0402_5%
1K_0402_5%
ALERT_L
APU_TCK
A11
TCK
APU_TEST24
G12
R590
R590
1 2
1K_0402_5%
1K_0402_5%
Q12
Q12
TEST24
APU_TMS
APU_THERMTRIP#
D12
3
1
1
2
TMS
H_THERMTRIP#
14
+1.5V
TEST25_H
Close to Header
AH10
R611
R611
0_0402_5%
0_0402_5%
TEST25_H
APU_TRST#
B12
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
TRST_L
TEST25_L
AH9
TEST25_L
R592
R592
1 APU_TDI
APU_DBRDY
2
1K_0402_5%
1K_0402_5%
B11
DBRDY
K7
TEST28_H
R593
R593
1 APU_TCK
APU_DBREQ#
2
1K_0402_5%
1K_0402_5%
C11
DBREQ_L
+1.5V
K8
HDT Debug conn
TEST28_L
R594
R594
1 APU_TMS
2
1K_0402_5%
1K_0402_5%
JP1
JP1
APU_TCK
AA12
1
2
T11T11
TEST30_H
1
2
R595
R595
1 APU_TRST#
2
1K_0402_5%
1K_0402_5%
E8
RSVD_1
APU_TMS
AB12
3
4
TEST30_L
T12T12
3
4
R596
R596
1 APU_DBREQ#
2
300_0402_5%
300_0402_5%
K21
RSVD_2
M_TEST
APU_TDI
K22
5
6
TEST31
5
6
AC11
RSVD_3
APU_TDO
AB11
7
8
Cut on CPU side, Debug mount
T13T13
TEST32_H
7
8
R597
R597
1 2
0_0402_5%
0_0402_5%
47 APU_VDDNB_RUN_FB_L
Route as differential
with VSS_SENSE
APU_TRST#
AA11
R598
R598
1
2
0_0402_5%
0_0402_5%
9
10
R599
R599
1
@
@
2
0_0402_5%
0_0402_5%
APU_PWRGD
TEST32_L
T14T14
9
10
R600
R600
1 2
0_0402_5%
0_0402_5%
B9
47 APU_VDD_RUN_FB_L
VSS_SENSE
TEST35
D10
R601
R601
APU_RST#
1 2
10K_0402_5%
10K_0402_5%
11
12
R602
R602
1
@
@
2
0_0402_5%
0_0402_5%
TEST35
11
12
C8
VDDP_SENSE
R603
R603
10K_0402_5%
10K_0402_5%
APU_DBRDY
1 2
13
14
13
14
APU_VDDNB_RUN_FB_L
APU_VDDNB_SEN
A9
47 APU_VDDNB_SEN
VDDNB_SENSE
APU_VDDNB_SEN
route as differential
FS1R1
R605
R605
10K_0402_5%
10K_0402_5%
APU_DBREQ#
Y11
1 2
15
16
FS1R1
15
16
B10
VDDIO_SENSE
ALLOW_STOP
R606
R606
1 APU_TEST19
AB10
17
18
2
0_0402_5%
0_0402_5%
DMAACTIVE_L
ALLOW_STOP 13
17
18
4
APU_VDD_SEN
4
APU_VDD_RUN_FB_L
C9
47 APU_VDD_SEN
VDD_SENSE
APU_VDD_SEN
route as differential
C639
C639
1 APU_TEST18
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
19
20
R608
R608
2
0_0402_5%
0_0402_5%
19
20
A10
AE12
@
@
T15T15
VDDR_SENSE
THERMDA
AD12
T16T16
THERMDC
Llano do not support this thermal die
SAMTE_ASP-136446-07-B
SAMTE_ASP-136446-07-B
CONN@
CONN@
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
AMD FS1 Display / MISC / HDT
AMD FS1 Display / MISC / HDT
AMD FS1 Display / MISC / HDT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.03
0.03
0.03
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
http://hobi-elektronika.net
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
Sheet
Sheet
8
8
8
of
of
of
49
49
49
A
B
C
D
E
PORT 1CLKSER.CTRLJTAGRSVDSENSE
PORT 1CLKSER.CTRLJTAGRSVDSENSE
DISPLAY PORT 0DISPLAY
DISPLAY PORT 0DISPLAY
TEST
TEST
DISPLAY PORT MISC.
DISPLAY PORT MISC.
1
2
1
2
2
12
C C
2
12
B B
E E
12
A B C D E 330U_D2_2V_Y 330U_D2_2V_Y Power Name Consumption C5 C5 VDD +CPU_CORE 50A
A
B
C
D
E
330U_D2_2V_Y
330U_D2_2V_Y
Power Name
Consumption
C5
C5
VDD
+CPU_CORE
50A
CPU BOTTOM SIDE DECOUPLING
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
VDDNB
JCPU1F
JCPU1F
CONN@
CONN@
C992
C992
C1025
C1025
+CPU_CORE
+CPU_CORE_NB
22.5A
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
VDDIO
A7
T11
VSS
VSS
A13
T19
+1.5V
4A
VSS
VSS
C991
C991
C1024
C1024
2000mil
2000mil
A15
U4
VSS
VSS
VDDP / VDDR
JCPU1E
JCPU1E
CONN@
CONN@
1 1
1
1 1
1
1
1 1
1 1
1
1
1
A17
U7
VSS
VSS
0.01U_0402_16V7K
0.01U_0402_16V7K
390U_2.5V_10M
390U_2.5V_10M
0.22U_0603_16V4Z
0.22U_0603_16V4Z
+CPU_CORE
+CPU_CORE
A19
U10
+1.2VS
3A / 3.5A
VSS
VSS
A21
U18
VSS
VSS
C990
C990
C1023
C1023
VDDA
C1
T6
A23
V9
VDD
VDD
1
2 2
2
2 2
2
2
2 2
2 2
2
2
2
VSS
VSS
C1011
C1011
1
0.75A
D3
T10
A25
V11
+2.5VS
VDD
VDD
VSS
VSS
0.01U_0402_16V7K
0.01U_0402_16V7K
390U_2.5V_10M
390U_2.5V_10M
0.22U_0603_16V4Z
0.22U_0603_16V4Z
D6
T18
B7
V19
VDD
VDD
VSS
VSS
E1
U1
C4
W4
VDD
VDD
VSS
VSS
C998
C998
C1022
C1022
C1010
C1010
0.01U_0402_16V7K
0.01U_0402_16V7K
390U_2.5V_10M
390U_2.5V_10M
0.22U_0603_16V4Z
0.22U_0603_16V4Z
CORE_NB
330uF X 2
22uF X 4
CPU_CORE
330uF X 4
22uF X 11
F3
U11
C10
W7
VDD
VDD
VSS
VSS
F6
U19
C14
W10
VDD
VDD
VSS
VSS
F8
V3
C16
W12
VDD
VDD
VSS
VSS
+CPU_CORE_NB
G1
V6
C18
W14
VDD
VDD
VSS
VSS
C989
C989
C1021
C1021
H3
V10
C20
W16
VDD
VDD
VSS
VSS
C1009
C1009
H6
V18
C22
W18
VDD
VDD
VSS
VSS
0.22U_0603_16V4Z
0.22U_0603_16V4Z
180P_0402_50V8J
180P_0402_50V8J
0.22U_0603_16V4Z
0.22U_0603_16V4Z
H8
W1
C24
Y9
VDD
VDD
VSS
VSS
J1
W11
1
1
1
C26
Y22
VDD
VDD
VSS
VSS
C988
C988
C1008
C1008
C1020
C1020
K3
W13
1
1 1
1 1
1 1
1
1
C28
AA4
VDD
VDD
VSS
VSS
+ +
+ +
+ +
K6
W15
D13
AA7
VDD
VDD
VSS
VSS
0.22U_0603_16V4Z
0.22U_0603_16V4Z
180P_0402_50V8J
180P_0402_50V8J
0.22U_0603_16V4Z
0.22U_0603_16V4Z
L1
W17
D15
AB9
VDD
VDD
VSS
VSS
L11
W19
D17
AB13
VDD
VDD
2
2 2
2 2
2 2
2
2
2
2
2
VSS
VSS
C987
C987
C1007
C1007
C1019
C1019
L19
Y3
D19
AB15
VDD
VDD
VSS
VSS
M3
Y6
D21
AB17
VDD
VDD
VSS
VSS
22U_0805_6.3V6M
22U_0805_6.3V6M
180P_0402_50V8J
180P_0402_50V8J
0.22U_0603_16V4Z
0.22U_0603_16V4Z
M6
Y10
D23
AB19
VDD
VDD
VSS
VSS
M10
Y12
D25
AB21
VDD
VDD
VSS
VSS
C986
C986
C1006
C1006
C1018
C1018
M18
Y14
D27
AB23
VDD
VDD
VSS
VSS
N1
Y16
E4
AB25
VDD
VDD
VSS
VSS
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0603_16V4Z
0.22U_0603_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+1.5V
N11
Y18
E10
AB27
VDD
VDD
VSS
VSS
N19
Y20
E12
AC4
VDD
VDD
VSS
VSS
C985
C985
C1005
C1005
C17
C17
1000P_0402_50V7K
1000P_0402_50V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
P3
AA1
F9
AC7
VDD
VDD
VSS
VSS
P6
AB3
F11
AC10
VDD
VDD
VSS
VSS
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0603_16V4Z
0.22U_0603_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C1051
C1051
C13
C13
P10
AB6
1
F14
AC12
VDD
VDD
VSS
VSS
P18
AC1
1
1 1
1
1 1
1
1
1
1 1
1 1
1
F16
AC14
VDD
VDD
VSS
VSS
C997
C997
C1004
C1004
C16
C16
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1000P_0402_50V7K
1000P_0402_50V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+ +
R1
AD3
F18
AC16
VDD
VDD
VSS
VSS
R11
AD6
F20
AC18
VDD
VDD
VSS
VSS
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
180P_0402_50V8J
180P_0402_50V8J
C1037
C1037
C1050
C1050
C12
C12
R19
AE1
F22
AC20
VDD
VDD
2
2 2
2
2 2
2
2
2
2 2
2 2
2
2
VSS
VSS
T3
F24
AC22
VDD
VSS
VSS
C984
C984
C1003
C1003
C15
C15
C1030
C1030
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1000P_0402_50V7K
1000P_0402_50V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
F26
AC24
VSS
VSS
2
2
900mil
900mil
F28
AC26
VSS
VSS
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
180P_0402_50V8J
180P_0402_50V8J
C1036
C1036
C1049
C1049
C11
C11
J9
K11
G4
AC28
+CPU_CORE_NB
+CPU_CORE_NB
VDDNB
VDDNB
VSS
VSS
J10
K12
G8
AD9
VDDNB
VDDNB
VSS
VSS
C983
C983
C1002
C1002
C14
C14
C1029
C1029
180P_0402_50V8J
180P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
J11
K13
G13
AD11
VDDNB
VDDNB
VSS
VSS
J12
K14
G15
AE4
VDDNB
VDDNB
VSS
VSS
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0603_16V4Z
0.22U_0603_16V4Z
C1035
C1035
C1048
C1048
C10
C10
J14
K16
G17
AE7
VDDNB
VDDNB
VSS
VSS
J16
K17
G19
AE13
VDDNB
VDDNB
VSS
VSS
C996
C996
C1001
C1001
C1013
C1013
C1028
C1028
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
0.22U_0603_16V4Z
0.22U_0603_16V4Z
K9
K18
G21
AE15
VDDNB
VDDNB
VSS
VSS
+1.5V
K10
L18
G23
AE17
VDDNB
VDDNB
VSS
VSS
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0603_16V4Z
0.22U_0603_16V4Z
C1034
C1034
C1047
C1047
C1055
C1055
G25
AE19
VSS
VSS
160mil
160mil
J4
AE21
VSS
VSS
C982
C982
C1000
C1000
C1012
C1012
C1027
C1027
10U_0603_6.3V6M
10U_0603_6.3V6M
180P_0402_50V8J
180P_0402_50V8J
0.22U_0603_16V4Z
0.22U_0603_16V4Z
G28
R22
J8
AE23
+1.5V
+1.5V
VDDIO
VDDIO
VSS
VSS
H26
R25
J18
AE25
VDDIO
VDDIO
VSS
VSS
C6
C6
C1046
C1046
C1054
C1054
J28
R28
1 1
1 1
J20
AE27
VDDIO
VDDIO
VSS
VSS
K20
T20
J22
AF3
VDDIO
VDDIO
VSS
VSS
10U_0603_6.3V6M
10U_0603_6.3V6M
180P_0402_50V8J
180P_0402_50V8J
0.22U_0603_16V4Z
0.22U_0603_16V4Z
K23
T23
J24
AF6
VDDIO
VDDIO
VSS
VSS
K26
T26
K19
AF9
VDDIO
VDDIO
2 2
2 2
VSS
VSS
C7
C7
C1045
C1045
C1053
C1053
L22
U22
L4
AF12
VDDIO
VDDIO
VSS
VSS
L25
U25
L7
AF14
VDDIO
VDDIO
VSS
VSS
10U_0603_6.3V6M
10U_0603_6.3V6M
180P_0402_50V8J
180P_0402_50V8J
0.22U_0603_16V4Z
0.22U_0603_16V4Z
L28
U28
L10
AF16
VDDIO
VDDIO
VSS
VSS
M20
V20
M9
AF18
VDDIO
VDDIO
VSS
VSS
C8
C8
C1044
C1044
C1052
C1052
M23
V23
Decoupling between CPU and DIMMs
across VDDIO and VSS split
M11
AF20
VDDIO
VDDIO
VSS
VSS
M26
V26
M19
AF22
VDDIO
VDDIO
VSS
VSS
N22
W22
N4
AF24
VDDIO
VDDIO
VSS
VSS
N25
W25
N7
AF26
VDDIO
VDDIO
VSS
VSS
N28
W28
N10
AF28
VDDIO
VDDIO
VSS
VSS
P20
Y24
N18
AG10
VDDIO
VDDIO
VSS
VSS
P23
Y26
VDDP decoupling
P9
AH5
VDDIO
VDDIO
VSS
VSS
P26
AA28
P11
AH8
VDDIO
VDDIO
VSS
VSS
+1.2VS
P19
AH13
VSS
VSS
+1.2VS
120mil
120mil
R4
AH15
VSS
VSS
AG2
A3
R7
AH17
+1.2VS
VDDP_A_1
VDDP_B_1
VSS
VSS
3
3
AG3
A4
R10
AH19
VDDP_A_2
VDDP_B_2
VSS
VSS
AG4
B3
1
R18
AH21
VDDP_A_3
VDDP_B_3
VSS
VSS
AG5
B4
1 1
1
1 1
1 1
T9
AH23
VDDP_A_4
VDDP_B_4
VSS
VSS
+ +
C1038
C1038
AH25
VSS
220U_6.3V_M
220U_6.3V_M
160mil
160mil
AG6
A5
+1.2VS
VDDR
VDDR
2 2
2
2 2
2 2
2
AG7
A6
VDDR
VDDR
AG8
B5
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
VDDR
VDDR
AG9
B6
VDDR
VDDR
+2.5VS
C1038 change to SF000002Y00
L1
L1
20101228
40mil
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
AE11
VDDA
+VDDA_APU
2
1
AF11
VDDR decoupling
VDDA
+1.2VS
1 1
1
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
1 1
1
1 1
1 1
1
Keep trace from resistor to APU
within 0.6"
2 2
2
2 2
2
2 2
2 2
2
Keep trace from Caps to APU
180P_0402_50V8J
180P_0402_50V8J
within 1.2"
Del C1039
C1043
C1043
201012061900
Demo Board Capacitor (include PWM side)
22U_0805_6.3V6M
22U_0805_6.3V6M
CPU_CORE
470uF x 6
CORE_NB
470uF x 4
C18
C18
1 1
1
1 1
1 1
2
VDDIO_SUS
(DIMM x2)
100uF x 4
VDDP/R_PWM
470uF x 2
10uF x 1
0.22U_0603_16V4Z
0.22U_0603_16V4Z
22uF x 9
0.22uF x 2
22uF x 6
0.22uF x 2
0.1uF
VDDP
10uF x 3
0.22uF x 2
180pF x 2
C1041
C1041
180uF x 3
VDDR
4.7uF x 4
0.22uF x 4
1nF x 4
180pF x 4
4
2 2
2
2 2
2 2
1
4
3300P_0402_50V7K
3300P_0402_50V7K
180pF x 2
10nF x 3
C1040
C1040
VDDIO_SUS
(CPU side)
680uF x 1
330uF x 1
22uF x 3
4.7uF x 4
0.22uF x 6
180pF x 4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
AMD FS1 PWR / GND
AMD FS1 PWR / GND
AMD FS1 PWR / GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.02
0.02 0.02
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
http://hobi-elektronika.net
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
Sheet
Sheet
9
9 9
of
of
of
49
49
49
A
B
C
D
E
12
5 4 3 2 1 +3VS +3VS +1.5VS @ @ R614 R614 R613 R613 @
5
4
3
2
1
+3VS
+3VS
+1.5VS
@
@
R614
R614
R613
R613
@
@
4.7K_0402_5%
4.7K_0402_5%
@
@
10K_0402_5%
10K_0402_5%
R616
R616
R617
R617
D
D
Translator HPD
R615
R615
4.7K_0402_5%
4.7K_0402_5%
100K_0402_5%
100K_0402_5%
APU_ENBKL
1K_0402_5%
1K_0402_5%
From Translator
D
D
Q13
Q13
LVDS_HPD
3
1
2
@
@
26
LVDS_HPD
DP0_HPD
8
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
G G
Q14
Q14
@
@
S
S
2N7002_SOT23
2N7002_SOT23
2
1
@
@
Q15
Q15
C C
R618
R618
100K_0402_5%
100K_0402_5%
1
2
2
8
DP_ENBKL
R619
R619
2.2K_0402_5%
2.2K_0402_5%
B B
E
E
@
@
R620
R620
+3VS
100K_0402_5%
100K_0402_5%
+1.5VS
R621
R621
@
@
10K_0402_5%
10K_0402_5%
R623
R623
CRT HPD
R622
R622
4.7K_0402_5%
4.7K_0402_5%
1K_0402_5%
1K_0402_5%
APU_ENBKL
R624
R624
1
@
@
2
0_0402_5%
0_0402_5%
ENBKL
36
From FCH
Q16
Q16
FCH_CRT_HPD
3
1
15
FCH_CRT_HPD
DP1_HPD
8
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
2
1
R627
R627
100K_0402_5%
100K_0402_5%
C
+3VS
C
+3VS
+1.5VS
R628
R628
@
@
@
@
10K_0402_5%
10K_0402_5%
R630
R630
@
@
R632
R632
HDMI HPD
R629
R629
4.7K_0402_5%
4.7K_0402_5%
R631
R631
4.7K_0402_5%
4.7K_0402_5%
1K_0402_5%
1K_0402_5%
100K_0402_5%
100K_0402_5%
From HDMI Conn
APU_ENVDD
27
Q17
Q17
APU_HDMI_HPD
3
1
28
APU_HDMI_HPD
DP5_HPD
8
D
D
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
2
Q18
Q18
2
1
G G
@
@
R659
R659
100K_0402_5%
100K_0402_5%
@
@
S
S
2N7002_SOT23
2N7002_SOT23
@
@
Q19
Q19
C C
1
2
2
8
DP_ENVDD
R633
R633
2.2K_0402_5%
2.2K_0402_5%
B
B
E
E
@
@
R634
R634
100K_0402_5%
100K_0402_5%
B
B
+3VS
C C
C C
C C
R635
R635
R636
R636
B B
B B
B B
4.7K_0402_5%
4.7K_0402_5%
47K_0402_5%
47K_0402_5%
E E
E E
E E
APU_INVT_PWM 26,27
D
D
2
G G
Q20
Q20
S
S
2N7002_SOT23
2N7002_SOT23
Q21
Q21
C C
1
2
2
8 DP_INT_PWM
R637
R637
2.2K_0402_5%
2.2K_0402_5%
B
B
E E
R638
R638
4.7K_0402_5%
4.7K_0402_5%
Q15 / Q19 / Q21 change to SB000006A00
20101228
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
2010/08/04
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
AMD FS1 Singal Level Shifter
AMD FS1 Singal Level Shifter
AMD FS1 Singal Level Shifter
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.03
0.03
0.03
http://hobi-elektronika.net
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
QBL60 LA-7552P
QBL60 LA-7552P
QBL60 LA-7552P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Tuesday, February 22, 2011
Sheet
Sheet
Sheet
10
10
10
of
of
of
49
49
49
5
4
3
2
1
1
2
1
2
1
2
2
12
2
12
2
12
12
12
12
1
2
1
2
12
3
1
1
2
3
1
1
2
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
3
1
12
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
13
12
13
12
13
12
C1063 C1063 A B C D E 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K +VREF_DQ +1.5V +1.5V 15mil JDIMM1 JDIMM1
C1063
C1063
A
B
C
D
E
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+VREF_DQ
+1.5V
+1.5V
15mil
JDIMM1
JDIMM1
1
2
VREF_DQ
VSS1
DDRA_SDQ4
DDRA_SDQ[0 63]
3
4
VSS2
DQ4
DDRA_SDQ[0
63]
7
DDRA_SDQ0
DDRA_SDQ5
5
6
DQ0
DQ5
DDRA_SDQ1
DDRA_SDM[0 7]
7
8
DDRA_SDM[0
7]
7
DQ1
VSS3
DDRA_SDQS0#
9
10
VSS4
DQS#0
7
DDRA_SDM0
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SMA[0 15]
11
12
DDRA_SMA[0
15]
7
DM0
DQS0
DDRA_SDQS0
7
13
14
VSS5
VSS6
DDRA_SDQ2
DDRA_SDQ6
15
16
DQ2
DQ6
DDRA_SDQ3
DDRA_SDQ7
17
18
DQ3
DQ7
19
20
VSS7
VSS8
1
DDRA_SDQ8
DDRA_SDQ12
1
21
22
DQ8
DQ12
DDRA_SDQ9
DDRA_SDQ13
23
24
DQ9
DQ13
25
26
VSS9
VSS10
DDRA_SDQS1#
DDRA_SDM1
27
28
7
DDRA_SDQS1#
DQS#1
DM1
DDRA_SDQS1
MEM_MA_RST#
29
30
Place near DIMM1
7
DDRA_SDQS1
DQS1
RESET#
MEM_MA_RST# 7
31
32
VSS11
VSS12
DDRA_SDQ10
DDRA_SDQ14
33
34
DQ10
DQ14
DDRA_SDQ11
DDRA_SDQ15
35
36
+1.5V
DQ11
DQ15
37
38
VSS13
VSS14
DDRA_SDQ16
DDRA_SDQ20
39
40
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DQ16
DQ20
DDRA_SDQ17
DDRA_SDQ21
41
42
2
2
2
2
2
2
2
2
2
2
DQ17
DQ21
43
44
VSS15
VSS16
DDRA_SDQS2#
DDRA_SDM2
45
46
C1067
C1067
C1068
C1068
C1069
C1069
C1070
C1070
C1071
C1071
C1072
C1072
C1073
C1073
C1074
C1074
C1075
C1075
C1076
C1076
7
DDRA_SDQS2#
DQS#2
DM2
DDRA_SDQS2
47
48
7
DDRA_SDQS2
DQS2
VSS17
1
1
1
1
1
1
1
1
1
1
DDRA_SDQ22
49
50
VSS18
DQ22
C1060
C1060
DDRA_SDQ18
DDRA_SDQ23
51
52
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DQ18
DQ23
DDRA_SDQ19
53
54
DQ19
VSS19
DDRA_SDQ28
55
56
VSS20
DQ28
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
DDRA_SDQ24
DDRA_SDQ29
57
58
DQ24
DQ29
DDRA_SDQ25
59
60
DQ25
VSS21
DDRA_SDQS3#
61
62
VSS22
DQS#3
DDRA_SDQS3#
7
DDRA_SDM3
DDRA_SDQS3
63
64
+0.75VS
+1.5V
DM3
DQS3
DDRA_SDQS3
7
65
66
@
@
VSS23
VSS24
DDRA_SDQ26
DDRA_SDQ30
67
68
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
DQ26
DQ30
DDRA_SDQ27
DDRA_SDQ31
69
70
C1106
C1106
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
DQ27
DQ31
71
72
VSS25
VSS26
C1077
C1077
C1078
C1078
C1079
C1079
Add C1106
20101101
1
1
2
DDRA_CKE0
DDRA_CKE1
73
74
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
7
DDRA_CKE0
CKE0
CKE1
DDRA_CKE1
7
75
76
VDD1
VDD2
DDRA_SMA15
77
78
NC1
A15
2
DDRA_SBS2#
DDRA_SMA14
2
79
80
7
DDRA_SBS2#
BA2
A14
81
82
VDD3
VDD4
DDRA_SMA12
DDRA_SMA11
83
84
A12/BC#
A11
DDRA_SMA9
DDRA_SMA7
85
86
A9
A7
87
88
VDD5
VDD6
DDRA_SMA8
DDRA_SMA6
89
90
A8
A6
DDRA_SMA5
DDRA_SMA4
91
92
A5
A4
93
94
VDD7
VDD8
DDRA_SMA3
DDRA_SMA2
+VREF_CA
+1.5V
95
96
A3
A2
DDRA_SMA1
DDRA_SMA0
+VREF_DQ
+1.5V
97
98
A1
A0
99
100
VDD9
VDD10
DDRA_CLK0
DDRA_CLK1
101
102
7
DDRA_CLK0
CK0
CK1
7
DDRA_CLK0#
DDRA_CLK1#
103
104
DDRA_CLK1
R640
R640
7
DDRA_CLK0#
CK0#
CK1#
DDRA_CLK1#
7
105
106
R639
R639
1K_0402_1%
1K_0402_1%
VDD11
VDD12
DDRA_SMA10
DDRA_SBS1#
107
108
1K_0402_1%
1K_0402_1%
A10/AP
BA1
DDRA_SBS0#
DDRA_SRAS#
109
110
DDRA_SBS1#
7
15mil
7
DDRA_SBS0#
BA0
RAS#
DDRA_SRAS#
7
111
15mil
+VREF_CA
112
VDD13
VDD14
DDRA_SWE#
DDRA_SCS0#
+VREF_DQ
113
114
7
DDRA_SWE#
WE#
S0#
DDRA_SCS0#
7
DDRA_SCAS#
DDRA_ODT0
115
116
7
DDRA_SCAS#
CAS#
ODT0
DDRA_ODT0
7
117
118
VDD15
VDD16
DDRA_SMA13
DDRA_ODT1
119
120
1 1
1
A13
ODT1
DDRA_ODT1
7
DDRA_SCS1#
121
122
@
@
C1064
C1064
C1065
C1065
1
1 1
7
DDRA_SCS1#
S1#
NC2
123
124
15mil
@
@
C1061
C1061
C1062
C1062
R642
R642
VDD17
VDD18
125
126
R641