A B C D E

1 1

2
YOGA3-BDW M/B Schematics Document 2

INTEL Broadwell Mobile ULT Platform

INTEL BDW U-series CPU + DDR3L DIMM+ NV N16S-GT

2014-04-28
REV:1.0
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 1 of 45
A B C D E
 5 4 3 2 1

D
Yoga3 BDW Refresh Block diagram D

32.768KHz
Page 7 Memory BUS-ChannelB SO-DIMM DDR3L
Page 14
24MHz
Page 8 1.35V DDR3L 1333/1600 MT/s
VRAM DDR3L SINGLE N15S/N16S-GT PCIE-Port5 UP TO 8G
1~2G 4psc Page 15-23
GEN2
USB 2.0-Port0 Int. Camera
Page 24
Micro HDMI Conn. DDI-Port1
Page 25 USB 2.0-Port1
USB 3.0-Port2 USB 3.0/2.0 Right
eDP-Port[0:1] Intel CPU Page 32
eDP Conn.
Page 24 Broadwell-U SDP 15W
USB 2.0-Port2
SATA Gen3 Port 1 USB 3.0/2.0 Left
SATA/SSHD 40x24x1.38 BGA USB 3.0-Port1
Page 32

PCIe Port3 BGA 1168

C
PCIe Mini Card USB 2.0-Port3 Cardreader C

SPK Conn. WIFI with BT support, USB 2.0-Port4 IO/CONN Realtek RTS5170 SD/MMC Conn.
Page 30
(1W x 2)

Int. MIC Conn. HD Audio USB 2.0-Port6 Touch Screen

Codec CX20752
Page 24

HP&Mic Combo Conn. USB 2.0-Port7 DC_IN Combo USB port

iphone type USB 2.0 Port 7

SPI BUS SPI ROM

(8MB) Page 7
Page 4~13

G-Sensor LPC BUS USB 2.0 1x

BMA222E USB 2.0 Port 5

B 32.768KHz B

Page 29
E-compass I2C EC Battery
G-sensor ITE IT8386 128VFBGA Page 37
BMC150 Page 29 SMBUS
Thermal Sensor
ALS NCT7718W Page 31
AL3010
Sensor Board Touch Pad Int.KBD LID PAD LID
Page 31 Page 30

USB Board

Sub-board
DMIC SUB

Sensor SUB
A A

USB SUB

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 2 of 45
5 4 3 2 1
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF ) BOM Structure Table Board ID Table
Board ID Description PCB Revision
+5VS BOM Structure BOM Structure
DA8@ PCB MIRROR@ EC Mirror-code enable
Power Plane +3VS
UMA@ UMA SKU part UNMIRROR@ EC Mirror-code disableable
+1.5VS
B+ DEBUG@ DEBUG CARD Part OPT@ Discrete GPU SKU part
+1.05VS
+3VALW_PCH +1.35V_CPU ME@ ME part(connector, hole) N15SGT@ For N15S-GT GPU part
+3VL +3VALW +1.35V +0.68VS
RF@ RF request GC6@ GC62.0 support part
+CPU_CORE
1
State +5VLP +5VALW EMC@ EMC request RANKA@ For VRAM RankA part
1
CD@ COST DOWN Part
REV@ RESERVER Part

S0 O O O O O O BOM Configuration Table

SKU Description BOM Config
S3 O O O O X O
SKU1

DS3 O O X O X X
SKU2

S5 S4/AC Only O O O X X X
S5 S4 O X X X X
Battery only X

S5 S4 X X X X X
2 AC & Battery X 2

don't exist
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# +VALW +VALW_PCH +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH ON ON ON ON LOW X76&VGA Configuration Table

SKU Description BOM Config
S3 (Suspend to RAM) LOW LOW HIGH ON ON ON OFF OFF

DS3 (Suspend to RAM) LOW LOW HIGH ON LOW ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW ON ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW ON ON OFF OFF OFF

SMBUS Control Table

GPU Thermal
SOURCE Sensor ALS BATT touch sensor SODIMM Sensor PCH charger

3 3

EC_SMB_CLK1 IT8386
EC_SMB_DAT1 +3VALW_EC X X V X X X X X V
+3VLP

EC_SMB_CLK3 IT8386
V V X X X X X X X
EC_SMB_DAT3 +3VS +3VS +3VS

EC_SMB_CLK0 IT8386
X X X X X V V V X
EC_SMB_DAT0 +3VS +3VS +3VALW_PCH
PCB And LOGO Config ZZZ3 DA8@
SMB_CLK PCH
X X X V X X X X
SMB_DATA +3VALW_PCH
X PCB LOGO
+3VS
PCB 0YC NM-A381 REV0 M/B
ZZZ1 I7@ ZZZ2 I5@ ZZZ9 I3@
ZZZ4 HDMI@ ZZZ5 USB30@

SM Bus address PCIE PORT LIST USB Port Table CPU

USB20 USB30 BDW U2+2 Ci7 BDW U2+2 Ci5 BDW 2+2U 1.6G 1333 ES2
Device address Port Device CAMERA Left USB HDMI LOGO USB30 LOGO
Battery 0001 011X b
0 1
Right USB Right USB ZZZ6 HY2G@ ZZZ7 MIC2G@ ZZZ8 SAM2G@
EC1 1 2
EXHCI/XHCI

Charger
4
1 X 2 Left USB 3 X
Sensor VRAM 4

EC3 2 X 3 CARD READER 4 X

ALS
3 WLAN 4 BT HYNIX 2G MICRON 2G SAMSUNG 2G
Thermal Sensor 1001_100xb
EC0 4 X 5 Sensor
PCH THM
5 GPU 6 TOUCH PANEL
PCH TP
7 DC_IN combo USB2.0 Title
Security Classification LC Future Center Secret Data
Issued Date 2014/01/11 Deciphered Date 2013/11/08 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 3 of 45
A B C D E
 5 4 3 2 1

Haswell MCP (DDI,EDP)

PCIECLKREQ5# PCIECLKREQ5# 8

+3VS

D RC41 1 D
2 10K_0402_5% GPIO55

RPC2
@
UC1A HSW_ULT_DDR3L 1 8 PCI_PIRQA#
2 7 PCIECLKREQ5#
3 6 PCI_PIRQB#
4 5 PCI_PIRQC#

25 PCH_HDMI_TX2- C54 C45 PCH_EDP_TX0- 24 10K_0804_8P4R_5%

C55 DDI1_TXN0 EDP_TXN0 B46
25 PCH_HDMI_TX2+ DDI1_TXP0 EDP_TXP0 PCH_EDP_TX0+ 24
25 PCH_HDMI_TX1- B58 A47 PCH_EDP_TX1- 24
C58 DDI1_TXN1 EDP_TXN1 B47 1 UMA@ 2 GC6_FB_EN
25 PCH_HDMI_TX1+ DDI1_TXP1 EDP_TXP1 PCH_EDP_TX1+ 24
25 PCH_HDMI_TX0- B55 RC1 10K_0402_5%
A55 DDI1_TXN2 C47 1 2 PCH_GPU_EVENT#
25 PCH_HDMI_TX0+ DDI1_TXP2 EDP_TXN2
25 PCH_HDMI_CLK- A57 C46 RC2 10K_0402_5%
B57 DDI1_TXN3 EDP_TXP2 A49 1 2 PXS_PWREN_R
25 PCH_HDMI_CLK+ DDI1_TXP3 DDI EDP EDP_TXN3 B49 RC3 10K_0402_5%
C51 EDP_TXP3 1 @ 2 PCH_GPU_RST#_R
C50 DDI2_TXN0 A45 RC4 10K_0402_5%
DDI2_TXP0 EDP_AUXN PCH_EDP_AUX- 24
C53 B45 PCH_EDP_AUX+ 24
B54 DDI2_TXN1 EDP_AUXP
C49 DDI2_TXP1 D20 EDP_COMP 1 2 RC5 24.9_0402_1%
DDI2_TXN2 EDP_RCOMP +VCCIOA_OUT
B50 A43 1
A53 DDI2_TXP2 EDP_DISP_UTIL
DDI2_TXN3 EDP_COMP:
B53 TP1 @ 1 2 PCH_BKLT_EN
DDI2_TXP3 RC6 100K_0402_5%
Trace Width:25mil
Space:25mil 1 2 PCH_LCD_VDDEN
RC7 100K_0402_5%
Max length:100mil 1 @ 2 GC6_FB_EN
1 OF 19 RC8 10K_0402_5%
HASWELL-ULT-DDR3L_BGA1168 1 2 PCH_GPU_RST#_R
RC9 100K_0402_5%
UC1I HSW_ULT_DDR3L
@ 1 @ 2 PXS_PWREN_R
RC10 100K_0402_5%
1 @ 2 PCH_GPU_EVENT#
RC11 10K_0402_5%
C C
24 PCH_BKLT_CTRL PCH_BKLT_CTRL B8 B9 PCH_HDMI_DDC_CLK 25
PCH_BKLT_EN A9 EDP_BKLCTL DDPB_CTRLCLK C9
24,29 PCH_BKLT_EN EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA PCH_HDMI_DDC_DAT 25
24 PCH_LCD_VDDEN PCH_LCD_VDDEN C6 D9
EDP_VDDEN DDPC_CTRLCLK D11
DDPC_CTRLDATA

PCI_PIRQA# U6
PCI_PIRQB# P4 PIRQA/GPIO77 C5
PCI_PIRQC# N4 PIRQB/GPIO78 DDPB_AUXN B6
PCI_PIRQD# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5
8 PCI_PIRQD# PIRQD/GPIO80 DDPB_AUXP
1 AD4 A6
TP4 @ PME PCIE DDPC_AUXP
GPIO55 U7
GC6_FB_EN L1 GPIO55
16 GC6_FB_EN GPIO52
18 PXS_PWREN PXS_PWREN RC39 1 OPT@ 21K_0402_5%PXS_PWREN_R L3 C8 PCH_HDMI_HPD 25
PCH_GPU_RST# RC40 1 OPT@ 20_0402_5% PCH_GPU_RST#_R R5 GPIO54 DDPB_HPD A8
16 PCH_GPU_RST# GPIO51 DDPC_HPD
16 PCH_GPU_EVENT# PCH_GPU_EVENT# L4 D6 PCH_EDP_HPD 24
GPIO53 EDP_HPD

Port DDI PROCESSOR Pin Names HDMI* Mapping

9 OF 19
Port 1 DDI1_TXN[0] HDMIxC_TX2_DN
HASWELL-ULT-DDR3L_BGA1168 DDI1_TXP[0] HDMIxC_TX2_DP
DDI1_TXN[1] HDMIxC_TX1_DN
DDI1_TXP[1] HDMIxC_TX1_DP
DDI1_TXN[2] HDMIxC_TX0_DN
DDI1_TXP[2] HDMIxC_TX0_DP
Connect to GPU signal : DDI1_TXN[3] HDMIxC_CLK_DN
GC6_FB_EN DDI1_TXP[3] HDMIxC_CLK_DP
PCH_GPU_EVENT# DDPB_HPD DDI1_HPD_Q
PCH_GPU_RST# DDPB_CTRLCLK DDI1_CTRL_CK
PCH_PLT_RST# DDPB_CTRLDATA DDI1_CTRL_DATA
PXS_PWREN

B
DisplayPort* Disabling and Termination B

Pin Name Recommendation

DDPC_AUXP No Connect
DDPC_AUXN No Connect
DDPC_HPD No Connect
DDI2_TXP[3:0] No Connect
DDI2_TXN[3:0] No Connect
DDPC_CTRLCLK No Connect
DDPC_CTRLDATA No Connect

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 4 of 45
5 4 3 2 1
 5 4 3 2 1

UC1B HSW_ULT_DDR3L

TP2 @ 1 TP_SKTOCC# D61

TP3 @ 1 CATERR# K61 PROC_DETECT MISC
CPU_PECI_R N62 CATERR J62
D 29 CPU_PECI_R PECI PRDY D
K62
PREQ E60
PROC_TCK E61
CPU_PROCHOT# RC13 1 2 CPU_PROCHOT#_R K63 JTAG PROC_TMS E59
29,37 CPU_PROCHOT# PROCHOT PROC_TRST
56_0402_5% THERMAL F63
PROC_TDI F62
PROC_TDO
RC14 2 1 CPU_PROCPWRGD C61
+1.35V_CPU 10K_0402_5% PROCPWRGD PWR
J60
RC20 200_0402_1% BPM#0 H60
BPM#1

2
RC15 RC21 121_0402_1% H61
RC22 100_0402_1% BPM#2 H62
470_0402_5% 2 1 SM_RCOMP_0 AU60 BPM#3 K59
2 1 SM_RCOMP_1 AV60 SM_RCOMP0 DDR3L BPM#4 H63
2 1 SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60

1
1 2 DDRA_DRAMRST#_R AV15 SM_RCOMP2 BPM#6 J61
14 DDRA_DRAMRST# SM_DRAMRST BPM#7
1 RD55 SM_PG_CNTL1 AV61
0_0402_5% SM_PG_CNTL1
CC14
2 OF 19
2 .1U_0402_10V6-K HASWELL-ULT-DDR3L_BGA1168
@
C C

+3VALW

1
RC42
100K_0402_5%

2
CPU_DRAMPG_CNTL 14,39
+1.35V

1
C
RC45 1 2 2 QC14
1K_0402_5% B
B E B

3
MMBT3904WH_SOT323-3

SM_PG_CNTL1

2
RC43
10K_0402_5%
@

1
+1.05VS
VR OD Output
Place CC9 Close to EC Side
RC23 Close to MCP
1

for Defensive Design RC23

CPU_PROCHOT# 62_0402_1%
2

A CPU_PROCHOT# A

1
CC9 Title
47P_0402_50V8J Security Classification LC Future Center Secret Data
2 Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (MISC,THERMAL,JATG)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 5 of 45
5 4 3 2 1
 5 4 3 2 1

BDW-U 使使so-dimm时,白白白白白的白白白白白interleaved,
DDRA_DQ[63:0] 14

D DDRA_MA[15:0] 14 D
UC1C HSW_ULT_DDR3L
DDRA_DQS[7:0] 14

DDRA_DQS#[7:0] 14 UC1D HSW_ULT_DDR3L

DDRA_DQ0 AH63 AU37
SA_DQ0 SA_CLK#0 DDRA_CLK0# 14
DDRA_DQ1 AH62 AV37
SA_DQ1 SA_CLK0 DDRA_CLK0 14
DDRA_DQ2 AK63 AW36
SA_DQ2 SA_CLK#1 DDRA_CLK1# 14
DDRA_DQ3 AK62 AY36
SA_DQ3 SA_CLK1 DDRA_CLK1 14
DDRA_DQ4 AH61 DDRA_DQ32 AY31 AM38
DDRA_DQ5 AH60 SA_DQ4 AU43 DDRA_DQ33 AW31 SB_DQ0 SB_CK#0 AN38
SA_DQ5 SA_CKE0 DDRA_CKE0 14 SB_DQ1 SB_CK0
DDRA_DQ6 AK61 AW43 DDRA_DQ34 AY29 AK38
SA_DQ6 SA_CKE1 DDRA_CKE1 14 SB_DQ2 SB_CK#1
DDRA_DQ7 AK60 AY42 1 @ TP19 DDRA_DQ35 AW29 AL38
DDRA_DQ8 AM63 SA_DQ7 SA_CKE2 AY43 1 @ TP20 DDRA_DQ36 AV31 SB_DQ3 SB_CK1
DDRA_DQ9 AM62 SA_DQ8 SA_CKE3 DDRA_DQ37 AU31 SB_DQ4 AY49
DDRA_DQ10 AP63 SA_DQ9 AP33 DDRA_DQ38 AV29 SB_DQ5 SB_CKE0 AU50
SA_DQ10 SA_CS#0 DDRA_CS0# 14 SB_DQ6 SB_CKE1
DDRA_DQ11 AP62 AR32 DDRA_DQ39 AU29 AW49
SA_DQ11 SA_CS#1 DDRA_CS1# 14 SB_DQ7 SB_CKE2
DDRA_DQ12 AM61 DDRA_DQ40 AY27 AV50
DDRA_DQ13 AM60 SA_DQ12 AP32 1 @ TP21 DDRA_DQ41 AW27 SB_DQ8 SB_CKE3
DDRA_DQ14 AP61 SA_DQ13 SA_ODT0 DDRA_DQ42 AY25 SB_DQ9 AM32
DDRA_DQ15 AP60 SA_DQ14 AY34 DDRA_DQ43 AW25 SB_DQ10 SB_CS#0 AK32
SA_DQ15 SA_RAS DDRA_RAS# 14 SB_DQ11 SB_CS#1
AP58 AW34 DDRA_DQ44 AV27
SA_DQ16 SA_WE DDRA_WE# 14 SB_DQ12
AR58 AU34 DDRA_DQ45 AU27 AL32
SA_DQ17 SA_CAS DDRA_CAS# 14 SB_DQ13 SB_ODT0
AM57 DDRA_DQ46 AV25
AK57 SA_DQ18 AU35 DDRA_DQ47 AU25 SB_DQ14 AM35
SA_DQ19 SA_BA0 DDRA_BS0# 14 SB_DQ15 SB_RAS
AL58 AV35 AM29 AK35
SA_DQ20 SA_BA1 DDRA_BS1# 14 SB_DQ16 SB_WE
AK58 AY41 AK29 AM33
SA_DQ21 SA_BA2 DDRA_BS2# 14 SB_DQ17 SB_CAS
AR57 AL28
AN57 SA_DQ22 AU36 DDRA_MA0 AK28 SB_DQ18 AL35
AP55 SA_DQ23 SA_MA0 AY37 DDRA_MA1 AR29 SB_DQ19 SB_BA0 AM36
AR55 SA_DQ24 SA_MA1 AR38 DDRA_MA2 AN29 SB_DQ20 SB_BA1 AU49
AM54 SA_DQ25 SA_MA2 AP36 DDRA_MA3 AR28 SB_DQ21 4 OF 19 SB_BA2
AK54 SA_DQ26 SA_MA3 AU39 DDRA_MA4 AP28 SB_DQ22 AP40
AL55 SA_DQ27 SA_MA4 AR36 DDRA_MA5 AN26 SB_DQ23 SB_MA0 AR40
AK55 SA_DQ28 SA_MA5 AV40 DDRA_MA6 AR26 SB_DQ24 SB_MA1 AP42
AR54 SA_DQ29 SA_MA6 AW39 DDRA_MA7 AR25 SB_DQ25 SB_MA2 AR42
AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDRA_MA8 AP25 SB_DQ26 SB_MA3 AR45
DDRA_DQ16 AY58 SA_DQ31 SA_MA8 AU40 DDRA_MA9 AK26 SB_DQ27 SB_MA4 AP45
DDRA_DQ17 AW58 SA_DQ32 SA_MA9 AP35 DDRA_MA10 AM26 SB_DQ28 SB_MA5 AW46
C C
DDRA_DQ18 AY56 SA_DQ33 SA_MA10 AW41 DDRA_MA11 AK25 SB_DQ29 SB_MA6 AY46
DDRA_DQ19 AW56 SA_DQ34 SA_MA11 AU41 DDRA_MA12 AL25 SB_DQ30 SB_MA7 AY47
DDRA_DQ20 AV58 SA_DQ35 SA_MA12 AR35 DDRA_MA13 DDRA_DQ48 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46
DDRA_DQ21 AU58 SA_DQ36 SA_MA13 AV42 DDRA_MA14 DDRA_DQ49 AW23 SB_DQ32 SB_MA9 AK36
DDRA_DQ22 AV56 SA_DQ37 SA_MA14 AU42 DDRA_MA15 DDRA_DQ50 AY21 SB_DQ33 SB_MA10 AV47
DDRA_DQ23 AU56 SA_DQ38 SA_MA15 DDRA_DQ51 AW21 SB_DQ34 SB_MA11 AU47
DDRA_DQ24 AY54 SA_DQ39 AJ61 DDRA_DQS#0 DDRA_DQ52 AV23 SB_DQ35 SB_MA12 AK33
DDRA_DQ25 AW54 SA_DQ40 SA_DQSN0 AN62 DDRA_DQS#1 DDRA_DQ53 AU23 SB_DQ36 SB_MA13 AR46
DDRA_DQ26 AY52 SA_DQ41 SA_DQSN1 AM58 DDRA_DQ54 AV21 SB_DQ37 SB_MA14 AP46
DDRA_DQ27 AW52 SA_DQ42 SA_DQSN2 AM55 DDRA_DQ55 AU21 SB_DQ38 SB_MA15
DDRA_DQ28 AV54 SA_DQ43 SA_DQSN3 AV57 DDRA_DQS#2 DDRA_DQ56 AY19 SB_DQ39 AW30 DDRA_DQS#4
DDRA_DQ29 AU54 SA_DQ44 SA_DQSN4 AV53 DDRA_DQS#3 DDRA_DQ57 AW19 SB_DQ40 SB_DQSN0 AV26 DDRA_DQS#5
DDRA_DQ30 AV52 SA_DQ45 SA_DQSN5 AL43 DDRA_DQ58 AY17 SB_DQ41 SB_DQSN1 AN28
DDRA_DQ31 AU52 SA_DQ46 SA_DQSN6 AL48 DDRA_DQ59 AW17 SB_DQ42 SB_DQSN2 AN25
AK40 SA_DQ47 SA_DQSN7 DDRA_DQ60 AV19 SB_DQ43 SB_DQSN3 AW22 DDRA_DQS#6
AK42 SA_DQ48 AJ62 DDRA_DQS0 DDRA_DQ61 AU19 SB_DQ44 SB_DQSN4 AV18 DDRA_DQS#7
AM43 SA_DQ49 SA_DQSP0 AN61 DDRA_DQS1 DDRA_DQ62 AV17 SB_DQ45 SB_DQSN5 AN21
AM45 SA_DQ50 SA_DQSP1 AN58 DDRA_DQ63 AU17 SB_DQ46 SB_DQSN6 AN18
AK45 SA_DQ51 SA_DQSP2 AN55 AR21 SB_DQ47 SB_DQSN7
AK43 SA_DQ52 SA_DQSP3 AW57 DDRA_DQS2 AR22 SB_DQ48 AV30 DDRA_DQS4
AM40 SA_DQ53 SA_DQSP4 AW53 DDRA_DQS3 AL21 SB_DQ49 SB_DQSP0 AW26 DDRA_DQS5
AM42 SA_DQ54 SA_DQSP5 AL42 AM22 SB_DQ50 SB_DQSP1 AM28
AM46 SA_DQ55 SA_DQSP6 AL49 AN22 SB_DQ51 SB_DQSP2 AM25
AK46 SA_DQ56 SA_DQSP7 AP21 SB_DQ52 SB_DQSP3 AV22 DDRA_DQS6
AM49 SA_DQ57 AP49 AK21 SB_DQ53 SB_DQSP4 AW18 DDRA_DQS7
SA_DQ58 SM_VREF_CA DDR_SM_VREFCA 14 SB_DQ54 SB_DQSP5
AK49 AR51 AK22 AM21
SA_DQ59 SM_VREF_DQ0 DDR_SA_VREFDQ 14 SB_DQ55 SB_DQSP6
AM48 AP51 1 @ AN20 AM18
AK48 SA_DQ60 SM_VREF_DQ1 TP22 AR20 SB_DQ56 SB_DQSP7
AM51 SA_DQ61 AK18 SB_DQ57
SA_DQ62 SMVREF SB_DQ58
AK51 WIDTH:20MIL AL18
SA_DQ63 AK20 SB_DQ59
SPACING: 20MIL AM20 SB_DQ60
AR18 SB_DQ61
AP18 SB_DQ62
SB_DQ63

B B

3 OF 19
HASWELL-ULT-DDR3L_BGA1168
@

HASWELL-ULT-DDR3L_BGA1168
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (DDR3L)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 6 of 45
5 4 3 2 1
 5 4 3 2 1

RPC3 +3VS
VCCRTC
1 8
1 2 SRTC_RST# 2 7
8,16 GPU_PCIE_CLKREQ#
RC24 20K_0402_1% SATA2GP 3 6
SATA3GP 4 5
1 2 RTC_RST#
RC25 20K_0402_1% 10K_0804_8P4R_5%
UC1E HSW_ULT_DDR3L
1 1

CC10
1U_0402_10V6K

CC11
1U_0402_10V6K

1
RTC_X1 AW5 +3VALW_PCH
2 2 RTC_X2 AY5 RTCX1
RPC4
SM_INTRUDER# AU6 RTCX2 J5 SML0_CLK 4 1
INTVRMEN AV7 INTRUDER SATA_RN0/PERN6_L3 H5 SML0_DATA 3 2
TP71 SRTC_RST# AV6 INTVRMEN SATA_RP0/PERP6_L3 B15
JCMOS1 SRTCRST
RTC
SATA_TN0/PETN6_L3
Place under RAM Door @ RTC_RST# AU7 A15 2.2K_0404_4P2R_5%
29 RTC_RST# RTCRST SATA_TP0/PETP6_L3

1
D D
RPC5
RTCRST#&SRTCRST# CC32 @ J8 PCH_SMB_CLK 4 1
10P_0402_50V8J SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1 32
Space 15Mil TP71 For clear CMOS. H8 PCH_SMB_DATA 3 2
SATA_PRX_DTX_P1 32

2
SATA_RP1/PERP6_L2 A17
Place close to PCH. SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 32
B17 2.2K_0404_4P2R_5%
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 32
RPC14
VCCRTC RC26 1 2 33_0402_5% PCH_HDA_BCLK_R AW8 J6 PCH_SML1_CLK 4 1
27 PCH_HDA_BCLK HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
RC27 1 2 33_0402_5% PCH_HDA_SYNC_R AV11 H6 PCH_SML1_DAT 3 2
27 PCH_HDA_SYNC HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
RC28 1 2 33_0402_5% PCH_HDA_RST#_R AU8 B14
27 PCH_HDA_RST# HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1
AY10 C15 2.2K_0404_4P2R_5%
27 PCH_HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
AU12 RPC7
2 1 SM_INTRUDER# RC30 1 2 33_0402_5% PCH_HDA_SDOUT_R AU11 HDA_SDI1/I2S1_RXD F5 1 8
27 PCH_HDA_SDOUT HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
RC29 1M_0402_5% RC31 1 2 0_0402_5% AW10 E5 2 7
29 PCH_ME_PROTECT HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 9 PCH_GPIO47
AV10 C17 3 6
HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 9 PCH_GPIO24
2 1 INTVRMEN AY8 D17 4 5
I2S1_SCLK SATA_TP3/PETP6_L0 9 PCH_GPIO28
RC32 330K_0402_5%
1 10K_0804_8P4R_5%
CC12
1U_0402_10V6K

@ V1 PCH_GPIO34
SATA0GP/GPIO34 PCH_GPIO34 9
U1 SATA1GP SATA1GP 9
SATA1GP/GPIO35 V6 SATA2GP
2 SATA2GP/GPIO36 AC1 SATA3GP +1.05VS_PSATA3PLL
AU62 SATA3GP/GPIO37
AE62 PCH_TRST A12 QC2A
PCH_TCK SATA_IREF 2N7002KDWH_SOT363-6
SODIMM
AD61 L11 RC33
AE61 PCH_TDI RSVD3 K10 3.01K_0402_1% PCH_SMB_CLK 6 1
INTVRMEN

D
PCH_TDO RSVD4 PM_SMB_CLK 14,31

S
* PU to VccRTC via 330 k, Internal VRM EN AD62 JTAG C12 SATACOMP 2 1
AL11 PCH_TMS SATA_RCOMP U3
PD to GND via 330 k,Internal VRM Disable AC4 RSVD1 SATALED
Width: 12-15Mil IREF&RCOMP +3VS
AE63 RSVD2 +3VS
AV2 JTAGX Space:12Mil

G
RPC18
Length: 500Mil

2
RTC_X1 RSVD0 +3VS 4 1
3 2
RTC_X2 SATALED#1 @ 2

5
2.2K_0404_4P2R_5%

G
2 1 5 OF 19 RC35
RC36 10M_0402_5% HASWELL-ULT-DDR3L_BGA1168 10K_0402_5%
YC1
C 1 2 @ PCH_SMB_DATA 3 4 C

S
PM_SMB_DAT 14,31

D
32.768KHZ_12.5PF_202740-PG14
QC2B
1 2
2N7002KDWH_SOT363-6
CC7 CC8
15P_0402_50V8J UC1G HSW_ULT_DDR3L
18P_0402_50V8J
2 1
AU14 AN2 SMB_ALERT# SMB_ALERT# 9
29 LPC_AD0 LAD0 SMBALERT/GPIO11
AW12 AP2 PCH_SMB_CLK
29 LPC_AD1 LAD1 SMBCLK
AY12 LPC AH1 PCH_SMB_DATA
29 LPC_AD2 LAD2 SMBUS SMBDATA
CRYSTAL AW11 AL2 SML0_ALERT# SML0_ALERT# 9
29 LPC_AD3 LAD3 SML0ALERT/GPIO60 QC5A
1,Space 15MIL AV12 AN1 SML0_CLK
29 LPC_FRAME# LFRAME SML0CLK 2N7002KDWH_SOT363-6
2,No trace under crystal AK1 SML0_DATA
SML0DATA AU4 SML1_ALERT# PCH_SML1_CLK 6 1

D
SML1ALERT/PCHHOT/GPIO73 SML1_ALERT# 9 EC_SMB_CLK0 16,29,31

S
AU3 PCH_SML1_CLK
RTC_VCC_R +3VL SML1CLK/GPIO75 AH3 PCH_SML1_DAT @
VCCRTC PCH_SPI_CLK RC297 1 2 15_0402_5% PCH_SPI_CLK_R AA3 SML1DATA/GPIO74
29 PCH_SPI_CLK SPI_CLK +3VS
PCH_SPI_CS0# RC60 1 2 0_0402_5% PCH_SPI_CS0#_R Y7 AF2 +3VS
29 PCH_SPI_CS0# SPI_CS0 CL_CLK
Y4 AD2

G
RPC26

2
SPI_CS1 CL_DATA
2

AC2 SPI C-LINK AF4 4 1

DC1 PCH_SPI_SI RC299 1 2 15_0402_5% PCH_SPI_SI_R AA2 SPI_CS2 CL_RST 3 2
29 PCH_SPI_SI SPI_MOSI
RB751V-40_SOD323-2 1 2 29 PCH_SPI_SO PCH_SPI_SO RC300 1 2 15_0402_5% PCH_SPI_SO_R AA4
SPI_MISO

5
CC17
1U_0402_10V6K

CC26
.1U_0402_10V6-K

PCH_SPI_WP# RC301 1 @ 2 15_0402_5% PCH_SPI_WP#_R Y6 2.2K_0404_4P2R_5%

G
SPI_IO2
1

PCH_SPI_HOLD# RC302 1 @ 2 15_0402_5% PCH_SPI_HOLD#_RAF1

1

RC1491 SPI_IO3 @
1K_0402_5% 2 1
7 OF 19 PCH_SML1_DAT 3 4

S
DC37 EC_SMB_DAT0 16,29,31
@

D
2

BAT_D 2 1
HASWELL-ULT-DDR3L_BGA1168 QC5B
2N7002KDWH_SOT363-6
RB751V-40_SOD323-2 @

RTC_VCC
RTC_VCC_R

B B
J3
1 2
1 2

JUMP_43X39
@
+3V_SPI +3VS
+3VALW_PCH
RTC COIN
RTC_VCC_R 20MIL UC3 MIRROR@ UNMIRROR@
+3VL 20MIL PCH_SPI_CS0# 1 8 50mA +3V_SPI RC68 1 2 0_0402_5% RC69 1 2 0_0402_5%
CS# VCC
VCCRTC 20MIL PCH_SPI_SO 2 7 PCH_SPI_HOLD#
BAT_D 20MIL DO HOLD#
PCH_SPI_WP# 3 6 PCH_SPI_CLK 2
WP# CLK CC22
4 5 PCH_SPI_SI
GND DI .1U_0402_10V6-K
1
W25Q64FVSSIG_SO8
+3VS

1 @ 2 PCH_HDA_SDOUT_R
RC1495 1K_0402_5%

PCH_ME_PROTECT +3V_SPI
HDA_SDO This signal has a weak internal pull-down.
*L ME Protection Enable
RC37 1 2 1K_0402_5% PCH_SPI_WP#
A
H ME Protection Disable: A
can make ME flash be enable with ME locked RC38 1 2 1K_0402_5% PCH_SPI_HOLD#
Must be PU with the same Power with HDA PWR, or
will make PWR leakage
EMI
PCH_HDA_SDIN0

1
CC1029 Title
10P_0402_50V8J Security Classification LC Future Center Secret Data
2 EMC_NS@
Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (RTC&AUDIO&SATA&SMBUS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 7 of 45
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (Clock,PM) RPC6

+3VS

WLAN_CLKREQ# 8 1
2 1 SYS_RESET# 7 2
RC770 1M_0402_5% PCIECLKREQ1# 6 3
5 4

YC2 10K_0804_8P4R_5%

2 3 XTAL24_OUT RPC8
GND1 OSC2 PCIECLKREQ3# 8 1
XTAL24_IN 1 4 PCI_PIRQD# 7 2
OSC1 GND2 4 PCI_PIRQD#
1 1 PCH_GPIO33 6 3
9 PCH_GPIO33
5 4
9 PCH_GPIO76
CC23 24MHZ_6PF_7V24000032 CC24
3.3P_0402_50V8-B 3.3P_0402_50V8-B 10K_0804_8P4R_5%
2 2
D D
RPC10 10K_0404_4P2R_5%
MCP_TESTLOW1 1 4
MCP_TESTLOW2 2 3

RPC21 10K_0404_4P2R_5%
MCP_TESTLOW3 1 4
UC1F HSW_ULT_DDR3L
+1.05VS_PLPTCLKPLL MCP_TESTLOW4 2 3

DIFFCLK_BIASREF PCH_PLT_RST# RC98 1 2 100K_0402_5%

Width: 12-15Mil
C43 A25 XTAL24_IN Space:12Mil SUSCLK RC1472 @ 1 1K_0402_5%
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
PCIECLKREQ0# U2 CLKOUT_PCIE_P0 XTAL24_OUT Length: 500Mil
9 PCIECLKREQ0# PCIECLKRQ0/GPIO18 K21
B41 RSVD5 M21
A41 CLKOUT_PCIE_N1 RSVD6 C26 2 1
PCIECLKREQ1# Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF RC71 3.01K_0402_1%
PCIECLKRQ1/GPIO19 C35 MCP_TESTLOW1
CLK_PCIE_WLAN# C41 CLOCK TESTLOW_C35 C34 MCP_TESTLOW2
30 CLK_PCIE_WLAN# CLKOUT_PCIE_N2 TESTLOW_C34
PCIE CLK2 WLAN CLK_PCIE_WLAN B42 AK8 MCP_TESTLOW3
30 CLK_PCIE_WLAN CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
30 WLAN_CLKREQ# WLAN_CLKREQ# AD1 AL8 MCP_TESTLOW4
PCIECLKRQ2/GPIO20 TESTLOW_AL8 +3VALW_PCH
B38 AN15 PCH_PCI_CLK_R 1 2
CLKOUT_PCIE_N3 CLKOUT_LPC_0 PCH_PCI_CLK 29
C37 AP15 RC72 22_0402_5%
PCIECLKREQ3# N1 CLKOUT_PCIE_P3 CLKOUT_LPC_1
PCIECLKRQ3/GPIO21 B35
CLKOUT_ITPXDP

1
CLK_PCIE_GPU# A39 A35 PCIE_WAKE# 1 2
16 CLK_PCIE_GPU# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
PCIE CLK4 GPU CLK_PCIE_GPU B39 @ CC31 RC89 10K_0402_5%
16 CLK_PCIE_GPU CLKOUT_PCIE_P4 10P_0402_50V8J
GPU_PCIE_CLKREQ# U5
7,16 GPU_PCIE_CLKREQ#

2
PCIECLKRQ4/GPIO22
B37 Place close to PCH.
A37 CLKOUT_PCIE_N5
PCIECLKREQ5# T2 CLKOUT_PCIE_P5
4 PCIECLKREQ5# PCIECLKRQ5/GPIO23

C 6 OF 19 C
HASWELL-ULT-DDR3L_BGA1168
07/22
+3VALW_PCH
change 10K to 1K for the HLH at RSMRST#
@

PCH_ACIN 1 2
RC94 1K_0402_5%

ACPRESENT
DSX_CFG-DEEP SX Configuration Register
*0 In DS-Sx config Mode, Internal 20K PD Enabled
RC65 1 2 0_0402_5% PCH_ACIN
29 EC_PCH_ACIN In Non DS-Sx config Mode, Internal 20K PD Disabled
6
1 Internal 20K PD Disabled

RC64 1 2 2
29 EC_ACIN# AO5804EL_SC89-6
0_0402_5%
@ QC11A
@ +3VALW_PCH
1

PCH_GPIO72 1 2
RC86 10K_0402_5%
UC1H HSW_ULT_DDR3L
BATLOW:
SYSTEM POWER MANAGEMENT RC66 1 2 0_0402_5%EC_RSMRST#
*PU To VCCDSW3_3 IN DEEP SX PLATFORM
TP5 @ 1 EC_SUSACK#_R AK2 AW7 DSWODVREN PU TO VCCSUS3_3 IN NON DEEP SX PLATFORM
SYS_RESET# AC3 SUSACK DSWVRMEN AV5 DPWROK
RC61 1 2100_0402_5% SYS_PWROK AG2 SYS_RESET DPWROK AJ5 PCIE_WAKE#
29 EC_SYS_PWROK SYS_PWROK WAKE PCIE_WAKE# 30
RC62 1 2 0_0402_5% PCH_PWROK AY7
10,29 EC_PCH_PWROK PCH_PWROK
RC1391 2 0_0402_5% APWROK AB5
PCH_PLT_RST# AG7 APWROK V5 PM_CLKRUN# VCCRTC
B 16,29,30 PCH_PLT_RST# PLTRST CLKRUN/GPIO32 B
AG4 SUS_STAT# 1 @ TP54
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK/GPIO62 SUSCLK 30
AP5 1 @ TP53
AW6 SLP_S5/GPIO63 DSWODVREN 2 1
29 EC_RSMRST# RSMRST
EC_SUSWARN# AV4 RC77 330K_0402_5%
29 EC_SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
RC1411 2 0_0402_5% EC_PBTN_OUT#_R AL7 AJ6 PCH_SLP_S4#_R RC56 1 2 0_0402_5%
29 EC_PBTN_OUT# PWRBTN SLP_S4 PCH_SLP_S4# 29
PCH_ACIN AJ8 AT4 PCH_SLP_S3#_R RC58 1 2 0_0402_5%
ACPRESENT/GPIO31 SLP_S3 PCH_SLP_S3# 29
PCH_GPIO72 AN4 AL5 DSWVRMEN(PU to RTCVCC):
AF3 BATLOW/GPIO72 SLP_A AP4 1 @ TP55
AM5 SLP_S0 SLP_SUS AJ7
SLP_WLAN/GPIO29 SLP_LAN *1 Enable DSW 3.3V TO 1.05V Integrated
DSW On-die Voltage Regulator
0 Disable
8 OF 19
HASWELL-ULT-DDR3L_BGA1168

+3VALW_PCH

EC_SUSWARN# 1 2
RC95 10K_0402_5%
SUSWARN: @

1, 10K PU to VCCSUS Follow CRB

+1.35V_CPU
2, No Need PU for Check List used as SUSWARN#
VR_VDDQ_PWRGD *3, Need PU for GPIO30 and not used
EC_SUS_VCCP +3VS

+1.05VS

VR_VCCST_PWRGD
A PM_CLKRUN# 2 1 A
EC_PCH_PWROK RC78 8.2K_0402_5%

VCCST_PWRGD
Intel demand
VR_CPU_PWROK

EC_SYS_PWROK

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (Clock,PM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 8 of 45
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (GPIO,USB,PCIE) +3VS

2
+3VALW_PCH RC314 RC503 RC569 RC584
RPC9 H_THRMTRIP#_R 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
8 1 PCH_GPIO45 @ OPT@

.01U_0402_16V7-K
7 2 PCH_GPIO56

1
+1.05VS

CC106
6 3 PCH_GPIO58 BOARD_ID0
5 4 PCH_GPIO59 1 BOARD_ID1
BOARD_ID2
10K_0804_8P4R_5% BOARD_ID3

2
RPC11 UC1J HSW_ULT_DDR3L
@2 RC101
1 8 PCH_GPIO26 1K_0402_1% RC566 RC512 RC372 RC598
2 7 SMB_ALERT# SMB_ALERT# 7 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
D D
3 6 PCH_GPIO57 UMA@ @ @

2
4 5 PCH_GPIO13 @

1
PCH_GPIO76 P1 D60 H_THRMTRIP#_R RC44 1 2 0_0402_5% H_THRMTRIP# H_THRMTRIP# 16
8 PCH_GPIO76 BMBUSY/GPIO76 THRMTRIP
10K_0804_8P4R_5% PCH_GPIO8 AU2 V4 EC_KBRST#_R RC7581 @ 2 0_0402_5% EC_KBRST# 29
PCH_GPIO12 AM7 GPIO8 RCIN/GPIO82 T4 SERIRQ RC7591 2 0_0402_5%
LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ EC_INT_SERIRQ 29
RPC12 PCH_GPIO15 AD6 AW15 OPI_COMP RC104 2 1 49.9_0402_1% BOM Control :BOARD_ID1
8 1 BOARD_ID0 Y1 GPIO15 MISC PCH_OPI_RCOMP AF20
7 2 PCH_GPIO9 BOARD_ID1 T3 GPIO16 RSVD7 AB21
GPIO17 RSVD8 OPI_RCOMP Width: 12-15Mil
6 3 SML0_ALERT# SML0_ALERT# 7 7 PCH_GPIO24 PCH_GPIO24 AD5 Space:12Mil
5 4 USB_OC0# PCH_GPIO27 AN5 GPIO24
PCH_GPIO28 AD7 GPIO27 Length: 500Mil
7 PCH_GPIO28 GPIO28
10K_0804_8P4R_5% PCH_GPIO26 AN3
GPIO26 R6 PCH_GPIO83
GSPI0_CS/GPIO83 BOARD_ID0 BOARD_ID1 Description
RPC13 PCH_GPIO56 AG6 L6 BOARD_ID3
8 1 PCH_GPIO10 PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
7 2 USB_OC2# PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86
6 3 PCH_GPIO46 PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_BT_OFF#
GPIO59 GSPI1_CS/GPIO87 PCH_BT_OFF# 30 0 0 UMA
5 4 PCH_GPIO14 WIN8_BUTTON#_R AK4 GPIO L5 PCH_WLAN_OFF#
GPIO44 GSPI1_CLK/GPIO88 PCH_WLAN_OFF# 30
PCH_GPIO47 AB6 N7 PCH_GPIO89
7 PCH_GPIO47 GPIO47 GSPI1_MISO/GPIO89
10K_0804_8P4R_5% PCH_LCD_FPBACK U4 K2 PCH_GPIO90
24 PCH_LCD_FPBACK GPIO48 GSPI_MOSI/GPIO90
PCH_GPIO49 Y3 J1 PCH_GPIO91 DIS
RPC20 PCH_GPIO50 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
GPIO50 UART0_TXD/GPIO92 0 1
8 1 SML1_ALERT# SML1_ALERT# 7 PCH_GPIO71 Y2 J2 PCH_GPIO93
7 2 PCH_GPIO8 PCH_GPIO13 AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 PCH_GPIO94
6 3 USB_OC1# PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
5 4 USB_OC3# PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
10K_0804_8P4R_5% PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 PCH_GPIO3
GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
+3VS PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5
PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 PCH_GPIO6
PCH_GPIO33 P2 GPIO10 I2C1_SDA/GPIO6 F1 PCH_GPIO7 RC7611 2 0_0402_5%
8 PCH_GPIO33 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 EC_SCI# 29
PCH_GPIO70 C4 E3 PCH_GPIO64
RPC15 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
8 1 PCH_GPIO93 BOARD_ID2 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66 +3VALW_PCH
7 2 PCH_GPIO91 PCH_BEEP V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67
27 PCH_BEEP SPKR/GPIO81 SDIO_D1/GPIO67
6 3 PCH_GPIO3 C3 PCH_GPIO68
SDIO_D2/GPIO68

2
C 5 4 PCH_GPIO1 E2 PCH_GPIO69 C
SDIO_D3/GPIO69 RC567
10K_0804_8P4R_5% 10 OF 19
10K_0402_5%
HASWELL-ULT-DDR3L_BGA1168
RPC16

1
8 1 PCH_GPIO34 PCH_GPIO34 7 @
7 2 PCIECLKREQ0# PCIECLKREQ0# 8 1 2 WIN8_BUTTON#_R
24,29 WIN8_BUTTON#
6 3 SATA1GP SATA1GP 7 RC763
5 4 PCH_GPIO50 0_0402_5%
16 PCIE_CRX_GTX_N[0..3] @
10K_0804_8P4R_5%
16 PCIE_CRX_GTX_P[0..3]
RPC17
8 1 PCH_GPIO38
16 PCIE_CTX_C_GRX_N[0..3] UC1K HSW_ULT_DDR3L
7 2 PCH_GPIO92
6 3 PCH_GPIO2
16 PCIE_CTX_C_GRX_P[0..3]
5 4 PCH_GPIO90
PCIE_CRX_GTX_N0 F10 AN8 USB20_N0 24 @
10K_0804_8P4R_5% PCIE_CRX_GTX_P0 E10 PERN5_L0 USB2N0 AM8 1 2 PCH_GPIO14
PERP5_L0 USB2P0 USB20_P0 24 Camera _Conn 24,29 EC_LID_OUT#
RC762
RPC19 PCIE_CTX_C_GRX_N0 OPT@1 2 PCIE_CTX_GRX_N0 C23 AR7 USB20_N1 32 0_0402_5%
8 1 PCH_GPIO89 PCIE_CTX_C_GRX_P0 OPT@1 2 PCIE_CTX_GRX_P0 C22 PETN5_L0 USB2N1 AT7
PETP5_L0 USB2P1 USB20_P1 32 Right USB2.0
7 2 PCH_GPIO0 .1U_0402_10V6-K CC19
6 3 PCH_GPIO85 .1U_0402_10V6-K CC18 PCIE_CRX_GTX_N1 F8 AR8 USB20_N2 27
5 4 PCH_GPIO83 PCIE_CRX_GTX_P1 E8 PERN5_L1 USB2N2 AP8
PERP5_L1 USB2P2 USB20_P2 27 Left USB2.0
10K_0804_8P4R_5% PCIE_CTX_C_GRX_N1 OPT@1 2 PCIE_CTX_GRX_N1 B23 AR10 USB20_N3 27
PCIE_CTX_C_GRX_P1 OPT@1 2 PCIE_CTX_GRX_P1 A23 PETN5_L1 USB2N3 AT10
PETP5_L1 USB2P3 USB20_P3 27 Card Reader
RPC23 .1U_0402_10V6-K CC20
8 1 PCH_GPIO6 .1U_0402_10V6-K CC21 PCIE_CRX_GTX_N2 H10 AM15 USB20_N4 30
7 2 PCH_GPIO70 PCIE_CRX_GTX_P2 G10 PERN5_L2 USB2N4 AL15
PCIE5 PERP5_L2 USB2P4 USB20_P4 30 Mini Card BT
6 3 PCH_GPIO64 GPIO15, Internal PD
5 4 PCH_GPIO67 PCIE_CTX_C_GRX_N2 OPT@1 2 PCIE_CTX_GRX_N2 B21 AM13
PCIE_CTX_C_GRX_P2 OPT@1 2 PCIE_CTX_GRX_P2 C21 PETN5_L2 USB2N5 AN13
USB20_N5 29 1: INTEL ME TLS W Confidentiality
PETP5_L2 USB2P5 USB20_P5 29 ECT8386 Sensor *0: INTEL ME TLS WO Confidentiality
10K_0804_8P4R_5% .1U_0402_10V6-K CC25 +3VALW_PCH
.1U_0402_10V6-K CC34 PCIE_CRX_GTX_N3 E6 AP11 USB20_N6 24
RPC24 PCIE_CRX_GTX_P3 F6 PERN5_L3 USB2N6 AN11 PCH_GPIO15 1 @ 2
PERP5_L3 USB2P6 USB20_P6 24 Touch Panel
8 1 PCH_GPIO94 RC540 1K_0402_5%
B B
7 2 PCH_GPIO65 PCIE_CTX_C_GRX_N3 OPT@1 2 PCIE_CTX_GRX_N3 B22 AR13 USB20_N7 37
6 3 PCH_GPIO69 PCIE_CTX_C_GRX_P3 OPT@1 2 PCIE_CTX_GRX_P3 A21 PETN5_L3 USB2N7 AP13
PETP5_L3 USB2P7 USB20_P7 37 DC_IN combo USB2.0
5 4 PCH_GPIO68 .1U_0402_10V6-K CC35
.1U_0402_10V6-K CC36 G11
10K_0804_8P4R_5% PCIE_PRX_DTX_N3 F11 PERN3 G20
30 PCIE_PRX_DTX_N3 PERP3 USB3RN1 USB30_RX_N1 27 GPIO66, Internal 20K PD
PCIE_PRX_DTX_P3 H20
30 PCIE_PRX_DTX_P3
C29 USB3RP1 USB30_RX_P1 27 1: Top-Block Swap Override EN +3VS
PETN3 Left USB3.0 *0: Disable
2 1 PCIE_PTX_DRX_N3 B30 PCIE USB C33
30 PCIE_PTX_C_DRX_N3 PETP3 USB3TN1 USB30_TX_N1 27
+3VS 2 1 PCIE_PTX_DRX_P3 B34 USB30_TX_P1 27 PCH_GPIO66 2 @ 1
30 PCIE_PTX_C_DRX_P3 USB3TP1
CC177 .1U_0402_10V6-K F13 RC541 1K_0402_5%
CC188 .1U_0402_10V6-K G13 PERN4 E18
PERP4 USB3RN2 USB30_RX_N2 32
RPC22 F18 USB30_RX_P2 32
1 4 PCH_GPIO5 B29 USB3RP2
PETN4 Right USB3.0
2 3 PCH_GPIO4 A29 B33 USB30_TX_N2 32 GPIO81, No Reboot, Internal PD
PETP4 USB3TN2 A33 +3VS
10K_0404_4P2R_5% G17 USB3TP2 USB30_TX_P2 32 1: Enabled No Reboot Mode
RC7541 2 10K_0402_5% PCH_GPIO71 F17 PERN1/USB3RN3 *0: Disable No Reboot Mode
@ PERP1/USB3RP3 PCH_BEEP 2 @ 1
C30 RC544 1K_0402_5%
RC7531 2 10K_0402_5% PCH_WLAN_OFF# C31 PETN1/USB3TN3 AJ10 USBRBIAS
PETP1/USB3TP3 USBRBIAS AJ11 RC1122 1 22.6_0402_1%
RC7561 2 10K_0402_5% PCH_BT_OFF# F15 USBRBIAS AN10 USBRBIAS
G15 PERN2/USB3RN4 RSVD11 AM10Width: 20Mil
PERP2/USB3RP4 RSVD12 Space:15Mil Length: 500Mil
RC7731 2 10K_0402_5% PCH_GPIO49
B31
RC7721 2 10K_0402_5% PCH_LCD_FPBACK A31 PETN2/USB3TN4 +3VS
+1.05VS_PUSB3PLL PETP2/USB3TP4 GPIO86, Internal PD
AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC1#
USB_OC0# 32 1: LPC
OC1/GPIO41 USB_OC1# 27 *0: SPI ROM
AH2 USB_OC2# PCH_GPIO86 2 @ 1
E15 OC2/GPIO42 AV3 USB_OC3# RC542 1K_0402_5%
RSVD9 OC3/GPIO43 USB_OC3# 37
E13 2 @ 1
+3VALW_PCH RC113 2 1 3.01K_0402_1% PCIE_RCOMP A27 RSVD10 RC543 1K_0402_5%
B27 PCIE_RCOMP
PCIE_IREF
2

PCIE_RCOMP&PCIE_IREF (Shared with DMI)

RC97 Width 20Mil
11 OF 19
0_0402_5% Space 15Mil
A HASWELL-ULT-DDR3L_BGA1168 A
Length 500Mil
1

1 2 PCH_GPIO27
RC764 10K_0402_5%
1 2 PCH_GPIO25
RC765 10K_0402_5%
1@ 2 PCH_GPIO12
RC766 10K_0402_5%
Security Classification LC Future Center Secret Data Title
Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (GPIO,USB,PCIE)
1 @ 2 PCH_GPIO71
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
RC767 10K_0402_5% Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 9 of 45
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (Power) +1.35V_CPU

+CPU_CORE 1 1 1 1
+1.35V_CPU
HSW_ULT_DDR3L

CC27
2.2U_0603_6.3V6K

CC28
2.2U_0603_6.3V6K

CC29
2.2U_0603_6.3V6K

CC30
2.2U_0603_6.3V6K
UC1L
+CPU_CORE(32A) 22 µF X23 2 2 2 2
L59 C36
J58 RSVD13 VCC8 C40
RSVD14 VCC9 C44
AH26 VCC10 C48
1.35V_CPU(1.4A) VDDQ1 VCC11
HW 4PCS 2.2UF CAP Mounted AJ31 C52
AJ33 VDDQ2 VCC12 C56
HW 6PCS 10UF CAP Mounted AJ37 VDDQ3 VCC13 E23
PWR 2PCS 470U Near VR Output AN33 VDDQ4 VCC14 E25
+CPU_CORE AP43 VDDQ5 VCC15 E27 CD@ CD@
AR48 VDDQ6 VCC16 E29
D
+VCCIO_OUT AY35 VDDQ7 VCC17 E31 D
+CPU_CORE AY40 VDDQ8 VCC18 E33
AY44 VDDQ9 VCC19 E35
AY50 VDDQ10 VCC20 E37
1 VDDQ11 VCC21

2
VCC_SENSE E39
CC65 RC114 F59 VCC22 E41
Length Match: <25Mil VCC1 VCC23
4.7U_0603_6.3V6K 100_0402_1% N58 E43
2 Space: More Than 25Mil AC58 RSVD15 VCC24 E45
1 1 1 1 1 1
@
GND Reference RSVD16 VCC25 E47 CC37 CC38 CC39 CC40 CC41 CC42

1
1 2 E63 VCC26 E49 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
43 CPU_VCC_SENSE VCC_SENSE VCC27 2 2 2 2 2 2
RC137 0_0402_5% AB23 E51
A59 RSVD17 VCC28 E53
E20 VCCIO_OUT VCC29 E55 CD@ CD@
+VCCIOA_OUT VCCIOA_OUT VCC30
AD23 E57
AA23 RSVD18 VCC31 F24
AE59 RSVD19 VCC32 F28
RSVD20 VCC33 F32
CPU_SVID_ALRT#_R L62 VCC34 F36
CPU_SVID_CLK_R N63 VIDALERT HSW ULT POWER VCC35 F40
CPU_SVID_DAT_R L63 VIDSCLK VCC36 F44
VCCST_PG_EC_R B59 VIDSOUT VCC37 F48
F60 VCCST_PWRGD VCC38 F52
43 CPU_VR_ON VR_EN VCC39
CPU_VR_READY C59 F56
VR_READY VCC40 G23 +1.35V_CPU +CPU_CORE
D63 VCC41 G25
2 @ 1 PWR_DEBUG H59 VSS344 VCC42 G27
+1.05VS PWR_DEBUG VCC43
RC161 150_0402_1% P62 G29
TP36 @ 1 P60 VSS345 VCC44 G31
TP44 @ 1 P61 RSVD_TP1 VCC45 G33
RSVD_TP2 VCC46 1 1 1 1

CC76
33P_0402_50V8J

CC75
33P_0402_50V8J

CC83
33P_0402_50V8J

CC80
33P_0402_50V8J
N59 G35
2 1 N61 RSVD_TP3 VCC47 G37
RC1515 10K_0402_5% T59 RSVD_TP4 VCC48 G39
RSVD21 VCC49 2 2 2 2

RF_NS@
AD60 G41
RSVD22 VCC50

RF_NS@
AD59 G43
RSVD23 VCC51

RF_NS@

RF_NS@
AA59 G45
AE60 RSVD24 VCC52 G47
AC59 RSVD25 VCC53 G49
AG58 RSVD26 VCC54 G51
C C
U59 RSVD27 VCC55 G53
+1.05V_VCCST V59 RSVD28 VCC56 G55
RSVD29 VCC57 G57
VCCST(0.1A) VCC58
+1.05VS RC1381 2 0_0402_5% AC22 H23
AE22 VCCST1 VCC59 J23
AE23 VCCST2 VCC60 K23
VCCST3 VCC61 K57
1 1 VCC62
+CPU_CORE AB57 L22
CC82 CC81 AD57 VCC2 VCC63 M23
22U_0603_6.3V6-M AG57 VCC3 VCC64 M57
.1U_0402_10V6-K VCC4 VCC65
CD@ 2 2 C24 P57
VCC_SENSE VCC5 VCC66
Length Match: No More Than 25Mil C28 U57
C32 VCC6 VCC67 W57
Space: More Than 25Mil VCC7 VCC68
GND Reference 12 OF 19
HASWELL-ULT-DDR3L_BGA1168
SVID
1, Stripline Line, No More Than 6000Mil @
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil +1.05VS
2

RC546 RC123 CC43

75_0402_1% 130_0402_1% .1U_0402_10V6-K
@
2
1

43 CPU_SVID_ALERT# 2 1 CPU_SVID_ALRT#_R
RC121 43_0402_5%
B B
RC1221 2 0_0402_5% CPU_SVID_CLK_R +1.05VS
43 CPU_SVID_CLK

2
RC1241 2 0_0402_5% CPU_SVID_DAT_R
43 CPU_SVID_DAT
RC1512
+3VALW 1K_0402_5%

1
2
CPU_VR_ON @ RC1517 VCCST_PG_EC_R RC81 1 2 0_0402_5%
VCCST_PG_EC 29
10K_0402_5% 3
+1.05VS QC13B
1

1
2

CC50
0.01U_0402_16V7K
2

RC1514 5 @
@ RC1513 10K_0402_5% 6
10K_0402_5% 2
AO5804EL_SC89-6
1

4
@
1

+3VALW 0_0402_5% 2 1 2
8,29 EC_PCH_PWROK AO5804EL_SC89-6
2 1 CPU_VR_READY 1 2 VR_CPU_PWROK RC80 0_0402_5%
RC84 0_0402_5% QC13A
@ 1
2

CC49
0.01U_0402_16V7K
@ RC85
RC1516 1
3
@ 10K_0402_5% QC12B
2
1

5 @
6
AO5804EL_SC89-6
4
@
29,43 VR_CPU_PWROK 2 1 2
RC83 0_0402_5% AO5804EL_SC89-6
QC12A
@ 1
CC54
0.01U_0402_16V7K
@

1
A A
2

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (Power)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 10 of 45
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (Power2)

+1.05VS_VCCHSIO +1.05VS +1.05VS_VCCHSIO

+1.05VS_PUSB3PLL +1.05VS_PUSB3PLL
LC1 41mA
1 2 PJ11
2.2UH_CIG10W2R2MNC_20% 1 1 JUMP_43X39
1 1 2
CC2 CC3 1 2
22U_0603_6.3V6-M 22U_0603_6.3V6-M CC107
2 2 1U_0402_10V6K @
2
+1.05VS_PSATA3PLL +1.05VS_PSATA3PLL
LC2 42mA
D D
1 2
2.2UH_CIG10W2R2MNC_20% 1
1 1 VCCHSIO
CC4 1.838A
+1.05VS 22U_0603_6.3V6-M CC5 CC111
2 1U_0402_10V6K 1U_0402_10V6K2 1 CC112 +1.05VS_VCCHSIO UC1M HSW_ULT_DDR3L
2
22U_0603_6.3V6-M
2
CC112,CC101 VCCRTC
Place Near K9,L10,M9 +3VALW_PCH 1mA
1U_0402_10V6K2 1 CC101 K9
L10 VCCHSIO[1] CC1251 2
+1.05VS_PLPTVCC1P05 +1.05VS_PLPTVCC1P05 CC84 VCCHSIO[2]
1U_0402_10V6K
LC4 185mA Place Near N8,P9 CD@ +1.05VS M9 VCCRTC CC85 1 2 1U_0402_10V6K CC1251
1 2 1U_0402_10V6K2 1 CC84 N8 VCCHSIO[3] HSIO RTC AH11 CC86 1 2 .1U_0402_10V6-K
P9 VCC1_05[1] VCCSUS3_3[5] AG10
Place Near AH11
2.2UH_CIG10W2R2MNC_20% CC107 +1.05VS_PUSB3PLL CC87 1 2 .1U_0402_10V6-K
22U_0603_6.3V6-M 1 B18 VCC1_05[2] VCCRTC AE7 +DCPRTC CC88 1 2
1 1 1 1 Place Near B18 +1.05VS_PSATA3PLL
VCC1_05[1:9] VCCUSB3PLL DCPRTC
.1U_0402_10V6-K CC85,86,87
CC6 1U_0402_10V6K CC130 1.741A B11 Place Near AG10
CC13 CD@ CC132 CC117 CD@ VCCSATA3PLL
CC111 VCCSPI
22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M Place Near B11 18mA CC88
2 2 2 2 2 +1.05VS_POPIPLL TP42 @ 1 Y20 SPI Y8 VCCSPI CC90 1 2 .1U_0402_10V6-K
AA21 RSVD30 VCCSPI Place Near AE7
+1.05VS_PLPTCLKPLL +1.05VS_PLPTCLKPLL CC122 VCCAPLL[1]
OPI @
LC5 31mA Place Near AA21,W21 W21 +1.05VS CC90
1 2 VCCAPLL[2] AG14
VCCASW[1] VCCASW[1:5] Place Near Y8
2.2UH_CIG10W2R2MNC_20% CC103 AG13 658mA
VCCASW[2] +1.05VS
1 1 1 Place Near J13 CC90
CD@ 1U_0402_10V6K2 @1 CC103 +1.05VS_DCPSUS3 J13 USB3
DCPSUS3 J11
Place Near Y8
CC118 CC127 CC119 CC120 VCCHDA CC1131 2 10U_0603_6.3V6M
47U_0805_6.3V6-M 47U_0805_6.3V6-M 1U_0402_10V6K VCC1_05[3] H11 CC1241 2 1U_0402_10V6K
2 2 2 Place Near AH14 11mA VCC1_05[4] CC113,CC124,CC115
1U_0402_10V6K2 1 CC120 VCCHDA AH14 HDA H15 CC1151 2 1U_0402_10V6K
VCCHDA VCC1_05[5] AE8
Place Near J11,H11,H15,AE8,AF22
CC102 CD@
VCC1_05[6] AF22
+1.05VS_POPIPLL Place Near AH13 VCC1_05[7] CC123
+1.05VS_POPIPLL 1U_0402_10V6K2 @1 CC102 +1.05VS_DCPSUS2 AH13 VRM AG19 +PCH_DCPSUSBYP CC1231 2 1U_0402_10V6K
1 2
57mA DCPSUS2 CORE DCPSUSBYP[1] AG20
Place Near AG19,Ag20
CC100 +1.05VS
RC107 0_0402_5% +3VS +3VALW_PCH DCPSUSBYP[2] AE9 CC94 1@ 2 22U_0603_6.3V6-M
Place Near AC9,AA9,AE20,AE21 VCCASW[3] CC94,CC126
1 CC121 1 CC128 1 CC129 1 CC131 1 VCCDSW AF9 CC1261 2 1U_0402_10V6K Place Near AE9,AF9,AG8
AC9 VCCASW[4] AG8
CC97 114mA VCCSUS3_3[1] VCCASW[5]
@ @ @ @ CC122 Place Near AH10 22U_0603_6.3V6-M 2 1 CC100 AA9 GPIO/LPC AD10 CC109
1U_0402_10V6K 1U_0402_10V6K 2@ 1 CC97 VCCDSW3_3 AH10 VCCSUS3_3[2] DCPSUS1[1] AD8 +1.05VS_DCPSUS1 1@ 2 1U_0402_10V6K
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

2 2 2 2 2 VCCDSW3_3 DCPSUS1[2] Place Near AD10,AD8

CC95 22U_0603_6.3V6-M 2 1 CC95 V8 +1.5VS CC109
W9 VCC3_3[1]
Place Near V8,W9 VCC3_3[1:4] VCC3_3[2] VCCTS1_5 CC96
C 41mA J15 3mA Place Near K14,K16 C
THERMAL SENSOR VCCTS1_5 K14 +3VS
CC117 VCC3_3[3]
Place Near J18,K19 K16 CC96 1 2 .1U_0402_10V6-K CC105
+1.05VS_PLPTVCC1P05 VCC3_3[4]
Place Near U8,T9
CC119 +3VS
+1.05VS Place Near A20 +1.05VS_PLPTCLKPLL J18 CC108
K19 VCCCLK[1] SERIAL IO U8 CC1051 2 1U_0402_10V6K
A20 VCCCLK[2] VCCSDIO[1] T9
Place Near AB8
CC98,CC99 VCCACLKPLL VCCSDIO[2]
Place Near J17,R21,T21 +1.05VS J17 0529 CD@ VCCSDIO CC104
1U_0402_10V6K2 1 CC99 R21 VCCCLK[3]
VCCCLK[4] LPT LP POWER
DEL CC108 for VCCSPI change 17mA Place Near AG16,AG17
1 1U_0402_10V6K2 1 CC98 T21
VCCCLK[5]
CC78
33P_0402_50V8J

K18 SUS OSCILLATOR AB8 +1.05VS_DCPSUS4 1@ 2 1U_0402_10V6K

+3VALW_PCH TP47 @ 1 M20 RSVD31 DCPSUS4 CC110
CD@ RSVD32
TP48 @ 1 V21 +1.05VS
2 AE20 RSVD33 AC20 1 @ TP121
AE21 VCCSUS3_3[3] RSVD34 AG16 CC1041 2 1U_0402_10V6K
VCCSUS3_3[1:5] VCCSUS3_3[4] VCC1_05[8]
RF_NS@

USB2 AG17
65mA VCC1_05[9]

+3VALW_PCH 13 OF 19
HASWELL-ULT-DDR3L_BGA1168

1 2 VCCDSW3_3
RC99 0_0402_5%

+3VS +3VALW_PCH

2 @ 1 VCCHDA
RC102 0_0402_5%
B B
1 2
RC103 0_0402_5%

VCCDSW3_3 1 2 +PCH_DCPSUSBYP
CC398 0.47U_0402_25V6K

0524
Add 0.47U for VCCDSW3_3 ramp up
slower than 100us

+3V_SPI
+3VS

RC105
1 2 0_0402_5% VCCSPI

2 1
RC106 0_0402_5%
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 11 of 45
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (VSS)

UC1N HSW_ULT_DDR3L UC1O HSW_ULT_DDR3L UC1P HSW_ULT_DDR3L
H17
A11 AJ35 AP22 AV59 D33 VSS300 H57
A14 VSS1 VSS65 AJ39 AP23 VSS129 VSS193 AV8 D34 VSS257 VSS301 J10
A18 VSS2 VSS66 AJ41 AP26 VSS130 VSS194 AW16 D35 VSS258 VSS302 J22
A24 VSS3 VSS67 AJ43 AP29 VSS131 VSS195 AW24 D37 VSS259 VSS303 J59
A28 VSS4 VSS68 AJ45 AP3 VSS132 VSS196 AW33 D38 VSS260 VSS304 J63
A32 VSS5 VSS69 AJ47 AP31 VSS133 VSS197 AW35 D39 VSS261 VSS305 K1
D A36 VSS6 VSS70 AJ50 AP38 VSS134 VSS198 AW37 D41 VSS262 VSS306 K12 D
A40 VSS7 VSS71 AJ52 AP39 VSS135 VSS199 AW4 D42 VSS263 VSS307 L13
A44 VSS8 VSS72 AJ54 AP48 VSS136 VSS200 AW40 D43 VSS264 VSS308 L15
A48 VSS9 VSS73 AJ56 AP52 VSS137 VSS201 AW42 D45 VSS265 VSS309 L17
A52 VSS10 VSS74 AJ58 AP54 VSS138 VSS202 AW44 D46 VSS266 VSS310 L18
A56 VSS11 VSS75 AJ60 AP57 VSS139 VSS203 AW47 D47 VSS267 VSS311 L20
AA1 VSS12 VSS76 AJ63 AR11 VSS140 VSS204 AW50 D49 VSS268 VSS312 L58
AA58 VSS13 VSS77 AK23 AR15 VSS141 VSS205 AW51 D5 VSS269 VSS313 L61
AB10 VSS14 VSS78 AK3 AR17 VSS142 VSS206 AW59 D50 VSS270 VSS314 L7
AB20 VSS15 VSS79 AK52 AR23 VSS143 VSS207 AW60 D51 VSS271 VSS315 M22
AB22 VSS16 VSS80 AL10 AR31 VSS144 VSS208 AY11 D53 VSS272 VSS316 N10
AB7 VSS17 VSS81 AL13 AR33 VSS145 VSS209 AY16 D54 VSS273 VSS317 N3
AC61 VSS18 VSS82 AL17 AR39 VSS146 VSS210 AY18 D55 VSS274 VSS318 P59
AD21 VSS19 VSS83 AL20 AR43 VSS147 VSS211 AY22 D57 VSS275 VSS319 P63
AD3 VSS20 VSS84 AL22 AR49 VSS148 VSS212 AY24 D59 VSS276 VSS320 R10
AD63 VSS21 VSS85 AL23 AR5 VSS149 VSS213 AY26 D62 VSS277 VSS321 R22
AE10 VSS22 VSS86 AL26 AR52 VSS150 VSS214 AY30 D8 VSS278 VSS322 R8
AE5 VSS23 VSS87 AL29 AT13 VSS151 VSS215 AY33 E11 VSS279 VSS323 T1
AE58 VSS24 VSS88 AL31 AT35 VSS152 VSS216 AY4 E17 VSS280 VSS324 T58
AF11 VSS25 VSS89 AL33 AT37 VSS153 VSS217 AY51 F20 VSS281 VSS325 U20
AF12 VSS26 VSS90 AL36 AT40 VSS154 VSS218 AY53 F26 VSS282 VSS326 U22
AF14 VSS27 VSS91 AL39 AT42 VSS155 VSS219 AY57 F30 VSS283 VSS327 U61
AF15 VSS28 VSS92 AL40 AT43 VSS156 VSS220 AY59 F34 VSS284 VSS328 U9
AF17 VSS29 VSS93 AL45 AT46 VSS157 VSS221 AY6 F38 VSS285 VSS329 V10
C VSS30 VSS94 VSS158 VSS222 VSS286 VSS330 C
AF18 AL46 AT49 B20 F42 V3
AG1 VSS31 VSS95 AL51 AT61 VSS159 VSS223 B24 F46 VSS287 VSS331 V7
AG11 VSS32 VSS96 AL52 AT62 VSS160 VSS224 B26 F50 VSS288 VSS332 W20
AG21 VSS33 VSS97 AL54 AT63 VSS161 VSS225 B28 F54 VSS289 VSS333 W22
AG23 VSS34 VSS98 AL57 AU1 VSS162 VSS226 B32 F58 VSS290 VSS334 Y10
AG60 VSS35 VSS99 AL60 AU16 VSS163 VSS227 B36 F61 VSS291 VSS335 Y59
AG61 VSS36 VSS100 AL61 AU18 VSS164 VSS228 B4 G18 VSS292 VSS336 Y63
AG62 VSS37 VSS101 AM1 AU20 VSS165 VSS229 B40 G22 VSS293 VSS337
AG63 VSS38 VSS102 AM17 AU22 VSS166 VSS230 B44 G3 VSS294
AH17 VSS39 VSS103 AM23 AU24 VSS167 VSS231 B48 G5 VSS295 V58
AH19 VSS40 VSS104 AM31 AU26 VSS168 VSS232 B52 G6 VSS296 VSS338 AH46
AH20 VSS41 VSS105 AM52 AU28 VSS169 VSS233 B56 G8 VSS297 VSS339 V23
AH22 VSS42 VSS106 AN17 AU30 VSS170 VSS234 B60 H13 VSS298 VSS340 E62 RC131 1 2
VSS43 VSS107 VSS171 VSS235 VSS299 VSS_SENSE CPU_VSS_SENSE 43
AH24 AN23 AU33 C11 AH16 0_0402_5%
VSS44 VSS108 VSS172 VSS236 VSS341

2
AH28 AN31 AU51 C14 16 OF 19
AH30 VSS45 VSS109 AN32 AU53 VSS173 VSS237 C18 HASWELL-ULT-DDR3L_BGA1168
AH32 VSS46 VSS110 AN35 AU55 VSS174 VSS238 C20 RC132
AH34 VSS47 VSS111 AN36 AU57 VSS175 VSS239 C25 @ 100_0402_1%
AH36 VSS48 VSS112 AN39 AU59 VSS176 VSS240 C27

1
AH38 VSS49 VSS113 AN40 AV14 VSS177 VSS241 C38
AH40 VSS50 VSS114 AN42 AV16 VSS178 VSS242 C39
AH42 VSS51 VSS115 AN43 AV20 VSS179 VSS243 C57
VSS52 VSS116 VSS180 VSS244 VSS_SENSE
AH44 AN45 AV24 D12 Length Match: No More Than 25Mil
AH49 VSS53 VSS117 AN46 AV28 VSS181 VSS245 D14
B
VSS54 VSS118 VSS182 VSS246 Space: More Than 25Mil B
AH51 AN48 AV33 D18
AH53 VSS55 VSS119 AN49 AV34 VSS183 VSS247 D2 GND Reference
AH55 VSS56 VSS120 AN51 AV36 VSS184 VSS248 D21
AH57 VSS57 VSS121 AN52 AV39 VSS185 VSS249 D23
AJ13 VSS58 VSS122 AN60 AV41 VSS186 VSS250 D25
AJ14 VSS59 VSS123 AN63 AV43 VSS187 VSS251 D26
AJ23 VSS60 VSS124 AN7 AV46 VSS188 VSS252 D27
AJ25 VSS61 VSS125 AP10 AV49 VSS189 VSS253 D29
AJ27 VSS62 VSS126 AP17 AV51 VSS190 VSS254 D30
AJ29 VSS63 VSS127 AP20 AV55 VSS191 VSS255 D31
VSS64 VSS128 VSS192 15 OF 19 VSS256
HASWELL-ULT-DDR3L_BGA1168

14 OF 19 @
HASWELL-ULT-DDR3L_BGA1168
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 12 of 45
5 4 3 2 1
 5 4 3 2 1

Haswell MCP (OTHER) UC1Q HSW_ULT_DDR3L

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4 1 @ TP59
TP60 @ 1 TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 CFG4 2 1
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60 1 @ TP64 RC1633 1K_0402_1%
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
TP67 @ 1 TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62 1 @ TP66
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 TP_DC_TEST_AV1 1 @ TP34
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW1 1 @ TP40
D DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 D
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 CFG4
AW63 TP_DC_TEST_AW63 1 @ TP45 *L: Embedded DisplayPort Enabled
17 OF 19 DAISY_CHAIN_NCTF_AW63
HASWELL-ULT-DDR3L_BGA1168
H: Embedded DisplayPort Disabled
@

UC1R HSW_ULT_DDR3L

N23
RSVD42 R23 CFG0 2 @ 1
RSVD43 T23 RC1634 1K_0402_1%
AT2 RSVD44
RSVD35 U10 CFG1 2 @ 1
AU44 RSVD45
RSVD36 RC1635 1K_0402_1%
AV44
RSVD37 CFG8 2 @ 1
D15
RSVD38 AL1 RC1644 1K_0402_1%
RSVD46 AM11 CFG9 2 @ 1
RSVD47 AP7 RC166 1K_0402_1%
F22 RSVD48
RSVD39 AU10 CFG10 2 @ 1
H22 RSVD49
RSVD40 AU15 RC167 1K_0402_1%
J21 RSVD50
RSVD41 AW14
C RSVD51 C
AY14
RSVD52

18 OF 19
HASWELL-ULT-DDR3L_BGA1168
@

UC1S HSW_ULT_DDR3L

TP84 @ 1CFG0 AC60 AV63 1 @ TP56 CFG3 2 1

TP85 @ 1CFG1 AC62 CFG0 RSVD_TP5 AU63 1 @ TP57 RC1636 1K_0402_1%
1CFG2 AC63 CFG1 RSVD_TP6
TP86 @
CFG2 CFG3 @
TP87 @ 1CFG3 AA63 1: Disable
TP88 @ 1CFG4 AA60 CFG3 C63 1 @ TP58
CFG4 RSVD_TP7 0: Enable, Set DFX Enabled BIT
TP89 @ 1CFG5 Y62 C62 1 @ TP62
TP90 @ 1CFG6 Y61 CFG5 RSVD_TP8 B43 In Debug Interface MSR
TP91 @ 1CFG7 Y60 CFG6 RSVD58
TP92 @ 1CFG8 V62 CFG7 A51 1 @ TP63
TP93 @ 1CFG9 V61 CFG8 RSVD_TP9 B51 1 @ TP65
TP94 @ 1CFG10 V60 CFG9 RSVD_TP10
B B
TP96 @ 1CFG11 U60 CFG10 L60 1 @ TP69
TP98 @ 1CFG12 T63 CFG11 RSVD_TP11
TP99 @ 1CFG13 T62 CFG12 RESERVED N60
TP100 @ 1CFG14 T61 CFG13 RSVD59
TP101 @ 1CFG15 T60 CFG14 W23
CFG15 RSVD60 Y22
TP116 @ 1 CFG16 AA62 RSVD61 AY15 PROC_OPI_COMP 2 1
TP117 @ 1 CFG18 U63 CFG16 PROC_OPI_RCOMP RC135 49.9_0402_1%
1 CFG17 AA61 CFG18 AV62
TP155 @
CFG17 RSVD62 OPI_RCOMP
TP160 @ 1 CFG19 U62 D58 Width 20Mil
CFG19 RSVD63
Space 15Mil
2 1 CFG_RCOMP V63 P22
RC134 49.9_0402_1% CFG_RCOMP VSS342 N21 Length 500Mil
A5 VSS343
RSVD53 P20
CFG_RCOMP&TD_IREF RSVD64
Width 20Mil E1 R20
D1 RSVD54 RSVD65
Space 15Mil RSVD55
J20
Length 500Mil H18 RSVD56
2 1 TD_IREF B12 RSVD57
RC136 8.2K_0402_1% TD_IREF
19 OF 19
HASWELL-ULT-DDR3L_BGA1168
A A
@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCP (OTHER)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 13 of 45
5 4 3 2 1
 A B C D E F G H

+1.35V

1
+1.35V +1.35V
DDR SO-DIMM RD11
1.82K_0402_1%

Trace width:20 mils RD12 For RF request

2
2_0402_5% JDDRL
Space:20mils 1 2 +VREF_DQ_DIMMA 1 2
6 DDR_SA_VREFDQ VREF_DQ VSS_2
3 4 DDRA_DQ4
VSS_1 DQ4

CD95
33P_0402_16V7K
RF_NS@

CD104
33P_0402_16V7K
RF_NS@
1 DDRA_DQ0 5 6 DDRA_DQ5
DQ0 DQ5 DDRA_DQ[63:0] 6

CD103
2.2U_0603_6.3V6K

CD108
.1U_0402_10V6-K
CD29 RD13 1 1 DDRA_DQ1 7 8 1 1
0.022U_0402_16V7-K 1.82K_0402_1% 9 DQ1 VSS_4 10 DDRA_DQS#0
VSS_3 DQS0# DDRA_MA[15:0] 6
CD@ 11 12 DDRA_DQS0
2 CD@ 13 DM0 DQS0 14
DDRA_DQS[7:0] 6

2
VSS_5 VSS_6

1
2 2 DDRA_DQ2 15 16 DDRA_DQ6 2 2
RD14 DDRA_DQ3 17 DQ2 DQ6 18 DDRA_DQ7
1 DQ3 DQ7 DDRA_DQS#[7:0] 6 1
24.9_0402_1% 19 20
DDRA_DQ12 21 VSS_7 VSS_8 22 DDRA_DQ11
CD@ DDRA_DQ8 23 DQ8 DQ12 24 DDRA_DQ10

2
25 DQ9 DQ13 26
CD@ DDRA_DQS#1 27 VSS_9 VSS_10 28
DDRA_DQS1 29 DQS1# DM1 30
DQS1 RESET# DDRA_DRAMRST# 5
31 32
DDRA_DQ13 33 VSS_11 VSS_12 34 DDRA_DQ14
DDRA_DQ9 35 DQ10 DQ14 36 DDRA_DQ15 +1.35V
37 DQ11 DQ15 38
DDRA_DQ20 39 VSS_13 VSS_14 40 DDRA_DQ21
DDR Swap Table DQ16 DQ20
DDRA_DQ17 41 42 DDRA_DQ16
43 DQ17 DQ21 44
DDRA_DQS#2 45 VSS_15 VSS_16 46
New Net Name Pin Number Old Net Name DQS2# DM2
DDRA_DQS2 47 48
49 DQS2 VSS_18 50 DDRA_DQ22 1 QC6
DDRA_DQ18 51 VSS_17 DQ22 52 DDRA_DQ23 D
DDRA_DQ19 53 DQ18 DQ23 54 1 2 2
DQ19 VSS_20 5,39 CPU_DRAMPG_CNTL
55 56 DDRA_DQ29 RD56 G
DDRA_DQ24 57 VSS_19 DQ28 58 DDRA_DQ25 0_0402_5% 1 S
DDRA_DQ28 59 DQ24 DQ29 60 PJA138K_SOT23-3
61 DQ25 VSS_22 62 DDRA_DQS#3 CD257 3
63 VSS_21 DQS3# 64 DDRA_DQS3
DM3 DQS3 .1U_0402_10V6-K
65 66 @2
DDRA_DQ26 67 VSS_23 VSS_24 68 DDRA_DQ30 1 2 DDRA_ODT0
DDRA_DQ27 69 DQ26 DQ30 70 DDRA_DQ31 RD53 66.5_0402_1%
71 DQ27 DQ31 72 DDRA_ODT 1 2 DDRA_ODT1
VSS_25 VSS_26 RD54 66.5_0402_1%

6 DDRA_CKE0 73 74
CKE0 CKE1 DDRA_CKE1 6
75 76
77 VDD_1 VDD_2 78 DDRA_MA15
79 NC_1 A15 80 DDRA_MA14
6 DDRA_BS2# BA2 A14
81 82
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD_5 VDD_6 90 DDRA_MA6
2 2
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
DDRA_MA3 95 VDD_7 VDD_8 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
99 A1 A0 100
101 VDD_9 VDD_10 102
6 DDRA_CLK0 CK0 CK1 DDRA_CLK1 6
6 DDRA_CLK0# 103 104
CK0# CK1# DDRA_CLK1# 6
105 106
DDRA_MA10 107 VDD_11 VDD_12 108 +1.35V
A10/AP BA1 DDRA_BS1# 6
6 DDRA_BS0# DDRA_BS0# 109 110
BA0 RAS# DDRA_RAS# 6
111 112
VDD_13 VDD_14

1
6 DDRA_WE# 113 114
WE# S0# DDRA_CS0# 6
6 DDRA_CAS# 115 116 DDRA_ODT0 RD6
117 CAS# ODT0 118 1.82K_0402_1%
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1
121 A13 ODT1 122 RD9
6 DDRA_CS1# Trace width:20 mils

2
123 S1# NC_2 124 2_0402_5%
125 VDD_17 VDD_18 126 +VREF_CA
Space:20mils 1 2
TEST VREF_CA DDR_SM_VREFCA 6
127 128 1
VSS_27 VSS_28

.1U_0402_10V6-K
DDRA_DQ37 129 130 DDRA_DQ36 CD20
DDRA_DQ32 131 DQ32 DQ36 132 DDRA_DQ33 0.022U_0402_16V7-K
DQ33 DQ37 1 1
133 134 CD94 CD98
DDRA_DQS#4 135 VSS_29 VSS_30 136 2.2U_0603_6.3V6K 2 CD@
DQS4# DM4

1
DDRA_DQS4 137 138
139 DQS4 VSS_32 140 DDRA_DQ38 2 2 CD@ RD7
DDRA_DQ34 141 VSS_31 DQ38 142 DDRA_DQ39 1.82K_0402_1% RD8
DDRA_DQ35 143 DQ34 DQ39 144 24.9_0402_1%
145 DQ35 VSS_34 146 DDRA_DQ44

2
DDRA_DQ40 147 VSS_33 DQ44 148 DDRA_DQ45 CD@
DDRA_DQ41 149 DQ40 DQ45 150
151 DQ41 VSS_35 152 DDRA_DQS#5 CD@
153 VSS_36 DQS5# 154 DDRA_DQS5
155 DM5 DQS5 156
DDRA_DQ42 157 VSS_37 VSS_38 158 DDRA_DQ46
DDRA_DQ43 159 DQ42 DQ46 160 DDRA_DQ47
161 DQ43 DQ47 162
DDRA_DQ48 163 VSS_39 VSS_40 164 DDRA_DQ52
3
VDDQ(2A) DQ48 DQ52 3
Decoupling CAP DDRA_DQ49 165 166 DDRA_DQ53
167 DQ49 DQ53 168
DDRA_DQS#6 169 VSS_41 VSS_42 170
4 PCS 1UF CAP Near Each Side Of DIMM VDD Pin DQS6# DM6
4PCS 10UF CAP Near Each Side Of DIMM VDD Pin DDRA_DQS6 171 172
173 DQS6 VSS_44 174 DDRA_DQ54
DDRA_DQ50 175 VSS_43 DQ54 176 DDRA_DQ55
VTT(700mA) DQ50 DQ55
Decoupling CAP DDRA_DQ51 177 178
179 DQ51 VSS_46 180 DDRA_DQ60
DDRA_DQ56 181 VSS_45 DQ60 182 DDRA_DQ61
4PCS 0.1UF CAP Near The DIMM DQ56 DQ61
2PCS 10UF CAP On the VTT Island DDRA_DQ57 183 184
185 DQ57 VSS_48 186 DDRA_DQS#7
187 VSS_47 DQS7# 188 DDRA_DQS7
189 DM7 DQS7 190
DDRA_DQ58 191 VSS_49 VSS_50 192 DDRA_DQ62
DDRA_DQ59 193 DQ58 DQ62 194 DDRA_DQ63
195 DQ59 DQ63 196
+0.68VS RD16 1 2 0_0402_5%197 VSS_51 VSS_52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA PM_SMB_DAT 7,31
201 202
SA1 SCL PM_SMB_CLK 7,31
203 204 +0.68VS
VTT_1 VTT_2
2

1 1 1 1 1 1 1 1
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M

2.2U_0603_6.3V6K

.1U_0402_10V6-K

RD22 205 206

GND1 GND2
CD115

CD65

CD66

CD88

CC53

CC55

CD102

CD99

0_0402_5% 207 208

BOSS1 BOSS2
2 2 2 2 2 2 2 2
1

LCN_DAN06-K4406-0103

CD@ ME@ DIMM ADRESS:

SA1:SA0 00
CD@

+1.35V

4 4
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD100

CD97

CD106

CD96

CD101

CD105

CD93

CD91

CD90

CD107

CD109

CD110

CD111

CD112

CD113

CD114

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

CD@ CD@ CD@ CD@
CD@ CD@ CD@ CD@
Issued Date 2013/03/26 Deciphered Date 2013/02/01 DDR3L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 14 of 45
A B C D E F G H
 5 4 3 2 1

N15x GPIO
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
GPIO I/O ACTIVE Function Description
FBVDDQ PCI Express I/O and Other
GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD
GPIO0 OUT - FB Enable for GC6 2.0 (4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.05V) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W)
D GPIO1 OUT N/A D

N14X
GPIO2 OUT N/A 128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
2GB
DDR3
GPIO3 OUT N/A

GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

N15x Multi-level Straps
GPIO10 OUT N/A

GPIO11 OUT - GPU Core VDD PWM control signal

GPIO12 IN AC Power Detect Input (10K pull High)

Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
C ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED C
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

GPIO20 N/A SMBUS_ALT_ADDR

GPIO21 OUT GPU PCIe self-reset control 0 0x9E (Default)

OVERT OUT Active Low Thermal Catastrophic Over Temperature 1 0x9C (Multi-GPU usage)

N15V-GM Power Sequence

B
N15x Binary Straps B

+3VG_AON Other Power rail

+VGA_CORE
+3VG_AON
tNVVDD >0
Physical
Strapping pin Power Rail Strap Mapping
+1.35VGS Tpower-off <10ms ROM_SCLK +3VGS SMB_ALT_ADDR
tFBVDDQ >0
ROM_SI +3VGS SUB_VENDOR
+1.05VS_VGA
ROM_SO +3VGS VGA_DEVICE
tPEX_VDD >0
STRAP0 +3VGS RAM_CFG[0]
1.all GPU power rails should be turned off within 10ms STRAP1 +3VGS RAM_CFG[1]
1. all power rail ramp up time should be larger than 40us 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
STRAP2 +3VGS RAM_CFG[2]
STRAP3 +3VGS RAM_CFG[3]
STRAP4 +3VGS PCIE_MAX_SPEED
N15S-GT Power Sequence

+3VG_AON

+VGA_CORE
A A

tNVVDD >0
+1.05VS_VGA

+1.35VGS
tPEX_VDD >0
Security Classification LC Future Center Secret Data Title

1. all power rail ramp up time should be larger than 40us and less than 2ms . Issued Date 2013/08/08 Deciphered Date 20140213 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 15 of 45
5 4 3 2 1
 5 4 3 2 1

4 GC6_FB_EN RV1 1 GC6@ 2 0_0402_5% FB_GC6_EN_R

RV2 1 GC6@ 2 0_0402_5% GPU_EVENT#

4 PCH_GPU_EVENT#

9 PCIE_CRX_GTX_N[0..3]

9 PCIE_CRX_GTX_P[0..3]

9 PCIE_CTX_C_GRX_N[0..3]
UV1A
9 PCIE_CTX_C_GRX_P[0..3]
+3VGS
Part 1 of 6 1 RV175 2 0_0402_5%
H_THRMTRIP# 9
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN @
D PEX_RX0 GPIO0 FB_GC6_EN 20 D

.1U_0402_10V6-K
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N0 AG7 B2
PEX_RX0_N GPIO1

1
PCIE_CTX_C_GRX_P1 AF7 D6 1
PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7 RV4
PCIE_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9 10K_0402_5% CV1
PEX_RX2 GPIO4
2

PCIE_CTX_C_GRX_N2 AF9 A3 3VGS_PWR_EN @ @

PEX_RX2_N GPIO5 3VGS_PWR_EN 18,42

3
RV3 RV5 PCIE_CTX_C_GRX_P3 AG9 A4 GPU_EVENT#_R D 2

2
PEX_RX3 GPIO6

5
2.2K_0402_5% 2.2K_0402_5% PCIE_CTX_C_GRX_N3 AG10 B6 5

G
OPT@ OPT@ AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON# G
AE10 NC81 GPIO8 F8 VGA_ALERT#
A6 Symbol update to OVER QV2B
1

NC82 GPIO9

6
AE12 C5 D S 2N7002KDWH_SOT363-6

4
VGA_SMB_CK2 4
S
3 AF12 NC83 GPIO10 E7 NVVDD_PWM_VID DV1 OVERT# 2 @
EC_SMB_CLK0 7,29,31 NC84 GPIO11 NVVDD_PWM_VID 42

D
AG12 D7 VGA_AC_DET_R 2 1 G
NC85 GPIO12 VGA_AC_DET 29
AG13 B4 PSI_VGA_R @ QV2A

GPIO
QV1B AF13 NC86 GPIO13 B3 RB751V-40_SOD323-2 S 2N7002KDWH_SOT363-6

1
2N7002KDWH_SOT363-6 AE13 NC87 GPIO14 C3 @
NC88 GPIO15 2 RV6
2

OPT@ AE15 D5 1 PSI_VGA

G

NC1 GPIO16 PSI_VGA 42

1
RV7 2 @ 1 0_0402_5% AF15 D4 N15SGT@ 0_0402_5% D
NC2 GPIO17

.1U_0402_10V6-K
AG15 C2 PLT_RST_VGA# 1 RV8 2 0_0402_5% 2 1
AG16 NC3 GPIO18 F7 @ G
NC4 GPIO19

.1U_0402_10V6-K
VGA_SMB_DA2 1 6 AF16 E6 QV3 CV2
S

EC_SMB_DAT0 7,29,31 NC5 GPIO20

D

AE16 C4 GPU_PEX_RST_HOLD# S 2N7002KW_SOT323-3 @

3
AE18 NC6 GPIO21 @ 2
NC7 1
QV1A AF18 A6 OVERT# CV3
2N7002KDWH_SOT363-6 AG18 NC8 OVERT AB6
AG19 NC9 NC33 @
OPT@
NC10 2
RV9 2 @ 1 0_0402_5% PU AT CPU SIDE, +3VS AND 2.2K AF19
NC11
RV174
AE19 PLT_RST_VGA# 1 2 1K_0402_5%
NC12

.1U_0402_10V6-K
AE21 AG3
AF21 NC13 NC97 AF4 @
NC14 NC98 1
AG21 AF3 CV218
NC15 NC99

2
AG22 @

G
NC16 +3VG_AON +3VG_AON
2
+3VS PCIE_CRX_GTX_P0 CV10 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P0 AC9 AE3
PEX_TX0 NC100

DACs
RV10 PCIE_CRX_GTX_N0 CV13 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N0 AB9 AE4 OVERT# 3 1
PEX_TX0_N NC101 WRST# 29

D
+3VGARST 2 @ 1 PCIE_CRX_GTX_P1 CV8 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P1 AB10
PCIE_CRX_GTX_N1 CV9 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1
PEX_TX1_N 1 QV23

2
PCI EXPRESS

.1U_0402_10V6-K
C 0_0402_5% +3VG_AON PCIE_CRX_GTX_P2 CV6 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P2 AD11 1 C
PCIE_CRX_GTX_N2 CV7 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 W5 CV221 2N7002KW_SOT323-3 RV13
RV12 1 2 0_0402_5% PCIE_CRX_GTX_P3 CV4 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_P3 AC12 PEX_TX2_N NC102 AE2 0.01U_0402_25V7K 10K_0402_5% CV12
@
PEX_TX3 NC103

2
@ PCIE_CRX_GTX_N3 CV5 OPT@ 1 2 .1U_0402_10V6-K PCIE_CRX_C_GTX_N3 AB12 AF2 @ 2 GC6@ GC6@

G
AB13 PEX_TX3_N NC104 2

1
AC13 NC89
1 NC90
AD14
UV2 NC91
CV11 AC14 GPU_EVENT#_R 3 1 GPU_EVENT#
NC92

D
.1U_0402_10V6-K AC15
PCH_PLT_RST# 1 5 2 OPT@ AB15 NC93 QV4
8,29,30 PCH_PLT_RST# B VCC NC94
AB16 B7 VGA_CRT_CLK 2N7002KW_SOT323-3
2 AC16 NC95 I2CA_SCL A7 VGA_CRT_DATA GC6@
4 PCH_GPU_RST# A AD17 NC96 I2CA_SDA
I2C,if not use, can be soft grounded
Connect to CPU GPIO
3 4 SYS_PEX_RST_MON# AC17 NC17 C9 I2CB_SCL 1 @ 2 RV15
GND Y AC18 NC18 I2CB_SCL C8 I2CB_SDA
and delete pull up resistor ---colin 0_0402_5%
NC19 I2CB_SDA

I2C
AB18
AB19 NC20 A9 I2CC_SCL
74LVC1G08GW_SOT353-1-5 AC19 NC21 I2CC_SCL B9 I2CC_SDA
OPT@ 2 1 AD20 NC22 I2CC_SDA
RV14 10K_0402_5% AC20 NC23 D9 VGA_SMB_CK2 +3VG_AON +3VG_AON
OPT@ AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2
NC25 I2CS_SDA Internal Thermal Sensor
AB21
1 2 RV16 AD23 NC26
@ 0_0402_5% AE23 NC27 VGA_CRT_DATA RV17 1 2 3VGS_PWR_EN RV18 2 1
AF24 NC28 60mA OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AE24 NC29 L6 +PLLVDD VGA_CRT_CLK RV19 1 2 OVERT# RV20 1 2
AG24 NC30 CORE_PLLVDD M6 OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
AG25 NC31 SP_PLLVDD I2CB_SCL RV22 1 2 VGA_ALERT# RV23 1 2
NC32 N6
45mA 1 2 RV24 +SP_PLLVDD OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
VID_PLLVDD @ 0_0402_5% I2CB_SDA RV25 1 2 VGA_AC_DET_R RV26 1 2
45mA OPT@ 2.2K_0402_5% OPT@ 100K_0402_5%
+3VGS +3VG_AON 8 CLK_PCIE_GPU CLK_PCIE_GPU AE8 I2CC_SCL RV28 1 2 PSI_VGA RV29 1 2
CLK_PCIE_GPU# AD8 PEX_REFCLK OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
8 CLK_PCIE_GPU# PEX_REFCLK_N
CLK_REQ_GPU# AC6 I2CC_SDA RV30 1 2 GPU_PEX_RST_HOLD#RV31 1 2
PEX_CLKREQ_N OPT@ 2.2K_0402_5% OPT@ 10K_0402_5%
1 2 RV32 PEX_TSTCLK_OUT AF22 XTALOUT RV33 1 2

CLK
Differential signal @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN @ 10K_0402_5% OVERT# RV27 1 2
PEX_TSTCLK_N XTAL_IN
2

0526 new symbol for haydn . B10 XTAL_OUT @ 100K_0402_5%

B
RV180 RV37 XTAL_OUT B
2.2K_0402_5% 10K_0402_5% PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV34 10K_0402_5%
GC6@ @ 1 2 RV35 PEX_TERMP AF25 PEX_RST_N XTAL_SSIN C10 XTALOUT 1 OPT@ 2 RV36 10K_0402_5%
PEX_TERMP XTAL_OUTBUFF Under GPU(below 150mils)
DV6 OPT@ 2.49K_0402_1% 180ohms (ESR=0.2) Bead
1

GPU_PEX_RST_HOLD# 3
1 PLT_RST_VGA# N15S-GT-S-A2_FCBGA595 +SP_PLLVDD 1 2 LV1 +1.05VGS
SYS_PEX_RST_MON# 2 N15SGT@

22U_0805_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0402_6.3V6M
150mA 1
CV15
1
CV16
1
CV17
1
CV18 PBY100505T-181Y-N_2P
BAT54AW_SOT323-3 OPT@
GC6@ 4.7uFX1 ,0.1uFX2 , 22uFX1
2 2 2 2
1 2 RV39 OPT@ OPT@ OPT@ OPT@
@ 0_0402_5%

1 2 RV38
change to BAT54A for cost down OPT@ 10M_0402_5%
YV1
Under GPU Near GPU 30ohms (ESR=0.05) Bead
+3VG_AON +3VG_AON XTAL_IN 1 4
OSC1 GND2 +PLLVDD 1 2 LV2 +1.05VGS
2 3 XTAL_OUT
GND1 OSC2
1 1 PBY100505T-300Y-N_2P
2

1 1
RV40 RV41 CV21 CV22 OPT@
10K_0402_5% 10K_0402_5% CV19 27MHZ_10PF_7V27000050 CV20 0.1U_0402_10V7K 22U_0603_6.3V6-M
OPT@ @ 12P_0402_50V8-J 12P_0402_50V8-J OPT@ 2 2
2 OPT@ 2
0.1uFX1 , 22uFX1
OPT@ OPT@ OPT@
1

+3VG_AON +3VG_AON
.1U_0402_10V6-K

.1U_0402_10V6-K

1 1
CV23 CV24
OPT@ @
2

2
2

A
2 RV44 2 RV45 A
2
G

10K_0402_5% 10K_0402_5%
OPT@ @
1

7,8 GPU_PCIE_CLKREQ# 6 1 CLK_REQ_GPU# FB_GC6_EN_R 1 3 FB_GC6_EN

D

QV6
2

2N7002KW_SOT323-3
QV5A RV46 @ RV47
AO5804EL_SC89-6 10K_0402_5% 10K_0402_5%
OPT@ @ 3
Connect to CPU GPIO GC6@ Title
1 2 RV48 QV5B 1 2 RV49 Security Classification LC Future Center Secret Data
1

@ 0_0402_5% GC6@ 0_0402_5%

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_PCIE/ DAC/ GPIO
OPT@ 5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
4
AO5804EL_SC89-6
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 16 of 45
5 4 3 2 1
 5 4 3 2 1

D D
UV1C

Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
B19 Symbol update to FBA_CMD32
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57

NC
AA1 G3
AA4 NC112 NC58 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 2 1 RV50
BUFRST_N @ 10K_0402_5%
Symbol update to GPIO8

LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
R2 NC128 NC71

GENERAL
R3 NC129 F10
N2 NC130 NC72
N3 NC131 +3VG_AON
NC132 D1 STRAP0
STRAP0 STRAP0 23
C D2 STRAP1 C
STRAP1 STRAP1 23
V3 E4 STRAP2
NC133 STRAP2 STRAP2 23

1
V4 E3 STRAP3
NC134 STRAP3 STRAP3 23
U3 D3 STRAP4 RV21
NC135 STRAP4 STRAP4 23
U4 C1 10K_0402_5%
T4 NC136 NC73
NC137 @
T5

2
R4 NC138 F6 MULTI_STRAP_REF0_GND
R5 NC139 MULTI_STRAP_REF0_GND F4
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5
MULTI_STRAP_REF2_GND

2
N1 RV51
M1 NC34
NC35 40.2K_0402_1%
M2 F12 N15SGT@
M3 NC36 THERMDP

1
K2 NC37 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41

M4 F2 VCCSENSE_VGA VCCSENSE_VGA 42
M5 NC42 VDD_SENSE
L3 NC43
NC44 trace width: 16mils
L4
K4 NC45 differential voltage sensing.
NC46 differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA 42

J5
N4 NC49
N5 NC141 TEST
NC142
P3 AD9 TESTMODE 1 OPT@ 2 RV52
P4 NC143 TESTMODE AE5 @ 1 10K_0402_5%
B NC144 JTAG_TCK TV1 B
AE6 @ 1
JTAG_TDI TV2
AF6 @ 1
JTAG_TDO TV3
J2 AD6 @ 1
NC145 JTAG_TMS TV4
J3 AG4 1 2 RV53
NC146 JTAG_TRST_N OPT@ 10K_0402_5%

H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N TV5
B12 ROM_SI
ROM_SI ROM_SI 23
A12 ROM_SO
ROM_SO ROM_SO 23
C12 ROM_SCLK
ROM_SCLK ROM_SCLK 23

N15S-GT-S-A2_FCBGA595
N15SGT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_LVDS/ HDMI/ THERM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 17 of 45
5 4 3 2 1
 5 4 3 2 1

4.7uFX2 ,1uFX2 ,0.1uFX2 ,22uFX1 ,10uFX1

UV1D
Near GPU 4.7uFX1 ,1uFX1 , 22uFX1 ,10uFX1
+1.35VGS Near GPU Under GPU(below 150mils)
2000mA +1.05VGS
3.5A Part 4 of 6
B26 AA10 For RF
FBVDDQ_01 PEX_IOVDDQ_1

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
C25 AA12

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_02 PEX_IOVDDQ_2

1U_0603_25V6M

1U_0603_25V6M

CV33

CV37

CV39

CV215
E23 AA13 1 1 2 1
FBVDDQ_03 PEX_IOVDDQ_3

CV25

CV26

CV27

CV28

CV29

CV30

CV31

CV32
1 2 1 1 1 1 1 1 E26 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19 RF_OPTNS@
G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 1 2
2 1 2 2 2 2 2 2 G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 OPT@ OPT@
FBVDDQ_08 PEX_IOVDDQ_8 OPT@
CD@ OPT@ OPT@ OPT@ OPT@ CD@ OPT@ OPT@ G15 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
D FBVDDQ_10 PEX_IOVDDQ_10 Under GPU(below 150mils) +1.05VGS PEX_IOVVDD/Q Decouling D
G18 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25
FBVDDQ_12 PEX_IOVDDQ_12

22U_0805_6.3V6M
G20 AF26
FBVDDQ_13 PEX_IOVDDQ_13 1 MLCC N15S-GT

CV43
G21 AF27
L22 FBVDDQ_14 PEX_IOVDDQ_14
Symbol update to FBVDDQ_AON L24 FBVDDQ_19
H24/H26/J21/K21 L26 FBVDDQ_20 AA22 2
Under Near +3VG_AON 1.0uF 1
M21 FBVDDQ_21 PEX_IOVDD_1 AB23
FBVDDQ_22 PEX_IOVDD_2

.1U_0402_10V6-K

1U_0402_6.3V6K
N21 AC24

4.7U_0603_6.3V6K
OPT@
FBVDDQ_23 PEX_IOVDD_3 4.7uF 1

CV47

CV48

CV49
R21 AD25 1 1 1

POWER
T21 FBVDDQ_24 PEX_IOVDD_4 AE26
V21 FBVDDQ_25 PEX_IOVDD_5 AE27
W21 FBVDDQ_26 PEX_IOVDD_6 10uF 1
FBVDDQ_27 2 2 2
Symbol update to 3V3_AON
4.7uFX1 ,1uFX1 , 0.1uFX1 OPT@ OPT@ OPT@
H24 22uF 1
H26 FBVDDQ_AON_1 +3VG_AON
J21 FBVDDQ_AON_2 G10
FBVDDQ_AON_3 3V3_AON_1 Place near balls(Under GPU) Place near GPU
K21 G12
FBVDDQ_AON_4 3V3_AON_2 +3VGS
+1.05VS +1.05VGS
for GPU +1.05V V7 G8 +VDD33 RV54 1 2 0_0402_5%
NC149 3V3_MAIN_1

.1U_0402_10V6-K

.1U_0402_10V6-K

1U_0402_6.3V6K
G9

4.7U_0603_6.3V6K
@
3V3_MAIN_2

CV50

CV51

CV52

CV53
AON6414AL_DFN8-5 +1.35VGS 1 1 1 1 4.7uFX1 ,1uFX1 , 0.1uFX2
W7
1 AA6 NC150
2 W6 NC151 D22 FB_CAL_VDDQ 1 2 RV55
5 3 Y6 NC152 FB_CAL_VDDQ OPT@ 40.2_0402_1% 2 2 2 2
NC153 OPT@ OPT@ OPT@ OPT@
1
CV220 C24 FB_CAL_GND 1 2 RV56
0.1U_0402_16V4Z @ QV7 FB_CAL_GND OPT@ 42.2_0402_1%
B+ 4 OPT@
2 M7 B25 FB_CAL_TERM 1 2 RV57 CALIBRATION PIN DDR3
+5VALW 1 2 RV58 N7 NC154 FB_CAL_TERM OPT@ 51.1_0402_1%
NC155

1
100K_0402_5% T6
OPT@ RV59 P6 NC156 FB_CAL_x_PD_VDDQ 40.2Ohm
470_0603_5% NC157
RV60 1 Place near balls
6

QV8A D
C
1 2 EN_VGA# 2 CV54 @ FB_CAL_x_PU_GND 42.2Ohm C

2
G 0.01U_0402_25V7K T7 +3VG_AON
2 OPT@ R7 NC158
47K_0402_5%
2N7002KDWH_SOT363-6 6 NC159 Under GPU(below 150mils) FB_CAL_xTERM_GND 51.1Ohm
OPT@ S U6
1

NC160

.1U_0402_10V6-K
R6 AA8

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
OPT@
NC161 PEX_PLL_HVDD_1

CV55

CV56

CV57
@ AA9 1 1 1
PEX_PLL_HVDD_2
3

0_0402_5% QV8B D EN_VGA# 2 4.7uFX2 ,0.1uFX1

RV226 1 2 @ 5 AO5804EL_SC89-6 AB8
19,40,42 EN_VGA G QV10A PEX_SVDD_3V3
0_0402_5% 2N7002KDWH_SOT363-6 2 2 2
RV227 1 2 OPT@ S 1 J7 OPT@ OPT@ OPT@ +1.05VGS
,40,42 DGPU_PWROK 120mA 120ohm (ESR=0.18) Bead
4

K7 NC76
K6 NC77 AA14 +PEX_PLLVDD 2 @ 1 LV3
NC78 PEX_PLLVDD_1

1U_0603_25V6M
.1U_0402_10V6-K
H6 AA15

4.7U_0603_6.3V6K
OPT@ HCB1608KF-121T30_0603
NC79 PEX_PLLVDD_2

CV58

CV59

CV60
J6 1 1 1
NC80 @
1 2 RV62
0_0603_5%
2 2 2
OPT@ OPT@ OPT@
N15S-GT-S-A2_FCBGA595
N15SGT@
Place near balls 4.7uFX1 ,1uFX1 , 0.1uFX1
+3.3VS TO +3VG_AON

+3VS +3VG_AON

+5VALW
S

3 1
1

QV11 OPT@
1

B B
RV63 OPT@
G

1 1 1
2

47K_0402_5% @ LP2301ALT1G_SOT23-3 CV62 RV64 CV63

CV61 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M +1.35V +1.35VGS
.1U_0402_10V6-K @ @ OPT@ +1.35V TO +1.35VGS AON6414AL_DFN8-5
2

2 2 2
2

PXS_PWREN# 1 2 RV65 1
10K_0402_5% 2
OPT@ 1 5 3
6

220U_B2_2.5VM_R15M
QV12A D OPT@ CV67 CV68 CV69 CV70
3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K
2 CV64 QV12B D CV65 CV66 1
4 PXS_PWREN

1
G .1U_0402_10V6-K PXS_PWREN# 5 1 1 QV14 OPT@ 1 1 1

4
2N7002KDWH_SOT363-6 2 G + RV67
1

OPT@ S 2N7002KDWH_SOT363-6 470_0603_5%

1

OPT@ S @
4

2 2 2 2 2 2

OPT@

OPT@

OPT@

OPT@
@

@
RV66 OPT@

2
100K_0402_5%
3
2

B+ QV10B

+5VALW
1 OPT@2 RV68 FBVDDQ_PWR_EN# 5 @
100K_0402_5%

+3VG_AON +3VGS AO5804EL_SC89-6

RV69 1

6
QV17A D 4
+3.3VS TO +3VGS 1 2 FBVDDQ_PWR_EN# 2 CV71
G 0.01U_0402_25V7K
2N7002KDWH_SOT363-6 2 OPT@
47K_0402_5% OPT@ S

1
RV171 1 2 OPT@
0_0603_5% @

3
0_0402_5% QV17B D
+5VALW RV228 1 2 5
20 FBVDDQ_PWR_EN
S

3 1 G
QV16 GC6@ 2N7002KDWH_SOT363-6
1

OPT@ OPT@ S

4
1

RV71 GC6@
G

1 1 1
2

A 47K_0402_5% @ CV73 RV72 CV74 CV506 A

CV72 LP2301ALT1G_SOT23-3 0.01U_0402_25V7K 470_0603_5% 10U_0603_6.3V6M 0.22U_0402_10V6K
.1U_0402_10V6-K GC6@ @ GC6@ OPT@
2

2 2 2
2

DGPU_PWR_EN# 1 2
RV73 4.7K_0402_5%
GC6@ 1
6

QV19A D
3

2 CV75 QV19B D
16,42 3VGS_PWR_EN G .1U_0402_10V6-K DGPU_PWR_EN# 5
2N7002KDWH_SOT363-6 2 GC6@ G
Security Classification LC Future Center Secret Data Title
1

GC6@ S 2N7002KDWH_SOT363-6
1

GC6@ S
Issued Date 2013/08/08 Deciphered Date 20140213 N15X_Power
4

RV74 N15SGT@
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
2

C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 18 of 45
5 4 3 2 1
 5 4 3 2 1

D D

UV1E
UV1F
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE
A26 GND_001 GND_057 K13 Part 6 of 6
AB11 GND_002 GND_058 K15
GND_003 GND_059 4.7uFX15 ,1uFX4 ,47uFX1 ,22uFX1 ,330uFX1
AB14 K17 K10 V18
AB17 GND_004 GND_060 L10 K12 VDD_001 VDD_041 V16
AB20 GND_005 GND_061 L12 +VGA_CORE K14 VDD_002 VDD_040 V14
AB24 GND_006 GND_062 L14 K16 VDD_003 VDD_039 V12
GND_007 GND_063 Under GPU VDD_004 VDD_038
AC2 L16 K18 V10
AC22 GND_008 GND_064 L18 L11 VDD_005 VDD_037 U17
GND_009 GND_065 VDD_006 VDD_036

POWER
AC26 L2 L13 U15
AC5 GND_010 GND_066 L23 L15 VDD_007 VDD_035 U13

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AC8 GND_011 GND_067 L25 L17 VDD_008 VDD_034 U11
AD12 GND_012 GND_068 L5 M10 VDD_009 VDD_033 T18
GND_013 GND_069 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_010 VDD_032

CV76

CV77

CV78

CV79

CV80

CV81

CV82

CV83

CV84

CV85

CV86

CV87

CV88
AD13 M11 M12 T16
AD15 GND_014 GND_070 M13 M14 VDD_011 VDD_031 T14
AD16 GND_015 GND_071 M15 M16 VDD_012 VDD_030 T12
AD18 GND_016 GND_072 M17 2 2 2 2 2 2 2 2 2 2 2 2 2 M18 VDD_013 VDD_029 T10
AD19 GND_017 GND_073 N10 N11 VDD_014 VDD_028 R17
AD21 GND_018 GND_074 N12 OPT@ CD@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ @ @ @ N13 VDD_015 VDD_027 R15
AD22 GND_019 GND_075 N14 N15 VDD_016 VDD_026 R13
AE11 GND_020 GND_076 N16 N17 VDD_017 VDD_025 R11
AE14 GND_021 GND_077 N18 P10 VDD_018 VDD_024 P18
AE17 GND_022 GND_078 P11 P12 VDD_019 VDD_023 P16
GND_023 GND_079 For RF VDD_020 VDD_022

33P_0402_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AE20 P13 P14
GND_024 GND_080 VDD_021

CV89

CV90

CV91

CV92

CV213
AF1 P15 1 1 1 1 1
AF11 GND_025 GND_081 P17
AF14 GND_026 GND_082 P2
AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26 2 2 2 2 2
C C
AF23 GND_029 GND_085 P5 OPT@ OPT@ OPT@ OPT@ RF_OPTNS@
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N15S-GT-S-A2_FCBGA595
B1 GND_034 GND_090 R18

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
GND_035 GND_091 N15SGT@
B11 T11
B14 GND_036 GND_092 T13
GND_037 GND_093 1 1 1 1 1 1 1 1 1 1

CV93

CV94

CV95

CV96

CV97

CV98

CV99

CV100

CV101

CV102
B17 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12 2 2 2 2 2 2 2 2 2 2
B5 GND_041 GND_097 U14
B8 GND_042 GND_098 U16 OPT@ OPT@ OPT@ CD@ CD@ @ @ @ @ @
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
GND_047 GND_103

33P_0402_50V8J
E20 U5
GND_048 GND_104

CV214
E22 V11 1 1 1 1
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15 CV103 CV104 CV105
E8 GND_051 GND_107 V17 RF_OPTNS@
GND_052 GND_108 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M
H2 Y2 2 2 2 2
H23 GND_053 GND_109 Y23 OPT@ OPT@ CD@
GND_054 GND_110 For RF
H25 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

Near GPU
AA7
GND_113 AB7
GND_114

N15S-GT-S-A2_FCBGA595
B B
N15SGT@

+VGA_CORE
+5VALW
1

RV173
2

470_0603_5%
RV172 @
47K_0402_5%
6 2

@
QV21A D
1

2
G
3

QV21B D 2N7002KDWH_SOT363-6
5 @ S
18,40,42 EN_VGA
1

G
2N7002KDWH_SOT363-6
@ S
4

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_+VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 19 of 45
5 4 3 2 1
 5 4 3 2 1

FBA_D[0..63]
21,22 FBA_D[0..63]

21,22 FBA_DQM[7..0]
21,22 FBA_DQS[7..0]
21,22 FBA_DQS#[7..0]

UV1B
D D

Part 2 of 6

FBA_D0 E18 C27 FBA_CS0#

FBA_D00 FBA_CMD00 FBA_CS0# 21
FBA_D1 F18 C26
FBA_D2 E16 FBA_D01 FBA_CMD01 E24 FBA_ODT0
FBA_D02 FBA_CMD02 FBA_ODT0 21
FBA_D3 F17 F24 FBA_CKE0
FBA_D03 FBA_CMD03 FBA_CKE0 21
FBA_D4 D20 D27 FBA_A14
FBA_D5 D21 FBA_D04
FBA_D05
FBA_CMD04
FBA_CMD05
D26 FBA_RST#
FBA_A14
FBA_RST#
21,22
21,22
CMD mapping mod Mode D
FBA_D6 F20 F25 FBA_A9
FBA_D06 FBA_CMD06 FBA_A9 21,22
FBA_D7 E21 F26 FBA_A7 Rank0
FBA_D07 FBA_CMD07 FBA_A7 21,22
FBA_D8 E15 F23 FBA_A2
FBA_D08 FBA_CMD08 FBA_A2 21,22
FBA_D9 D15
FBA_D09 FBA_CMD09
G22 FBA_A0
FBA_A0 21,22 Address 0..31 32..63
FBA_D10 F15 G23 FBA_A4
FBA_D10 FBA_CMD10 FBA_A4 21,22
FBA_D11 F13 G24 FBA_A1 FBx_CMD0 CS0#
FBA_D11 FBA_CMD11 FBA_A1 21,22
FBA_D12 C13 F27 FBA_BA0
FBA_D12 FBA_CMD12 FBA_BA0 21,22
FBA_D13 B13 G25 FBA_WE FBx_CMD1
FBA_D13 FBA_CMD13 FBA_WE 21,22
FBA_D14 E13 G27
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CAS#
FBA_D15 FBA_CMD15 FBA_CAS# 21,22 FBx_CMD2 ODT0
FBA_D16 B15 M24 FBA_CS1#
FBA_D16 FBA_CMD16 FBA_CS1# 22
FBA_D17 C16 M23 FBx_CMD3 CKE0
FBA_D18 A13 FBA_D17 FBA_CMD17 K24 FBA_ODT1
FBA_D18 FBA_CMD18 FBA_ODT1 22
FBA_D19 A15 K23 FBA_CKE1 FBx_CMD4 A14 A14
FBA_D19 FBA_CMD19 FBA_CKE1 22
FBA_D20 B18 M27 FBA_A13
FBA_D20 FBA_CMD20 FBA_A13 21,22
FBA_D21 A18 M26 FBA_A8 FBx_CMD5 RST RST
FBA_D21 FBA_CMD21 FBA_A8 21,22
FBA_D22 A19 M25 FBA_A6
FBA_D22 FBA_CMD22 FBA_A6 21,22
FBA_D23 C19 K26 FBA_A11 FBx_CMD6 A9 A9
FBA_D23 FBA_CMD23 FBA_A11 21,22
FBA_D24 B24 K22 FBA_A5
FBA_D24 FBA_CMD24 FBA_A5 21,22
FBA_D25 C23 J23 FBA_A3 FBx_CMD7 A7 A7
FBA_D25 FBA_CMD25 FBA_A3 21,22
FBA_D26 A25 J25 FBA_BA2
FBA_D26 FBA_CMD26 FBA_BA2 21,22
FBA_D27 A24 J24 FBA_BA1 FBx_CMD8 A2 A2
FBA_D27 FBA_CMD27 FBA_BA1 21,22
FBA_D28 A21 K27 FBA_A12
FBA_D28 FBA_CMD28 FBA_A12 21,22
FBA_D29 B21 K25 FBA_A10 FBx_CMD9 A0 A0
FBA_D29 FBA_CMD29 FBA_A10 21,22
FBA_D30 C20 J27 FBA_RAS#
FBA_D30 FBA_CMD30 FBA_RAS# 21,22
FBA_D31 C21 J26 FBx_CMD10 A4 A4
FBA_D32 R22 FBA_D31 FBA_CMD31 B19 +1.35VGS
C FBA_D33 R24 FBA_D32 FBA_CMD32 Symbol update to FBA_CMD34/35 FBx_CMD11 A1 A1 C

INTERFACE A
FBA_D34 T22 FBA_D33 F22 RV121 2 @ 1 60.4_0402_1%
FBA_D35 R23 FBA_D34 FBA_CMD34 J22 RV122 2 1 60.4_0402_1%
FBA_D35 FBA_CMD35 FBx_CMD12 BA0 BA0
FBA_D36 N25 @
FBA_D37 N26 FBA_D36 D19 FBA_DQM0 FBx_CMD13 WE WE

MEMORY
FBA_D38 N23 FBA_D37 FBA_DQM0 D14 FBA_DQM1
FBA_D39 N24 FBA_D38 FBA_DQM1 C17 FBA_DQM2
30ohms (ESR=0.01) Bead FBA_D39 FBA_DQM2 FBx_CMD14 A15 A15
FBA_D40 V23 C22 FBA_DQM3
FBA_D41 V22 FBA_D40 FBA_DQM3 P24 FBA_DQM4
+1.05VGS +FB_PLLAVDD FBA_D41 FBA_DQM4 FBx_CMD15 CAS# CAS#
FBA_D42 T23 W24 FBA_DQM5
FBA_D43 U22 FBA_D42 FBA_DQM5 AA25 FBA_DQM6
200mA FBA_D43 FBA_DQM6 FBx_CMD16 CS1#
FBA_D44 Y24 U25 FBA_DQM7
1 2 LV4 FBA_D45 AA24 FBA_D44 FBA_DQM7
FBA_D45 FBx_CMD17
HCB1608KF-300T60_2P FBA_D46 Y22 F19 FBA_DQS#0
FBA_D47 AA23 FBA_D46 FBA_DQS_RN0 C14 FBA_DQS#1
OPT@ FBA_D47 FBA_DQS_RN1 FBx_CMD18 ODT1
FBA_D48 AD27 A16 FBA_DQS#2
FBA_D49 AB25 FBA_D48 FBA_DQS_RN2 A22 FBA_DQS#3
Place close to BGA FBA_D49 FBA_DQS_RN3 FBx_CMD19 CKE1
FBA_D50 AD26 P25 FBA_DQS#4
FBA_D51 AC25 FBA_D50 FBA_DQS_RN4 W22 FBA_DQS#5
0.1uFX2 ,22uFX1 FBA_D51 FBA_DQS_RN5 FBx_CMD20 A13 A13
FBA_D52 AA27 AB27 FBA_DQS#6
FBA_D53 AA26 FBA_D52 FBA_DQS_RN6 T27 FBA_DQS#7
Place close to BGA Place close to ball FBA_D53 FBA_DQS_RN7 FBx_CMD21 A8 A8
FBA_D54 W26
FBA_D55 Y25 FBA_D54 E19 FBA_DQS0
+FB_PLLAVDD FBA_D55 FBA_DQS_WP0 FBx_CMD22 A6 A6
22U_0603_6.3V6-M

0.1U_0402_10V7K

0.1U_0402_10V7K

FBA_D56 R26 C15 FBA_DQS1

FBA_D56 FBA_DQS_WP1
CV111

CV112

CV113

1 1 1 FBA_D57 T25 B16 FBA_DQS2 FBx_CMD23 A11 A11

FBA_D58 N27 FBA_D57 FBA_DQS_WP2 B22 FBA_DQS3
FBA_D59 R27 FBA_D58 FBA_DQS_WP3 R25 FBA_DQS4
FBA_D59 FBA_DQS_WP4 FBx_CMD24 A5 A5
FBA_D60 V26 W23 FBA_DQS5
2 2 2 FBA_D61 V27 FBA_D60 FBA_DQS_WP5 AB26 FBA_DQS6
FBA_D61 FBA_DQS_WP6 FBx_CMD25 A3 A3
OPT@ FBA_D62 W27 T26 FBA_DQS7
OPT@ OPT@ FBA_D63 W25 FBA_D62 FBA_DQS_WP7
FBA_D63 FBx_CMD26 BA2 BA2
D24 FBA_CLK0
FBA_CLK0 FBA_CLK0 21
F16 D25 FBA_CLK0# FBx_CMD27 BA1 BA1
FB_PLLAVDD_1 FBA_CLK0_N FBA_CLK0# 21
P22
FB_PLLAVDD_2 N22 FBA_CLK1
FBA_CLK1 FBA_CLK1 22 FBx_CMD28 A12 A12
D23 M22 FBA_CLK1#
FB_VREF FBA_CLK1_N FBA_CLK1# 22
+FB_PLLAVDD FBx_CMD29 A10 A10
Place close to ball D18
B
1 2 CV115 H22 FBA_WCK01 C18 B
0.1U_0402_10V7K FB_DLLAVDD FBA_WCK01_N FBx_CMD30 RAS# RAS#
OPT@ D17
FB_GC6_EN RV119 1 @ 2 0_0402_5% FB_CLAMP F3 FBA_WCK23 D16
FB_CLAMP FBA_WCK23_N FBx_CMD31
RV120 1 OPT@ 2 10K_0402_5% T24
FBA_WCK45 U24
FBA_WCK45_N FBx_CMD32
V24
FBA_WCK67 V25
FBA_WCK67_N FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1
N15S-GT-S-A2_FCBGA595
N15SGT@

RV123 DV4 GC6@

16 FB_GC6_EN FB_GC6_EN 1 2 0_0402_5% GC6_EN 2
@ 1
FBVDDQ_PWR_EN 18
3
1

+3VGS RV124 1 2 BAV70W-7-F_SOT323-3

10K_0402_5% RV125
200K_0402_5%
OPT@ GC6@
18,40,42 DGPU_PWROK
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 20 of 45
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes FBA_D[0..63] 20,22
+1.35VGS
D D
1

RANKA@
FBA_DQM[7..0] 20,22
RV128
1.33K_0402_1% UV6 UV5
FBA_DQS[7..0] 20,22
2

+FBA_VREFCA0 +FBA_VREFCA0 M8 E3 FBA_D25 +FBA_VREFCA0 M8 E3 FBA_D12

VREFCA DQL0 VREFCA DQL0 FBA_DQS#[7..0] 20,22
+FBA_VREFDQ0 H1 F7 FBA_D28 +FBA_VREFDQ0 H1 F7 FBA_D11
VREFDQ DQL1 VREFDQ DQL1 CMD mapping mod Mode D
1

1 F2 FBA_D27 F2 FBA_D15
RANKA@ CV116 FBA_A0 N3 DQL2 F8 FBA_D29 FBA_A0 N3 DQL2 F8 FBA_D8
.01U_0402_16V7-K 20,22 FBA_A0 A0 DQL3 Group3 A0 DQL3 Group1
RV127 FBA_A1 P7 H3 FBA_D26 FBA_A1 P7 H3 FBA_D9 Rank0
20,22 FBA_A1 A1 DQL4 A1 DQL4
1.33K_0402_1% RANKA@ FBA_A2 P3 H8 FBA_D30 FBA_A2 P3 H8 FBA_D14
2 20,22 FBA_A2 A2 DQL5 A2 DQL5
20,22 FBA_A3
FBA_A3 N2 G2 FBA_D24 FBA_A3 N2 G2 FBA_D13 Address 0..31 32..63
2

FBA_A4 P8 A3 DQL6 H7 FBA_D31 FBA_A4 P8 A3 DQL6 H7 FBA_D10

20,22 FBA_A4 A4 DQL7 A4 DQL7
FBA_A5 P2 FBA_A5 P2 FBx_CMD0 CS0#
20,22 FBA_A5 A5 A5
FBA_A6 R8 FBA_A6 R8
20,22 FBA_A6 A6 A6
FBA_A7 R2 D7 FBA_D1 FBA_A7 R2 D7 FBA_D17 FBx_CMD1
20,22 FBA_A7 A7 DQU0 A7 DQU0
FBA_A8 T8 C3 FBA_D6 FBA_A8 T8 C3 FBA_D23
20,22 FBA_A8 A8 DQU1 A8 DQU1
FBA_A9 R3 C8 FBA_D2 FBA_A9 R3 C8 FBA_D18 FBx_CMD2 ODT0
20,22 FBA_A9 A9 DQU2 A9 DQU2
FBA_A10 L7 C2 FBA_D5 FBA_A10 L7 C2 FBA_D20
20,22 FBA_A10 A10/AP DQU3 A10/AP DQU3
+1.35VGS FBA_A11 R7 A7 FBA_D0 Group0 FBA_A11 R7 A7 FBA_D16 Group2 FBx_CMD3 CKE0
20,22 FBA_A11 A11 DQU4 A11 DQU4
FBA_A12 N7 A2 FBA_D7 FBA_A12 N7 A2 FBA_D21
20,22 FBA_A12 A12/BC DQU5 A12/BC DQU5
FBA_A13 T3 B8 FBA_D3 FBA_A13 T3 B8 FBA_D22 FBx_CMD4 A14 A14
20,22 FBA_A13 A13 DQU6 A13 DQU6
1

FBA_A14 T7 A3 FBA_D4 FBA_A14 T7 A3 FBA_D19

20,22 FBA_A14 A14 DQU7 A14 DQU7
RANKA@ FBx_CMD5 RST RST
RV167 +1.35VGS +1.35VGS
1.33K_0402_1% FBx_CMD6 A9 A9
FBA_BA0 M2 B2 FBA_BA0 M2 B2
20,22 FBA_BA0
2

+FBA_VREFDQ0 FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA1 N8 BA0 VDD_1 D9

20,22 FBA_BA1 BA1 VDD_2 BA1 VDD_2 FBx_CMD7 A7 A7
FBA_BA2 M3 G7 FBA_BA2 M3 G7
20,22 FBA_BA2 BA2 VDD_3 BA2 VDD_3
1

1 K2 K2 FBx_CMD8 A2 A2
RANKA@ CV216 VDD_4 K8 VDD_4 K8
RV168 .01U_0402_16V7-K VDD_5 N1 VDD_5 N1
VDD_6 VDD_6 FBx_CMD9 A0 A0
1.33K_0402_1% RANKA@ FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
2 20 FBA_CLK0 CK VDD_7 CK VDD_7
FBA_CLK0# K7 R1 FBA_CLK0# K7 R1 FBx_CMD10 A4 A4
20 FBA_CLK0#
2

FBA_CKE0 K9 CK VDD_8 R9 FBA_CKE0 K9 CK VDD_8 R9

20 FBA_CKE0 CKE VDD_9 CKE VDD_9
FBx_CMD11 A1 A1
C C
FBA_ODT0 K1 A1 FBA_ODT0 K1 A1 FBx_CMD12 BA0 BA0
20 FBA_ODT0 ODT VDDQ_1 ODT VDDQ_1
FBA_CS0# L2 A8 FBA_CS0# L2 A8
20 FBA_CS0# CS VDDQ_2 CS VDDQ_2
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD13 WE WE
20,22 FBA_RAS# RAS VDDQ_3 RAS VDDQ_3
FBA_CAS# K3 C9 FBA_CAS# K3 C9
20,22 FBA_CAS# CAS VDDQ_4 CAS VDDQ_4
FBA_WE L3 D2 FBA_WE L3 D2 FBx_CMD14 A15 A15
20,22 FBA_WE WE VDDQ_5 WE VDDQ_5
E9 E9
VDDQ_6 F1 VDDQ_6 F1
VDDQ_7 VDDQ_7 FBx_CMD15 CAS# CAS#
FBA_DQS3 F3 H2 FBA_DQS1 F3 H2
FBA_CLK0 FBA_DQS0 C7 DQSL VDDQ_8 H9 FBA_DQS2 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9 DQSU VDDQ_9 FBx_CMD16 CS1#
FBx_CMD17
1

FBA_DQM3 E7 A9 FBA_DQM1 E7 A9
RV129 FBA_DQM0 D3 DML VSS_1 B3 FBA_DQM2 D3 DML VSS_1 B3
DMU VSS_2 DMU VSS_2 FBx_CMD18 ODT1
162_0402_1% E1 E1
RANKA@ VSS_3 G8 VSS_3 G8
VSS_4 VSS_4 FBx_CMD19 CKE1
FBA_DQS#3 G3 J2 FBA_DQS#1 G3 J2
2

FBA_DQS#0 B7 DQSL VSS_5 J8 FBA_DQS#2 B7 DQSL VSS_5 J8

DQSU VSS_6 DQSU VSS_6 FBx_CMD20 A13 A13
FBA_CLK0# M1 M1
VSS_7 M9 VSS_7 M9
VSS_8 VSS_8 FBx_CMD21 A8 A8
P1 P1
FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
20,22 FBA_RST# RESET VSS_10 RESET VSS_10 FBx_CMD22 A6 A6
1

T1 T1
RV131 1 2 RV130 L8 VSS_11 T9 L8 VSS_11 T9
ZQ VSS_12 ZQ VSS_12 FBx_CMD23 A11 A11

1
10K_0402_5% 243_0402_1%
RANKA@ RANKA@ RV132 FBx_CMD24 A5 A5
J1 B1 243_0402_1% J1 B1
2

L1 NC1 VSSQ_1 B9 RANKA@ L1 NC1 VSSQ_1 B9

NC2 VSSQ_2 NC2 VSSQ_2 FBx_CMD25 A3 A3
J9 D1 J9 D1

2
FBA_ODT0 L9 NC3 VSSQ_3 D8 L9 NC3 VSSQ_3 D8
NC4 VSSQ_4 NC4 VSSQ_4 FBx_CMD26 BA2 BA2
M7 E2 M7 E2
NC5 VSSQ_5 E8 NC5 VSSQ_5 E8
VSSQ_6 VSSQ_6 FBx_CMD27 BA1 BA1
FBA_CKE0 F9 F9
VSSQ_7 G1 VSSQ_7 G1
VSSQ_8 VSSQ_8 FBx_CMD28 A12 A12
G9 G9
VSSQ_9 VSSQ_9
1

FBx_CMD29 A10 A10

RV133 RV134 96-BALL 96-BALL
10K_0402_5% 10K_0402_5% SDRAM DDR3 SDRAM DDR3 FBx_CMD30 RAS# RAS#
B B
RANKA@ RANKA@ K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96
@ @ FBx_CMD31
2

FBx_CMD32
FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1

+1.35VGS UV6 SIDE +1.35VGS +1.35VGS UV5 SIDE +1.35VGS

For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV117

CV118

CV119

CV120

CV121

CV122

CV127

CV129

CV130

CV131

CV132

CV133

CV134

CV139
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2
For RF
RANKA@ RANKA@ RANKA@ RANKA@ CD@ RANKA@ RF_OPTNS@ RANKA@ RANKA@ CD@ RANKA@ RANKA@ RANKA@ RF_OPTNS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 DDR3 VRAM Rank0_L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 21 of 45
5 4 3 2 1
 5 4 3 2 1

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

+1.35VGS
1

D FBA_D[0..63] 20,21 D
RANKA@
RV135
1.33K_0402_1%
UV8 UV7
2

+FBA_VREFCA1
FBA_DQM[7..0] 20,21
+FBA_VREFCA1 M8 E3 FBA_D53 +FBA_VREFCA1 M8 E3 FBA_D40
VREFCA DQL0 VREFCA DQL0
1

1 +FBA_VREFDQ1 H1 F7 FBA_D55 +FBA_VREFDQ1 H1 F7 FBA_D43

VREFDQ DQL1 VREFDQ DQL1 FBA_DQS[7..0] 20,21
RANKA@ CV141 F2 FBA_D52 F2 FBA_D41
RV136 .01U_0402_16V7-K FBA_A0 N3 DQL2 F8 FBA_D50 FBA_A0 N3 DQL2 F8 FBA_D42
20,21 FBA_A0 A0 DQL3 A0 DQL3 Group5 FBA_DQS#[7..0] 20,21
1.33K_0402_1% RANKA@ FBA_A1 P7 H3 FBA_D48 Group6 FBA_A1 P7 H3 FBA_D45
2 20,21
20,21
FBA_A1
FBA_A2
FBA_A2 P3 A1 DQL4 H8 FBA_D51 FBA_A2 P3 A1 DQL4 H8 FBA_D47 CMD mapping mod Mode D
2

FBA_A3 N2 A2 DQL5 G2 FBA_D54 FBA_A3 N2 A2 DQL5 G2 FBA_D44

20,21 FBA_A3 A3 DQL6 A3 DQL6
FBA_A4 P8 H7 FBA_D49 FBA_A4 P8 H7 FBA_D46 Rank0
20,21 FBA_A4 A4 DQL7 A4 DQL7
FBA_A5 P2 FBA_A5 P2
20,21 FBA_A5 A5 A5
20,21 FBA_A6
FBA_A6 R8
A6
FBA_A6 R8
A6
Address 0..31 32..63
FBA_A7 R2 D7 FBA_D32 FBA_A7 R2 D7 FBA_D57
20,21 FBA_A7 A7 DQU0 A7 DQU0
FBA_A8 T8 C3 FBA_D39 FBA_A8 T8 C3 FBA_D63 FBx_CMD0 CS0#
20,21 FBA_A8 A8 DQU1 A8 DQU1
FBA_A9 R3 C8 FBA_D33 FBA_A9 R3 C8 FBA_D59
20,21 FBA_A9 A9 DQU2 A9 DQU2
+1.35VGS FBA_A10 L7 C2 FBA_D36 FBA_A10 L7 C2 FBA_D62 FBx_CMD1
20,21 FBA_A10 A10/AP DQU3 A10/AP DQU3
FBA_A11 R7 A7 FBA_D35 Group4 FBA_A11 R7 A7 FBA_D56 Group7
20,21 FBA_A11 A11 DQU4 A11 DQU4
FBA_A12 N7 A2 FBA_D38 FBA_A12 N7 A2 FBA_D61 FBx_CMD2 ODT0
20,21 FBA_A12 A12/BC DQU5 A12/BC DQU5
1

FBA_A13 T3 B8 FBA_D34 FBA_A13 T3 B8 FBA_D58

20,21 FBA_A13 A13 DQU6 A13 DQU6
RANKA@ FBA_A14 T7 A3 FBA_D37 FBA_A14 T7 A3 FBA_D60 FBx_CMD3 CKE0
20,21 FBA_A14 A14 DQU7 A14 DQU7
RV169
1.33K_0402_1% +1.35VGS +1.35VGS FBx_CMD4 A14 A14
2

+FBA_VREFDQ1 FBA_BA0 M2 B2 FBA_BA0 M2 B2 FBx_CMD5 RST RST

20,21 FBA_BA0 BA0 VDD_1 BA0 VDD_1
FBA_BA1 N8 D9 FBA_BA1 N8 D9
20,21 FBA_BA1 BA1 VDD_2 BA1 VDD_2
1

1 FBA_BA2 M3 G7 FBA_BA2 M3 G7 FBx_CMD6 A9 A9

20,21 FBA_BA2 BA2 VDD_3 BA2 VDD_3
RANKA@ CV217 K2 K2
RV170 .01U_0402_16V7-K VDD_4 K8 VDD_4 K8
VDD_5 VDD_5 FBx_CMD7 A7 A7
1.33K_0402_1% RANKA@ N1 N1
2 FBA_CLK1 J7 VDD_6 N9 FBA_CLK1 J7 VDD_6 N9
20 FBA_CLK1 FBx_CMD8 A2 A2
2

FBA_CLK1# K7 CK VDD_7 R1 FBA_CLK1# K7 CK VDD_7 R1

20 FBA_CLK1# CK VDD_8 CK VDD_8
FBA_CKE1 K9 R9 FBA_CKE1 K9 R9 FBx_CMD9 A0 A0
20 FBA_CKE1 CKE VDD_9 CKE VDD_9
FBx_CMD10 A4 A4
C FBA_ODT1 K1 A1 FBA_ODT1 K1 A1 C
20 FBA_ODT1 ODT VDDQ_1 ODT VDDQ_1
FBA_CS1# L2 A8 FBA_CS1# L2 A8 FBx_CMD11 A1 A1
20 FBA_CS1# CS VDDQ_2 CS VDDQ_2
FBA_RAS# J3 C1 FBA_RAS# J3 C1
20,21 FBA_RAS# RAS VDDQ_3 RAS VDDQ_3
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBx_CMD12 BA0 BA0
20,21 FBA_CAS# CAS VDDQ_4 CAS VDDQ_4
FBA_WE L3 D2 FBA_WE L3 D2
20,21 FBA_WE WE VDDQ_5 WE VDDQ_5
FBA_CLK1 E9 E9 FBx_CMD13 WE WE
VDDQ_6 F1 VDDQ_6 F1
FBA_DQS6 F3 VDDQ_7 H2 FBA_DQS5 F3 VDDQ_7 H2
DQSL VDDQ_8 DQSL VDDQ_8 FBx_CMD14 A15 A15
1

FBA_DQS4 C7 H9 FBA_DQS7 C7 H9
RV137 DQSU VDDQ_9 DQSU VDDQ_9
FBx_CMD15 CAS# CAS#
162_0402_1%
FBA_DQM6 E7 A9 FBA_DQM5 E7 A9 FBx_CMD16 CS1#
RANKA@ FBA_DQM4 D3 DML VSS_1 B3 FBA_DQM7 D3 DML VSS_1 B3
2

DMU VSS_2 E1 DMU VSS_2 E1

VSS_3 VSS_3 FBx_CMD17
FBA_CLK1# G8 G8
FBA_DQS#6 G3 VSS_4 J2 FBA_DQS#5 G3 VSS_4 J2
DQSL VSS_5 DQSL VSS_5 FBx_CMD18 ODT1
FBA_DQS#4 B7 J8 FBA_DQS#7 B7 J8
DQSU VSS_6 M1 DQSU VSS_6 M1
VSS_7 VSS_7 FBx_CMD19 CKE1
M9 M9
VSS_8 P1 VSS_8 P1
VSS_9 VSS_9 FBx_CMD20 A13 A13
FBA_RST# T2 P9 FBA_RST# T2 P9
20,21 FBA_RST# RESET VSS_10 RESET VSS_10
T1 T1 FBx_CMD21 A8 A8
L8 VSS_11 T9 L8 VSS_11 T9
FBA_CKE1 ZQ VSS_12 ZQ VSS_12
FBx_CMD22 A6 A6

1
J1 B1 RV141 J1 B1 FBx_CMD23 A11 A11
NC1 VSSQ_1 NC1 VSSQ_1
1

FBA_ODT1 L1 B9 243_0402_1% L1 B9
RV140 J9 NC2 VSSQ_2 D1 RANKA@ J9 NC2 VSSQ_2 D1
NC3 VSSQ_3 NC3 VSSQ_3 FBx_CMD24 A5 A5
243_0402_1% L9 D8 L9 D8

2
RANKA@ M7 NC4 VSSQ_4 E2 M7 NC4 VSSQ_4 E2
NC5 VSSQ_5 NC5 VSSQ_5 FBx_CMD25 A3 A3
1

E8 E8
2

RV138 RV139 VSSQ_6 F9 VSSQ_6 F9

VSSQ_7 VSSQ_7 FBx_CMD26 BA2 BA2
10K_0402_5% 10K_0402_5% G1 G1
RANKA@ RANKA@ VSSQ_8 G9 VSSQ_8 G9
VSSQ_9 VSSQ_9 FBx_CMD27 BA1 BA1
2

96-BALL 96-BALL FBx_CMD28 A12 A12

SDRAM DDR3 SDRAM DDR3
K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96 FBx_CMD29 A10 A10
B B
@ @
FBx_CMD30 RAS# RAS#
FBx_CMD31
FBx_CMD32
FBx_CMD33
FBx_CMD34 DBG0
FBx_CMD35 DBG1

+1.35VGS UV8 SIDE +1.35VGS +1.35VGS UV7 SIDE +1.35VGS

For RF For RF
1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M

1U_0603_25V6M
33P_0402_50V8J

33P_0402_50V8J
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV142

CV143

CV144

CV145

CV146

CV147

CV152

CV154

CV155

CV156

CV157

CV158

CV159

CV164
1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2

RANKA@ RANKA@ CD@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ RANKA@ CD@
RF_OPTNS@ RF_OPTNS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 DDR3 VRAM Rank0_H
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

+3VG_AON Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
D D
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE

2
RV146 RV147 RV148 RV149 RV150 STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
49.9K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
N15SGT@ @ @ @ @ STRAP1 +3VGS

1
STRAP2 +3VGS
17 STRAP0 STRAP0 Reserved(keep pull-up and pull-down footprint and not stuff by default)
17 STRAP1 STRAP1 STRAP3 +3VGS
17 STRAP2 STRAP2
17 STRAP3 STRAP3 STRAP4 +3VGS
17 STRAP4 STRAP4

DEVID_SEL
2

2
Pull-up to
RV151 RV152 RV153 RV154 RV155 Resistor Values Pull-down to Gnd
45.3K_0402_1% 4.99K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
+3VGS
0 (Default)
@ @ @ @ @ 4.99K 1000 0000
1

1
10K 1001 0001 1
15K 1010 0010
20K 1011 0011 PCIE_CFG
24.9K 1100 0100
0 (Default)
30.1K 1101 0101
34.8K 1110 0110 1
+3VGS 45.3K 1111 0111
C C

SMBUS_ALT_ADDR
N15x Binary Straps
0 0x9E (Default)
2

2 Physical
RV156 RV157 RV158 Power Rail Strap Mapping
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% Strapping pin
1 0x9C (Multi-GPU usage)
@ @ @ ROM_SCLK +3VGS SMB_ALT_ADDR
1

ROM_SI +3VGS SUB_VENDOR

ROM_SO +3VGS VGA_DEVICE
VGA_DEVICE
17 ROM_SI ROM_SI
17 ROM_SO ROM_SO STRAP0 +3VGS RAM_CFG[0] 0 3D Device (Class Code 302h)
17 ROM_SCLK ROM_SCLK
STRAP1 +3VGS RAM_CFG[1]
1 VGA Device (Default)
2

STRAP2 +3VGS RAM_CFG[2]

RV159 RV160 RV161
X76 20K_0402_1% 4.99K_0402_1% 4.99K_0402_1% STRAP3 +3VGS RAM_CFG[3]
@ N15SGT@ N15SGT@
STRAP4 +3VGS PCIE_MAX_SPEED
1

X76

GPU FB Memory (DDR3) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
B H5TC4G63AFR-11C 0x3 B
Hynix VRAM X76 VRAM P/N
900MHz 256M x 16 PD 20K
MT41J256M16HA-093G:E 0x4 X76409JVL01 SA00005SH10
Micron Samsung
900MHz 256M x 16 PD 24.9K
X76409JVL51 (1G 32Mx16)
K4W4G1646D-BC1A 0x5
Samsung
900MHz 256M x 16 PD 30.1K X76409JVL02 SA00005M100
N15S-GT PD 4.99K PD 4.99K PU 49.9K Un-stuff Un-stuff Un-stuff Un-stuff Micron
H5TC2G63FFR-11C 0x9
Hynix X76409JVL02 (2G 64Mx32)
900MHz 128M x 16 PU 10K
Hynix
Micron MT41J128M16JT-093G:K 0xA
900MHz
128M x 16 PU 15K
Samsung K4W2G1646Q-BC1A 0xB
900MHz
128M x 16 PU 20K

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 20140213 N15X_MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 23 of 45
5 4 3 2 1
 5 4 3 2 1

LCD
PWR
+3VS_LCDVCC +3VS
U9
2 1 1 5
R2 0_0603_5% VOUT VIN2

.1U_0402_10V6-K
C23

4.7U_0402_6.3V6M
C22
1 1 2
GND
3 4
2 2
EN
AP2821KTR-G1_SOT23-5
VIN1
Hot-Plug

PCH_LCD_VDDEN R183 1 2 0_0402_5% +3VS +3VS

4 PCH_LCD_VDDEN

B+

C21
.1U_0402_10V6-K
1
@

2
D D
2

2
@ R15
R351 R235 2 1M_0402_5%

5
0_0402_5% 100K_0402_5%

1
1

1
R237 2 1 LVDS_VDD_EN#
100K_0402_5% EDP_HPD_OUT 3 4

S
PCH_EDP_HPD 4

D
0.1U_0402_25V6
@
Q152B
1

1
D

1
C209
2 2N7002KDWH_SOT363-6
G Q17 R80

2
C25
.1U_0402_10V6-K

1 2N7002KW_SOT323-3 100K_0402_5% R184 1 2 0_0402_5%

@

S
3

2
2

B+ +LCD_VDD
L31 EDP_HPD
1@ 2
BLM15PX121SN1D_2P *EDP EN,EDP-HPD EN
2 EDP EN, EDP-HPD Disabled, 10K PU Via VCCIO
1

EDP Disabled, NC
C200
10U_0805_25V6K

C206
0.1U_0402_25V6

L38
1@ 2
2

BLM15PX121SN1D_2P 1

Q25
S

3 1
AO3401A_SOT23-3

Q17
G
2

换5800E
LVDS_VDD_EN#
Q25
换 AO3401A

BKLT CNTL +3VS

C
For LCD CONN YOGA3_11" C
2

R43 JLVDS ME@

1K_0402_5%
@ 1
C42 1 2 .1U_0402_10V6-K PCH_EDP_TX1-_C 2 1
4 PCH_EDP_TX1-
1

C43 1 2 .1U_0402_10V6-K PCH_EDP_TX1+_C 3 2

4 PCH_EDP_TX1+ 3
R185 1 2 0_0402_5% LCD_BKLT_CTRL 4
4 PCH_BKLT_CTRL 4
4 PCH_EDP_TX0- C38 1 2 .1U_0402_10V6-K PCH_EDP_TX0-_C 5
C39 1 2 .1U_0402_10V6-K PCH_EDP_TX0+_C 6 5
4 PCH_EDP_TX0+ 6 Touch
1

C28
.1U_0402_10V6-K
@

0529 1 7 +3VS 500mA(Max: 200mA) +3VALW_TOUCH

R24 C40 1 2 .1U_0402_10V6-K PCH_EDP_AUX+_C 8 7
Change R347 to R-Short 4 PCH_EDP_AUX+ 8
100K_0402_5% 4 PCH_EDP_AUX- C41 1 2 .1U_0402_10V6-K PCH_EDP_AUX-_C 9 +3VS 500mA(Max: 300mA) +3VS_TOUCH 0_0603_5% 2 @ 1 R25
10 9
2 10

C44
.1U_0402_10V6-K

C45
.1U_0402_10V6-K
CD@
+3VS_LCDVCC 11 2 1 1 1
2

12 11 R22 0_0603_5% CD@

12

C32
.1U_0402_10V6-K

C31
.1U_0402_10V6-K
CD@
40MIL EDP_HPD_OUT 13 1 1
LCD_BKLT_EN 14 13 CD@
LCD_BKLT_CTRL 15 14 2 2
16 15
16 2
Touch Panel Poer USB20 Port6 2
+LCD_VDD 17
18 17
19 18
2 1 D2 1 2 LCD_BKLT_EN 20 19
9,29 EC_LID_OUT# 20
R39 1K_0402_5% 21
22 21
@ RB751V-40_SOD323-2 +3VS_DMIC 22
DMIC_DATA 0_0402_5% 1 RA286 2 23
27 DMIC_DATA 23
@ DMIC_CLK 0_0402_5% 1 RA287 2 24
27 DMIC_CLK 24
25
26 25
MCU_I2C_RE_SDA 27 26
26 MCU_I2C_RE_SDA 27
MCU_I2C_RE_SCL 28
26 MCU_I2C_RE_SCL 28
+3VS 2 1 29
29
6

Q152A D R26 0_0603_5% 30

2 +3VS_CMOS 31 30 +3VALW_TOUCH
9 PCH_LCD_FPBACK G 9 USB20_P0 31 +3VALW
@ 1A 32
9 USB20_N0 32
2N7002KDWH_SOT363-6 33 Q2
S 34 33 LP2301ALT1G_SOT23-3 ID=2.8A
+3VS_TOUCH
1

35 34
9 USB20_N6 35

D
+3VALW_TOUCH 36 3 1
9 USB20_P6 36
37
EC_LID_OUT# 1 R227 2 0_0402_5% 38 37
38

C338
.1U_0402_10V6-K

C339
0.01U_0402_25V7K
39 41 @

G
1 1

2
40 39 GND1 42
LCD背背背背，LID背背控控PCH的的的背背的NC，直直直EC来来背背背背. 9,29 WIN8_BUTTON# 40 GND2
I-PEX_20374-040E-31 @
2 2

R909 1 2 0_0402_5%
B 29,32,37 EC_USB_ON# B

预预for win8 button wake up 1

C340
.1U_0402_10V6-K
2 1 LCD_BKLT_EN @
29 EC_BKLT_EN 2
R349 1K_0402_5%
1

2 @ 1
4,29 PCH_BKLT_EN
R54
100K_0402_5%

C29
.1U_0402_10V6-K

R350 1K_0402_5% 1
CD@
PCH_BKLT_EN 0415 update
2

2
USB20_N6

USB20_P6 +3VS_TOUCH

0801 reserve for touch panel

2

2
D8 D7
2

AZ5425-01F_DFN1006P2E2 AZ5425-01F_DFN1006P2E2 U55

2
AZ5123-01F.R7G_DFN1006P2X2
EMC_NS@ EMC_NS@ EMC_NS@
1

1
1

1
+3VALW_TOUCH

1
R169
10K_0402_5%
@

2
Camera WIN8_BUTTON#

+3VS +3VS_CMOS

2
A A

500mA(Max: 117mA) U57

2
DMIC AZ5725-01F_DFN1006P2X2 1

CG381
470P_0402_50V8-J
2 1 EMC_NS@
RG20 0_0603_5%
500mA(Max: 20mA) 2

1
CG16
.1U_0402_10V6-K

CG17
10U_0603_6.3V6M
@
1 1
+3VS +3VS_DMIC DMIC_DATA

1
DMIC_CLK
2 1
R5 0_0603_5% 2 2
2
2

CG3379 2 C1938 C1937

.1U_0402_10V6-K 47P_0402_50V8J 47P_0402_50V8J
CD@ @ @
1
1

CD@
1

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 LCD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 24 of 45
5 4 3 2 1
 5 4 3 2 1

TMDS CV255 1 2 .1U_0402_10V6-K HDMI_TX0+_C

DDC ESD
4 PCH_HDMI_TX0+
CV256 1 2 .1U_0402_10V6-K HDMI_TX0-_C +3VS +3VS 5V_HDMI_S0
4 PCH_HDMI_TX0-

4 PCH_HDMI_TX1+ CV257 1 2 .1U_0402_10V6-K HDMI_TX1+_C

4 PCH_HDMI_TX1- CV258 1 2 .1U_0402_10V6-K HDMI_TX1-_C

RP9 RP8
4 PCH_HDMI_TX2+ CV259 1 2 .1U_0402_10V6-K HDMI_TX2+_C 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% HDMI_CLK+_CON HDMI_TX1+_CON

3
4

3
4
HDMI_CLK-_CON HDMI_TX1-_CON
4 PCH_HDMI_TX2- CV260 1 2 .1U_0402_10V6-K HDMI_TX2-_C
D31 EMC_NS@ D32 EMC_NS@

2
CV262 1 2 .1U_0402_10V6-K HDMI_CLK+_C 1 1 10 9 1 1 10 9

G
4 PCH_HDMI_CLK+

2
1

2
1
4 PCH_HDMI_CLK- CV263 1 2 .1U_0402_10V6-K HDMI_CLK-_C 2 2 9 8 2 2 9 8

1 6 HDMI_DDC_CLK_CON 4 4 7 7 4 4 7 7

S
D 4 PCH_HDMI_DDC_CLK D

D
5 5 6 6 5 5 6 6
Q153A

5
G
2N7002KDWH_SOT363-6 3 3 3 3
1 2
R865 @ 0_0402_5% 8 8
L13 4 3 HDMI_DDC_DAT_CON

S
4 PCH_HDMI_DDC_DAT

D
HDMI_CLK+_C 1 2 HDMI_CLK+_CON
1 2 AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
Q153B HDMI_TX0+_CON HDMI_TX2+_CON
HDMI_CLK-_C 4 3 HDMI_CLK-_CON 2N7002KDWH_SOT363-6 HDMI_TX0-_CON HDMI_TX2-_CON
4 3
EMC@ HDMI2012F2SF-900T04_4P

1 2
H-PLUG +3VS

R866 @ 0_0402_5%

2
1 2
R867 @ 0_0402_5% R862
L12 1M_0402_5%
HDMI_TX0+_C 1 2 HDMI_TX0+_CON D34 EMC_NS@
1 2

2
HDMI_HPD_OUT 1 1 10 9 HDMI_HPD_OUT

G
1
HDMI_TX0-_C 4 3 HDMI_TX0-_CON HDMI_DDC_CLK_CON 2 2 9 8 HDMI_DDC_CLK_CON
4 3
EMC@ HDMI2012F2SF-900T04_4P 1 6 HDMI_HPD_OUT HDMI_DDC_DAT_CON 4 4 7 7 HDMI_DDC_DAT_CON

S
4 PCH_HDMI_HPD

2
1 2 5V_HDMI_S0 5 5 6 6 5V_HDMI_S0
R868 @ 0_0402_5% Q155A R885
2N7002KDWH_SOT363-6 20K_0402_5% 3 3
1 2
R869 @ 0_0402_5% 8

1
L14
HDMI_TX1+_C 1 2 HDMI_TX1+_CON
1 2 AZ1045-04F_DFN2510P10E-10-9

HDMI_TX1-_C 4 3 HDMI_TX1-_CON
4 3
C C
EMC@ HDMI2012F2SF-900T04_4P

1 2
CONN
R870 @ 0_0402_5% 5V_HDMI_S0

1 2
R871 @ 0_0402_5%
L15
HDMI_TX2+_C 1 2 HDMI_TX2+_CON
1 2
1A
F1
HDMI_TX2-_C 4 3 HDMI_TX2-_CON 1 3 Q5 1 2

S
4 3 +5VS
AO3401A_SOT23-3 1 CD@
EMC@ HDMI2012F2SF-900T04_4P 0.5A_8V_KMC3S050RY

C261
.1U_0402_10V6-K
G
2
1 2
33 SUSP 2
R872 @ 0_0402_5%

HDMI_CLK+_C R342 1 2470_0402_5%

HDMI_CLK-_C R344 1 2470_0402_5%

MINI HDMI
ME@
CONN
C263 2 1 .1U_0402_10V6-K JHDMI
HDMI_TX0+_C R381 1 2470_0402_5% 5V_HDMI_S0 19 17 HDMI_DDC_CLK_CON
+5V_POWER SCL 18 HDMI_DDC_DAT_CON
HDMI_TX0-_C R382 1 2470_0402_5% SDA
B B
HDMI_TX0+_CON 9
HDMI_TX1+_C R383 1 2470_0402_5% HDMI_TX0-_CON 11 TMDS_DATA0+ 15
HDMI_TX1+_CON 6 TMDS_DATA0- CEC 16
HDMI_TX1-_C R384 1 2470_0402_5% HDMI_TX1-_CON 8 TMDS_DATA1+ DDC/CEC_GROUND 1 HDMI_HPD_OUT
HDMI_TX2+_CON 3 TMDS_DATA1- HOT_PLUG_DETECT
HDMI_TX2+_C R385 1 2470_0402_5% HDMI_TX2-_CON 5 TMDS_DATA2+ 2
TMDS_DATA2- RESERVED#2
HDMI_TX2-_C R389 1 2470_0402_5% 10
7 TMDS_DATA0_SHIELD
4 TMDS_DATA1_SHIELD
TMDS_DATA2_SHIELD
3

D 20
5 Q155B 13 GND0 21
+3VS TMDS_CLOCK_SHIELD GND1
G 2N7002KDWH_SOT363-6 HDMI_CLK+_CON 12 22
HDMI_CLK-_CON 14 TMDS_CLOCK+ GND2 23
S TMDS_CLOCK- GND3
4

ACON_AHRW0-AK1200

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 25 of 45
5 4 3 2 1
 5 4 3 2 1

G-SENSOR
+3VS +3VS

+3VS +3VS
CG24 2 1.1U_0402_10V6-K
UG25
CD@ RPG1 1 12 EC_SMB_CLK3
2.2K_0404_4P2R_5% EC_SMB_DAT3 2 SDO SCx 11
SDx PS

3
4
10
5 CSB
UG16 6 INT1 9
1 8 3 INT2 GND 8
D VCCA VCCB 7 VDDIO GNDIO 4 D

2
1
EC_SMB_CLK3 2 7 MCU_I2C_RE_SCL VDD NC
29 EC_SMB_CLK3 A1 B1 MCU_I2C_RE_SCL 24
EC_SMB_DAT3 3 6 MCU_I2C_RE_SDA BMA222E_LGA12_2X2
29 EC_SMB_DAT3 A2 B2 MCU_I2C_RE_SDA 24
1 1

CG3380
.1U_0402_10V6-K
CD@

CG3381
.1U_0402_10V6-K
CD@
4 5 +3VS
GND OE

2
RG47 2 2 0416 update
NTSX2102GU8_XQFN8_1P2X1P4
100K_0402_5%

NEW symbol for Haydn 0604

1
+3VS
1
1

EC_SMB_CLK3 1 2 MCU_I2C_RE_SCL
RG911 RG910 R873 @ 0_0402_5%
2.2K_0402_5% 2.2K_0402_5% EC_SMB_DAT3 1 2 MCU_I2C_RE_SDA
R874 @ 0_0402_5%
2
2

EC_SMB_CLK3

EC_SMB_DAT3

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 MCU
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 26 of 45
5 4 3 2 1
 5 4 3 2 1

JIO HDA CARDREADER USB CONN +3VALW +3VS

+5VS +5VALW

2 2 2 2
C204 C194 C201 C202
D D
.1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K
@ @ @ @
1 1 1 1

+5VALW HRS_FH52E-40S-0P5SH

40
+5VS 39 40
38 39 42
37 38 GND2 41
+3VALW +3VS 36 37 GND1
35 36
34 35
33 34
DA1 33
7 PCH_HDA_RST# 32
3 1 2PCH_HDA_BCLK_RC 31 32
29 EC_BEEP 7 PCH_HDA_BCLK 31
1 1
CA323
2PC_BEEP_R
7
7
PCH_HDA_SYNC
PCH_HDA_SDIN0
RA28 0_0402_5% 30
29 30 RA28 Close to JIO
.1U_0402_10V6-K 28 29
7 PCH_HDA_SDOUT 28
9 PCH_BEEP 2 27 PCH_HDA_RST#
PC_BEEP_R 26 27
26
2

BAT54CW_SOT323-3 25 PCH_HDA_SYNC
29 EC_MUTE# 25
RA20 24
23 24 PCH_HDA_SDOUT
10K_0402_5% 24 DMIC_DATA 23

CA23 EMC_NS@

CA24 EMC_NS@
22 EMC@
24 DMIC_CLK 22
21 RA27 1 2 PCH_HDA_BCLK_RC
1

20 21 27_0402_5%
29 USB_CHG_EN 20

EMC_NS@
RA20 19 PCH_HDA_SDIN0
9 USB_OC1# 19
Add for Beep Noise on 5/21 18
18

CA25

CA26
17
9 USB20_N3 17

68P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

33P_0402_50V8J

33P_0402_50V8J
16
CARD READER 9 USB20_P3
15 16
15 1 1 1 1 1

EMC_NS@
CA22
14
9 USB20_N2 14
13
Left USB_CONN 9 USB20_P2 13

EMC@
12
11 12 2 2 2 2 2
9 USB30_TX_P1 11
10
9 USB30_TX_N1 10
C 9 C
8 9
9 USB30_RX_P1
7 8 For EMI
9 USB30_RX_N1 7
6
5 6
29 LID_SW# 5
4
29 LID_PAD# 4
29 CHG_MOD1 3
2 3
29 CHG_MOD2 2
29 CHG_MOD3 1
1
JIO ME@

NEW symbol for Haydn 0609

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 AUDIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 27 of 45
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 Cardreader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 28 of 45
5 4 3 2 1
 5 4 3 2 1

PWR

+3VALW_EC
+3VALW_EC +3VALW_EC_VCCA
RE16 1 2 0_0402_5% CPU_PROCHOT# 5,37
@ 43 VR_HOT#

+3VALW 2 1 2 1
RE1 0_0603_5% 1 1 1 1 1 1 1 RE22 0_0603_5% 1 1

1
CE15
1U_0402_10V6K

CE11
.1U_0402_10V6-K

CE10
.1U_0402_10V6-K

CE9
.1U_0402_10V6-K

CE8
.1U_0402_10V6-K

CE7
.1U_0402_10V6-K

CE6
.1U_0402_10V6-K

CE3
.1U_0402_10V6-K

CE4
1000P_0402_50V7K
D
EC_PROCHOT# 2 QE1
2 1 G 2N7002KW_SOT323-3
+3VL
RE5 0_0603_5% @2 2 2 2 2 2 2 2 2
S

3
2 1 +3VALW_EC
CD@ CD@ RE23 0_0603_5%
D D

EC_AGND EC_USB_ON# 2 1
RE704 10K_0402_5%

8386 +3VS +3VALW_EC +3VALW_EC_VCCA LID_PAD# 2

RE196 @
1
10K_0402_5%
2 1 CE1 VCOREVCC
.1U_0402_10V6-K 20MIL 20MIL 20MIL
WIN8_BUTTON# 2 @1 TS internal pull high

.1U_0402_10V6-K
VCCRTC FBE36 VCCRTC_EC 1 RE168 10K_0402_5%

CE13
BLM15PX121SN1D_2P EC_SMB_CLK1 4 1
1 2 EC_SMB_DAT1 3 2 Open Drain Signal
@ RPE680 SMB3 PU at MCP Side
RE188 1 2 0_0402_5% 2 2.2K_0404_4P2R_5%
CC1 @ 2 1 CPU_PECI EC_PWR_LED# 2 1
47P_0402_50V8J RE682 2.2K_0402_5%

114
121
127
UE1 EC_BATTCHG_LED# 4 1

12

11

26
50
92

74
3
VBAT EC_BATTLOW_LED# 3 2
for register keep RPE683

VCC
VBAT

VCORE

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)

AVCC
2.2K_0404_4P2R_5%
EC_USB20_N5 2 1
RE690 @ 1.5K_0402_5%
EC_USB20_P5 2 1
RE691 @ 1.5K_0402_5%
EMC@ 2 1 PCH_PCI_CLK EC_KBRST# 4 24 EC_PWR_LED#
9 EC_KBRST# KBRST#/GPB6 PWM0/GPA0 EC_PWR_LED# 30
RE254 33_0402_5% EC_INT_SERIRQ 5 25 EC_BATTCHG_LED# +3VS
9 EC_INT_SERIRQ SERIRQ/GPM6 PWM1/GPA1 EC_BATTCHG_LED# 30
2 7 LPC_FRAME# 6 28 EC_BATTLOW_LED#
LFRAME#/GPM5 PWM2/GPA2 EC_BATTLOW_LED# 30
7 29 EC_VOL_UP#
7 LPC_AD3 LAD3/GPM3 PWM3/GPA3 EC_VOL_UP# 31
CE339 8 PWM 30 EC_FAN_PWM1 EC_USB20_P5 2 1
7 LPC_AD2 LAD2/GPM2 PWM4/SMCLK5/GPA4 EC_FAN_PWM1 31
18P_0402_50V8J 9 31 EC_FAN_PWM RE708 1.5K_0402_5%
1 EMC@ 7 LPC_AD1 LAD1/GPM1 PWM5/SMDAT5/GPA5 EC_FAN_PWM 31
10 32
7 LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 EC_BEEP 27
8 PCH_PCI_CLK PCH_PCI_CLK 13 LPC 34 EC_SUS_VCCP
LPCCLK/GPM4 PWM7/RIG1#/GPA7 EC_SUS_VCCP 40
WRST# 14 120 EC_VOL_DOWN# EC_KBLED_PWREN 2 @ 1
WRST# TMRI0/GPC4 EC_VOL_DOWN# 31
15 124 EC_SUSP# RE693 10K_0402_5%
VCCST_PG_EC10 ECSMI#/GPD4 TMRI1/GPC6 EC_SUSP# 33,39,40,41
EC_RX 16 RPE3
30 EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
17 66 EC_TP_CLK 2 3
30 EC_TX LPCPD#/GPE6 ADC0/GPI0 VR_CPU_PWROK 10,43
+3VALW_EC 8,16,30 PCH_PLT_RST# RE217 1 2 0_0402_5% 22 67 EC_TP_DATA 1 4
LPCRST#/GPD2 ADC1/SMINT0/GPI1 NTC_V 37
EC_SCI# 23 68 BATT_TEMP
9 EC_SCI# ECSCI#/GPD3 ADC2/SMINT1/GPI2 BATT_TEMP 37
LID_PAD# 126 ADC 69 EC_VOL_UP# 2 10K_0404_4P2R_5%
1
C 27 LID_PAD# GA20/GPB5 ADC3/SMINT2/GPI3 VR_IMVP_IMON 43 C
70 RE18 1 2 0_0402_5% RE184 10K_0402_5%
IT8386E-192 CX ADC4/SMINT3/GPI4 EC_KBLED_PWREN 30
1
RE220
100K_0402_5%

71 RE13 1 2 0_0402_5% EC_VOL_DOWN# 2 1

ADC5/DCD1#/GPI5 VR_ADP_I 37
1

72 RE185 10K_0402_5%
CHG_MOD2 27
DE23
RB751V-40_SOD323-2 30 KSI0
58
KSI0/STB#
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73
USB_ID_N 37
DE24
@ 0_0402_5%
EC_MUTE# 2 @
RE179
1
10K_0402_5%
@ 59 78 RE216 1 2 0_0402_5% @ EC_ROTATION_LOCK#2 1
30 KSI1 EC_SUSWARN# 8
2

60 KSI1/AFD# DAC2/TACH0B/SMINT6/GPJ2 79 1 2 1 2 RE219 EC_ON RE187 10K_0402_5%

30 KSI2
2

61 KSI2/INIT# DAC3/TACH1B/SMINT7/GPJ3 80 EC_PROCHOT#

30 KSI3 KSI3/SLIN# DAC DAC4/DCD0#/GPJ4
WRST# 62 81 PCH_BKLT_EN 4,24 RPE225
WRST# 16 30 KSI4 KSI4 DAC5/RIG0#/GPJ5 SDM10U45LP-7_DFN1006-2-2
63 EC_FAN_PWM 1 4 @
30 KSI5 KSI5
1 64 85 EC_RTCRST_ON EC_FAN_PWM1 2 3
30 KSI6 KSI6 PS2CLK0/TMB0/CEC/GPF0
CE20
1U_0402_10V6K

65 86
30 KSI7 KSI7 PS2DAT0/TMB1/GPF1 EC_PBTN_OUT# 8
36 87 RE11 1 2 0_0402_5% 10K_0404_4P2R_5%
30 KSO0 KSO0/PD0 SMCLK0/GPF2 EC_SMB_CLK0 7,16,31
37 Int. K/B PS2 88 RE12 1 2 0_0402_5% GPU Thermal PCH EC_RX 2 @ 1
2 30 KSO1 KSO1/PD1 SMDAT0/GPF3 EC_SMB_DAT0 7,16,31
38 89 EC_TP_CLK RE207 10K_0402_5%
30 KSO2
39 KSO2/PD2 Matrix PS2CLK2/SMINT10/GPF4 90 EC_TP_DATA
EC_TP_CLK 31 Sensor
30 KSO3 KSO3/PD3 PS2DAT2/SMINT11/GPF5 EC_TP_DATA 31
40 RPE224
30 KSO4 KSO4/PD4
41 96 EC_FAN_SPEED1 1 4
30 KSO5 KSO5/PD5 GPH3/ID3/YM EC_CAPS_LED# 30
42 97 EC_FAN_SPEED 2 3
30 KSO6 KSO6/PD6 GPH4/ID4/YP USB_CHG_EN 27
+3VL +3VALW_EC 43 EXTERNAL SERIAL FLASH 98 EC_USB20_N5 RE214 1 2 0_0402_5%
USB20_N5
30 KSO7 KSO7/PD7 GPH5/ID5/DM USB20_N5 9
44 99 EC_USB20_P5 RE215 1 2 0_0402_5%
USB20_P5 10K_0404_4P2R_5%
30 KSO8 KSO8/ACK# GPH6/ID6/DP USB20_P5 9
45
30 KSO9 KSO9/BUSY
46 101 EC_SPI_CS0# RE204 1 2 MIRROR@ 0_0402_5% EC_SCI# 2 1
30 KSO10 KSO10/PE FSCE#/GPG3 PCH_SPI_CS0# 7
1

1
RE221
100K_0402_5%

RE223
100K_0402_5%
MIRROR@

51 102 EC_SPI_SI RE205 1 2 MIRROR@ 0_0402_5% RE206 10K_0402_5%

30 KSO11 KSO11/ERR# FMOSI/GPG4 PCH_SPI_SI 7
@ 52 SPI Flash ROM 103 EC_SPI_SO RE208 1 2 MIRROR@ 0_0402_5% PCH_SPI_SO 7 RPE200
30 KSO12 KSO12/SLCT FMISO/GPG5
53 105 EC_SPI_CLK RE212 1 2 MIRROR@ 0_0402_5% EC_INT_SERIRQ 1 4
30 KSO13 KSO13 FSCK/GPG7 PCH_SPI_CLK 7
54 EC_KBRST# 2 3
30 KSO14 KSO14
55
30 KSO15
2

56 KSO15 108 EC_ACIN# 10K_0404_4P2R_5%

31 EC_ROTATION_LOCK# KSO16/SMOSI/GPC3 AC_IN#/GPB0
57 UART 109 LID_SW# LID_SW# 27
9,24 EC_LID_OUT# KSO17/SMISO/GPC5 LID_SW#/GPB1
GPG2

31
EC_ONOFF_BTN# EC_ONOFF_BTN# 110 82 EC_SYS_PWROK EC_SYS_PWROK 8
111 PWRSW#/GPB3 EGAD/GPE1 83 CHG_MOD3
38 EC_ON XLP_OUT/GPB4 SM Bus EGCS#/GPE2 CHG_MOD3 27
1
RE222
100K_0402_5%
UNMIRROR@

BATT charger EC_SMB_CLK1 115 84 DCIN_USB_EN

EC_SMB_CLK1 37 SMCLK1/GPC1 EGCLK/GPE3 DCIN_USB_EN 37
EC_SMB_DAT1 116 @
EC_SMB_DAT1 37 SMDAT1/GPC2
1 2 CPU_PECI 117 GPIO EC_ON_5V 2 1
5 CPU_PECI_R SMCLK2/PECI/GPF6
RC12 43_0402_5% 118 77 RE10 10K_0402_5%
8,10 EC_PCH_PWROK SMDAT2/PECIRQT#/GPF7 SMINT5/GPJ1 VGA_AC_DET 16
94 100 GPG2
26 EC_SMB_CLK3
2

95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE0#/GPG2 106 EC_RSMRST#_R 2 1

B
Sensor 26 EC_SMB_DAT3 CTX1/SOUT1/GPH2/SMDAT3/ID2 SSCE1#/GPG0 EC_PCH_ACIN 8 B
104 RE7 10K_0402_5%
DSR0#/GPG6 PCH_ME_PROTECT 7
20MIL 107 EC_SYSON EC_SYS_PWROK 2 1
DTR1#/SBUSY/GPG1/ID7 EC_SYSON 33,39
+3VL RE202 1 2 0_0402_5% 119 RE181 10K_0402_5%
CRX0/GPC0 EC_BKLT_EN 24
GPG2 112 123 EC_ON_5V EC_SYSON 2 1
VSTBY0 CTX0/TMA0/GPB2 EC_ON_5V 38
*H MIRROR CODE EN EC_MUTE# 125 WAKE UP 18 RE3 10K_0402_5%
27 EC_MUTE# GPE4 RI1#/GPD0 PCH_SLP_S3# 8
L MIRROR CODE DISABLE 21
RI2#/GPD1 PCH_SLP_S4# 8
76 EC_NOVO_BTN#_R RPE2
TACH2/SMINT4/GPJ0 48 EC_FAN_SPEED1 EC_SUSP# 1 4
24,32,37 EC_USB_ON# TACH1A/TMA1/GPD7 EC_FAN_SPEED1 31
EC_USB_ON# 33 47 EC_FAN_SPEED EC_PCH_PWROK 2 3
EC_X1 PCH_PWREN# 35 GINT/CTS0#/GPD5 TACH0A/GPD6 19 WIN8_BUTTON# EC_FAN_SPEED 31
33 PCH_PWREN# RTS1#/GPE5 GPIO L80HLAT/BAO/SMCLK4/GPE0 WIN8_BUTTON# 9,24
RE218 1 2 EC_RSMRST#_R 93 20 CHG_MOD1 10K_0404_4P2R_5%
8 EC_RSMRST# CLKRUN#/GPH0/ID0 L80LLAT/SMDAT4/GPE7 CHG_MOD1 27
2 1 EC_X2
RE8 10M_0402_5% 100_0402_5%
1

EC_X1 2
RE707 EC_X2 128 CK32KE/GPJ7
CK32K/GPJ6 Clock
470K_0402_5% EC_SUS_VCCP 2 1
RE14 10K_0402_5%
1

YE1
2

EC_X1_R 1 2 RE182
10K_0402_5%
AVSS

32.768KHZ_12.5PF_200458-PG14 @
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

2 2
2

CE21 CE22
18P_0402_50V8J 18P_0402_50V8J
1

27
49
91
113
122

75

1 1 BATT_TEMP 1 2
CE17 100P_0402_50V8J
EMC_NS@
IT8386E-192-CX_LQFP128_14X14
CRYSTAL
1,Space 15MIL
2,No trace under crystal EC_AGND

EC DSW Signal RTC_RST# 7

+3VALW_EC +3VL +3VALW_EC

1
QE3 D
+3VL +3VALW_EC EC_RTCRST_ON 2
2

2
G
+3VL +3VALW_EC RE31 @ RE32
2

1
RE586
10K_0402_5%

RE587
10K_0402_5%

0_0402_5% 0_0402_5% 2N7002KW_SOT323-3 S

3
A @ RE50 A
1

KSI7 @1 TP131 TP136 1@ 100K_0402_5%

1

KSI6 @1 TP132 TP137 1@ @ RE183 EC_ONOFF_BTN# 2 1

WRST# @1 TP133 TP138 1@ RE197 100K_0402_5% RE186 10K_0402_5%
1

2
EC_ACIN# EC_SMB_CLK1 @1 TP134 100K_0402_5% LID_SW# 2 @ 1
8 EC_ACIN#
EC_SMB_DAT1 @1 TP135 DE40 RE189 10K_0402_5%
2

2 EC_NOVO_BTN#_R
QE15 0604
1

D 2N7002KW_SOT323-3 1
31 EC_NOVO_BTN#
2 2 1 VR_ACIN 37 For off-line programming烧烧EC code
G RE203 3 EC_ONOFF_BTN#
1K_0402_5% KSI-6 (pin-H13 --> I2C_DATA) 1 Security Classification LC Future Center Secret Data Title
CE5
.1U_0402_10V6-K

S KSI-7 (pin-G9 --> I2C_CLK)

3

BAT54CW_SOT323-3
SMDAT0/GPF3(pin-B10) Issued Date 2014/01/11 Deciphered Date 2013/11/08 ECT8386
SMCLK0/GPF2(pin-A10) 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 29 of 45
5 4 3 2 1
 5 4 3 2 1

WIFI&BT Board Connector

+3VS_WLAN

Mini Card(WLAN/WiMAX)

C79
.1U_0402_10V6-K
1

Need short
+3VS_WLAN JWLAN ME@ 2
J2 @
+3VS 1 2 1 2
1 2 R113 1 2 0_0402_5% USB20_P4_R 3 GND1 3.3VAUX1 4
9 USB20_P4 USB_D+ 3.3VAUX2
JUMP_43X79 9 USB20_N4 R114 1 2 0_0402_5% USB20_N4_R 5 6 @ 1 TP52
7 USB_D- LED#1 8
9 GND2 PCM_CLK 10
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0
SDIO_DAT1
PCM_OUT
LED#2
16 @ 1 TP61 KB BL

22U_0603_6.3V6-M
17 18
SDIO_DAT2 GND11

C78
1 1 19 20
D C53 21 SDIO_DAT3 UART_WAKE 22 D
.1U_0402_10V6-K 23 SDIO_WAKE UART_RX
SDIO_RESET
2 2
+5VS +5VS_LED
KEY E Q24
25 PIN24~PIN31 NC PIN 24 LP2301ALT1G_SOT23-3
27 26 +5VS

D
29 28 3 1
31 30

C205 CD@
.1U_0402_10V6-K
33 32 ID=2.8A

G
2
GND3 UART_TX

2
35 34 1
9 PCIE_PTX_C_DRX_P3 PETP0 UART_CTS
37 36 R254
9 PCIE_PTX_C_DRX_N3 PETN0 UART_RTS
39 38 EC_TX_RSVD R65 1 @ 2 0_0402_5% EC_TX_R 10K_0402_5%
41 GND4 CLink_RESET 40 EC_RX_RSVD R66 1 @ 2 0_0402_5% BT_CTRL#
9 PCIE_PRX_DTX_P3 PERP0 CLink_DATA 2
43 42
9 PCIE_PRX_DTX_N3

1
45 PERN0 CLink_CLK 44 R109 1 2 0_0402_5%
47 GND5 COEX3 46
8 CLK_PCIE_WLAN REFCLKP0 COEX2

1
49 48 D
8 CLK_PCIE_WLAN# REFCLKN0 COEX1

C213
.1U_0402_10V6-K
R126 51 50 R125 1 2 0_0402_5% 2
GND6 SUSCLK SUSCLK 8 29 EC_KBLED_PWREN G
8 WLAN_CLKREQ# WLAN_CLKREQ# 1 2 0_0402_5% WLAN_CLKREQ#_R 53 52 1 2 1
CLKEQ0# PERSTO# PCH_PLT_RST# 8,16,29

2
8 PCIE_WAKE# R120 1 @ 2 0_0402_5% WLAN_PCIE_WAKE# 55 54 BT_CTRL# R121 0_0402_5%
57 PEWAKE0# RSRVD/W_DISABLE#2 56 WL_OFF# R261 Q20 S @

3
GND7 W_DISABLE#1 100K_0402_5% 2N7002KW_SOT323-3
2
59 58 @ 1 TP68

1
61 RSRVD/PETP1 I2C_DATA 60 @ 1 TP82
63 RSRVD/PETN1 I2C_CLK 62 @ 1 TP111
65 GND8 NFC_I2C_IRQ(MGPIO5) 64 EC_TX_R
67 RSRVD/PERP1 NFC_Reset#(MGPIO7) 66
69 RERVD/PERN1 RSRVD7 68 +3VS_WLAN
71 GND9 RSRVD8 70
73 RSRVD1 RSRVD12 72
75 RSRVD2 3.3VAUX3 74
GND10 3.3VAUX4

C203 CD@
.1U_0402_10V6-K
77 76 1
GND15 GND14

+3VS_WLAN
DEREN_40-42313-06742RHFL 2 +5VS_LED

JKBBL ME@

2
1 5
RC2525 2 1 GND1
10K_0402_5%
NEW symbol for Haydn 0609 3 2
@ 4 3 6
4 GND2

1
C WLAN_PCIE_WAKE# ACES_51524-0040N-001 C

NEW symbol for Haydn 0530

BT_CTRL# R105 1 2 1K_0402_5% EC_TX_R R187 1 2 100_0402_1% EC_TX

PCH_BT_OFF# 9
WL_OFF# 1 2 DEBUG@
PCH_WLAN_OFF# 9
R110 0_0402_5% BT_CTRL# R188 1 2 100_0402_1% EC_RX
WLAN&BT Combo module circuits DEBUG@
BT on module BT on module

1
Enable Disable R191
100K_0402_5%
DEBUG@
* BT_CRTL H L

2
PCH_BT_ON# L H

Keyboard Connector
2

D4007
2

AZ5123-01F.R7G_DFN1006P2X2
ACES_50519-02601-001
EMC_NS@ UART Debug Connector
28 26 KSI1
G2 26 KSI1 29
1

27 25 KSI7
G1 25 KSI7 29
24 KSI6
KSI6 29
1

LED300 R3000 24 23 KSO9

23 KSO9 29 +3VS
EC_PWR_LED# 1 2 1 2 +3VALW 22 KSI4 JDB2 ME@
29 EC_PWR_LED# 22 KSI4 29
2 21 KSI5 1 5
21 KSI5 29 1 GND1
100_0402_5% 20 KSO0 2
KSO0 29 29 EC_TX
3

C1942 12-21C-T3D-CP1Q2B12Y-2C_WHITE 20 19 KSI2 3 2

19 KSI2 29 29 EC_RX 3
220P_0402_50V7K 18 KSI3 4 6
18 KSI3 29 4 GND2

2
1 17 KSO5
17 KSO5 29
16 KSO1 R259
16 KSO1 29
15 KSI0 100K_0402_5% ACES_50208-00408-001
B 15 KSI0 29 B
14 KSO2 @
14 KSO2 29
13 KSO4
LED301 KSO4 29

1
13 12 KSO7
12 KSO7 29
11 KSO8
11 KSO8 29
EC_BATTLOW_LED# 3 10 KSO6
29 EC_BATTLOW_LED# R3001 10 KSO6 29
9 KSO3
9 KSO3 29
1 1 2 +3VALW 8 KSO12
8 KSO12 29
7 KSO13
7 KSO13 29
EC_BATTCHG_LED# 2 6 KSO14
29 EC_BATTCHG_LED# 150_0402_5% 6 KSO14 29
2

5 KSO11
5 KSO11 29
D4008 4 KSO10
2

4 KSO10 29
12-22-S2ST3D-C30-2C_WHI-ORG AZ5123-01F.R7G_DFN1006P2X2 3 KSO15
3 KSO15 29
2 2 2 +3VALW_CAPLED R101 1 2 100_0402_5%
2 +3VS
EMC_NS@ 1 R102 1 @ 2 100_0402_5%
1 +3VALW
C1943 C1948
EC_CAPS_LED# 29
1

220P_0402_50V7K
220P_0402_50V7K JKB ME@
1 1
1

2
D13
D4006
2

2
AZ5725-01F_DFN1006P2X2

AZ5123-01F.R7G_DFN1006P2X2

EMC@ EMC_NS@
1

1
1

EC_PWR_LED#

EC_BATTCHG_LED# +3VALW_CAPLED C117 1 2 EMC_NS@ 100P_0402_50V8J EC_CAPS_LED# C133 1 2 EMC_NS@ 100P_0402_50V8J

EC_BATTLOW_LED# KSO2 C89 1 2 EMC_NS@ 100P_0402_50V8J KSO1 C90 1 2 EMC_NS@ 100P_0402_50V8J

KSO15 C92 1 2 EMC_NS@ 100P_0402_50V8J KSO7 C93 1 2 EMC_NS@ 100P_0402_50V8J

KSO6 C94 1 2 EMC_NS@ 100P_0402_50V8J KSI2 C95 1 2 EMC_NS@ 100P_0402_50V8J

EMC_NS@ EMC_NS@ EMC_NS@
KSO8 C96 1 2 EMC_NS@ 100P_0402_50V8J KSO5 C97 1 2 EMC_NS@ 100P_0402_50V8J
2

D4 D5 D6
KSO13 C98 1 2 EMC_NS@ 100P_0402_50V8J KSI3 C99 1 2 EMC_NS@ 100P_0402_50V8J
2

2
AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

KSO12 C100 1 2 EMC_NS@ 100P_0402_50V8J KSO14 C109 1 2 EMC_NS@ 100P_0402_50V8J

KSO11 C119 1 2 EMC_NS@ 100P_0402_50V8J KSI7 C110 1 2 EMC_NS@ 100P_0402_50V8J

1

A KSO10 C107 1 2 EMC_NS@ 100P_0402_50V8J KSI6 C122 1 2 EMC_NS@ 100P_0402_50V8J A

1

KSO3 C116 1 2 EMC_NS@ 100P_0402_50V8J KSI5 C108 1 2 EMC_NS@ 100P_0402_50V8J

KSO4 C115 1 2 EMC_NS@ 100P_0402_50V8J KSI4 C123 1 2 EMC_NS@ 100P_0402_50V8J

KSI0 C121 1 2 EMC_NS@ 100P_0402_50V8J KSO9 C111 1 2 EMC_NS@ 100P_0402_50V8J

KSO0 C124 1 2 EMC_NS@ 100P_0402_50V8J KSI1 C120 1 2 EMC_NS@ 100P_0402_50V8J

Reserve
For EMC

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 CONN(WLAN&KB&PWRB&UART)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 30 of 45
5 4 3 2 1
 5 4 3 2 1

THERMAL SENSOR AND FAN

NOVO button
Rotation button SW4003
SW4000 29 EC_NOVO_BTN# EC_NOVO_BTN# 1 4
EC_ROTATION_LOCK# 1 4 1 4
29 EC_ROTATION_LOCK# 1 4

TESTPAD 1 2 3
TP43 2 3
TESTPAD 1 2 3
TP41 2 3
EVQP7L01K_4P
+5VS EVQP7L01K_4P C1940 1 2 220P_0402_50V7K
C1934 1 2 220P_0402_50V7K
JFANC ME@ D4004
1A 1 5 D4000 1 2
2 1 2 1 GND1 1 2 1 2
3 2 1 2
D 1 1 R223 0_0603_5%
3
EMC_NS@
D
4 6 EMC_NS@
C986 C175 4 GND2 ON/OFF button AZ5725-01F_DFN1006P2X2

2
10U_0603_6.3V6M
2
.1U_0402_10V6-K Vol up/down button AZ5725-01F_DFN1006P2X2
SW4004
@ ACES_50208-00408-001 SW4001 EC_ONOFF_BTN# 1 4
29 EC_ONOFF_BTN# 1 4
EC_VOL_UP# 1 4
29 EC_VOL_UP# 1 4
0530 New symbol
29 EC_FAN_SPEED 0530 New symbol
29 EC_FAN_PWM TESTPAD TP39 1 2 3
1 2 3 2 3
TESTPAD TP37 2 3
EVQP7L01K_4P
EVQP7L01K_4P C1939 1 2 220P_0402_50V7K
C1935 1 2 220P_0402_50V7K
D4003
D4001 1 2
1 2 1 2
1 2 EMC_NS@
EMC_NS@ AZ5725-01F_DFN1006P2X2
Vol up/down button AZ5725-01F_DFN1006P2X2
+5VS SW4002
29 EC_VOL_DOWN# EC_VOL_DOWN# 1 4
JFANS ME@ 1 4
1A 1 5 0530 New symbol
2 1 2 1 GND1
3 2 1 2 3
1 1 R224 0_0603_5%
3 TESTPAD TP38 2 3
4 6
C987 C176 4 GND2
10U_0603_6.3V6M .1U_0402_10V6-K EVQP7L01K_4P
2 2 @ ACES_50208-00408-001 C1936 1 2 220P_0402_50V7K

29 EC_FAN_SPEED1 D4002
29 EC_FAN_PWM1 1 2
1 2
EMC_NS@
AZ5725-01F_DFN1006P2X2
C C

Touch Pad Connector

+3VS
+3VS_TP

Nuvoton thermal sensor

2
+3VS
R222
Address 1001_100xb 0_0402_5% PM_SMB_CLK
PM_SMB_DAT
10mA U35 EMC_NS@ EMC_NS@ EMC_NS@

1
1 8 EC_SMB_CLK0 ACES_50505-00641-001 D3 D11 D12
VDD SCL EC_SMB_CLK0 7,16,29

2
+3VS_TP 6 8
5 6 G2 7
C1933
1U_0402_10V6K

C179
.1U_0402_10V6-K

C181
.1U_0402_10V6-K

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2

AZ5725-01F_DFN1006P2X2
1 1 REMOTE+_R 2 7 EC_SMB_DAT0 1 1

2
D+ SDA EC_SMB_DAT0 7,16,29 29 EC_TP_CLK
4 5 G1
C1020
4.7U_0402_6.3V6M
29 EC_TP_DATA
REMOTE-_R 3 6 THM_ALERT# 3 4
D- ALERT# PM_SMB_CLK 2 3
7,14 PM_SMB_CLK
@2 2 THM_SHDN# 4 5 2 2 PM_SMB_DAT 1 2
T_CRIT# GND 7,14 PM_SMB_DAT 1

1
NCT7718W_MSOP8 ME@

1
JTP

B B

+3VS

THM_ALERT# R625 1 2 10K_0402_5%

@

THM_SHDN# R624 1 2 10K_0402_5%

@

Close to memory side Close to GPU&VRAM

REMOTE1+ REMOTE2+
1 1
1

C C
C982 2 Q137 C983 2 Q138
100P_0402_50V8J B MMST3904-7-F_SOT323-3 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 @ E 2 @ E
3

REMOTE1- REMOTE2-

UMA@ OPT@

REMOTE1+/-:
Trace width/space:10/10 mil
Trace length:<8"

UMA@
Close U35 REMOTE1+ R176 1 2 0_0402_5%
A A
REMOTE+_R REMOTE2+ R175 1 OPT@ 2 0_0402_5% REMOTE+_R
1
REMOTE2- R178 1 OPT@ 2 0_0402_5% REMOTE-_R
C451
2200P_0402_50V7K REMOTE1- R177 1 2 0_0402_5%
2 REMOTE-_R
UMA@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 CONN(THM&FAN&RTN&SPKR&TP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 31 of 45
5 4 3 2 1
 5 4 3 2 1

USB30 USB30_TX_N2_CON
L68 USB30_TX_P2_CON
USB20_N1 1 2 USB20_N1_CON USB20_N1_CON
1 2 D33 EMC_NS@
R876,R877 COLAY WITH L68 USB20_P1_CON 1 1 10 9
USB20_P1 4 3 USB20_P1_CON U8
EMC@ 4 3 2 2 9 8

2
CMM21T-900M-N_4P
D9 D10 4 4 7 7 1 8 2.5A

2
GND VOUT3 +5V_USB30
AZ5425-01F_DFN1006P2E2 AZ5425-01F_DFN1006P2E2
EMC_NS@ 5 5 6 6 +5VALW 2 7 C15 1 2 100U_1206_6.3V6M
EMC_NS@ VIN1 VOUT2
EMC@ 3 3 C184 2 1 3 6 C187 1 2 .1U_0402_10V6-K
EXC24CH900U_4P VIN2 VOUT1

1
.1U_0402_10V6-K
USB30_TX_R_N2 4 3 USB30_TX_N2_CON 8 EC_USB_ON# 4 5
24,29,37 EC_USB_ON# USB_OC0# 9

1
D 4 3 EN/EN FLAG D

R880,R881 COLAY WITH L69

USB30_TX_R_P2 1 2 USB30_TX_P2_CON AZ1045-04F_DFN2510P10E-10-9 AP2820CMMTR-G1_MSOP8
1 2 USB30_RX_N2_CON
L69 USB30_RX_P2_CON

EMC@ Low Active 2A

EXC24CH900U_4P
USB30_RX_N2 4 3 USB30_RX_N2_CON Left USB3.0/2.0
4 3
R878,R879 COLAY WITH L70
USB30_RX_P2 1 2 USB30_RX_P2_CON
1 2 +5V_USB30
L70
JUSB30 ME@

2
C185 1 2USB30_TX_R_P2 R880 1 @ 2 0_0402_5% USB30_TX_P2_CON 9
9 USB30_TX_P2 SSTX+
.1U_0402_10V6-K 1 D4005

2
+5V_USB30 VBUS
C186 1 2USB30_TX_R_N2 R881 1 @ 2 0_0402_5% USB30_TX_N2_CON 8 10 AZ5725-01F_DFN1006P2X2
9 USB30_TX_N2 SSTX- GND_PAD1
.1U_0402_10V6-K USB20_N1 R876 1 2 0_0402_5% USB20_N1_CON 2 11 EMC_NS@
9 USB20_N1 D- GND_PAD2
@ 4 12
USB20_P1 R877 1 @ 2 0_0402_5% USB20_P1_CON 3 GND GND_PAD3 13
9 USB20_P1 D+ GND_PAD4

1
USB30_RX_P2 R878 1 2 0_0402_5% USB30_RX_P2_CON 6
9 USB30_RX_P2 SSRX+
@ 7

1
USB30_RX_N2 R879 1 2 0_0402_5% USB30_RX_N2_CON 5 GND_D
9 USB30_RX_N2 SSRX-
@

DEREN_40-42039-00901RHF-L
NEW symbol for Haydn 0604

C C

MSATA (Full Card) JSATA ME@

1
0.01U_0402_25V7K 1 2 C1946 SATA_PTX_C_DRX_P1 2 1
7 SATA_PTX_DRX_P1 2
0.01U_0402_25V7K 1 2 C1945 SATA_PTX_C_DRX_N1 3 11
7 SATA_PTX_DRX_N1 3 GND1
4
0.01U_0402_25V7K 1 2 C1947 SATA_PRX_C_DTX_N1 5 4
7 SATA_PRX_DTX_N1 5
0.01U_0402_25V7K 1 2 C1949 SATA_PRX_C_DTX_P1 6
7 SATA_PRX_DTX_P1 6
7 12
8 7 GND2
+5VS_MSATA 2A 8
9
10 9
10

ELCO_006809610010846

New Symbol
B B

R891
2A
1 2
+5VS +5VS_MSATA
0_0603_5%
C1955
22U_0603_6.3V6-M

1 1 1
C1956
4.7U_0402_6.3V6M
@

C1950
.1U_0402_10V6-K
2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 CONN(MSATA&USB30&USB20)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 32 of 45
5 4 3 2 1
 5 4 3 2 1

+1.35V +1.35V_CPU
+5VALW +5VALW +5VLP
PJ13 Enable:
VIH=1.2V~5.5V
1 VIL=0~0.4V

1
PJ_43x79_6
C112 +5VS R231 R234
1 1U_0402_10V6K U56 100K_0402_5% 100K_0402_5%
@ 2 1 14 1 @
C214 2 VIN1_1 VOUT1_2 13 C216

2
.1U_0402_10V6-K VIN1_2 VOUT1_1 .1U_0402_10V6-K
2 1 2 @ EC_SUSP# R264 1 2 0_0402_5% 3 12 5VS_CT1 SUSP
EN1 SS1 2 SUSP 25
R16 0_0603_5%
@ 4 11
D BIAS GND D

1
R265 1 2 0_0402_5% 5 10 3VS_CT2 +3VS D
+3VALW EN2 SS2 Q16 2 EC_SUSP#
EC_SUSP# 29,39,40,41

0.01U_0402_25V7K
C114 @
1 6 9 1 2N7002KW_SOT323-3 G
7 VIN2_1 VOUT2_2 8 C215
+5VALW VIN2_2 VOUT2_1 .1U_0402_10V6-K S
1

3
15
2 C113 GPAD 2
1U_0402_10V6K APL3523AQBI-TRG_TDFN14_2X3
+3VS +5VS 2

1 1 0522 new symbol for haydn .

EMC_NS@ C217 EMC_NS@ C218
.1U_0402_10V6-K .1U_0402_10V6-K +5VALW +5VLP
2 2 C226
1 2 5VS_CT1 3VS_CT2

1000P_0402_50V7K

1000P_0402_50V7K

1
.1U_0402_10V6-K 1 1

C101

C102

@
R230 @ R236
EMC_NS@ 100K_0402_5% 100K_0402_5%
REV@
2 2

2
SYSON#

+1.05VS +3VALW

1
D
Q19 2
G EC_SYSON 29,39
2N7002KW_SOT323-3
REV@
1 S

3
1 1
EMC_NS@ C220
EMC_NS@ C224 EMC_NS@ C225 .1U_0402_10V6-K
.1U_0402_10V6-K .1U_0402_10V6-K 2
C
2 2 C

For CLK signal cross moat concern.

+3VALW +3VALW_PCH

2 1
R13 0_0603_5%
@

1
Q23 C219
LP2301ALT1G_SOT23-3 .1U_0402_10V6-K
2

D
3 1

.1U_0402_10V6-K
C37

C30 @
0.01U_0402_25V7K
G
1 1

2
2 2

PCH_PWREN# 2 1
29 PCH_PWREN#
R11
10K_0402_5% 1
B B

C441
.1U_0402_10V6-K
1
R238
2
470K_0402_5%

+1.35V +3VALW_PCH
+5VS +3VS +1.05VS +0.68VS

2
2

@ R246 @ R258
@ R257 @ R245 @ R247 @ R248 22_0402_5% 22_0402_5%
22_0402_5% 22_0402_5% 22_0402_5% 22_0402_5%

1
1

SUSP 1 2 3
R118 0_0402_5% QC11B
REV@

6
D PCH_PWREN# 1 2 5 @
6

D D D Q148 D SYSON# 1 2 2 Q147A R119 0_0402_5%

2 Q146A 5 Q146B 5 Q147B 2 R117 0_0402_5% G 2N7002KDWH_SOT363-6 @
G 2N7002KDWH_SOT363-6 G 2N7002KDWH_SOT363-6 G 2N7002KDWH_SOT363-6 G AO5804EL_SC89-6
REV@ 4
S

1
S S S S 2N7002KW_SOT323-3
1

A REV@ A
REV@ REV@ REV@ REV@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 POWER SWITCH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 33 of 45
5 4 3 2 1
 5 4 3 2 1

FD1 FD2 FD3 FD4 FD5 FD6

D 0801 DFB需需需需 D
1

1
PAD_CT6P0B7P0D3P6 PAD_CT6P0
H1 H12 H14 H15 H16 H2 H4 H5
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_CT6P0B7P0D3P6 PAD_CT6P0B7P0D3P6 PAD_CT6P0B7P0D3P6 PAD_CT6P0B7P0D3P6 PAD_CT6P0B7P0D3P6 PAD_CT6P0 PAD_CT6P0 PAD_CT6P0

PAD_C7P0D4P3 PAD_RT4P0X2P0 PAD_C7P0D5P6

H18 H19
H3 H6 H10 HOLEA HOLEA H11
HOLEA HOLEA HOLEA HOLEA

1
1

1
PAD_C7P0D4P3 PAD_C7P0D4P3 PAD_C7P0D4P3 PAD_C7P0D5P6
PAD_RT4P0X2P0 PAD_RT4P0X2P0

PAD_C7P0D2P3
H7 H9 H13 H17
C HOLEA HOLEA HOLEA HOLEA C
1

PAD_C7P0D2P3 PAD_C7P0D2P3 PAD_C7P0D2P3 PAD_C7P0D2P3

PAD_ShapeT6P0X5P5 PAD_O2P7X2P2D2P7X2P2N
PAD_C2P2D2P2N
H20 H21
HOLEA HOLEA H22
HOLEA
1

PAD_ShapeT6P0X5P5 PAD_O2P7X2P2D2P7X2P2N
PAD_C2P2D2P2N

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 Screw and Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Haydn
Date: Monday, November 17, 2014 Sheet 34 of 45
5 4 3 2 1
 5 4 3 2 1

SIT
4/16: 5/29:
1.EDP connector change to 40 pin , touch connector change to 10pin . 1.Reserve RV39 ,RV171 follow NVIDIA suggestion.
2.G sensor change to BMA222E 2.Modify JIO pin define ,add USB charger mode control signal .
3.Modify DIMM connector pin define 9/23:
1.Change JLVDS to I-PEX_20374-040E-31 follow ME suggestion.
2.Change some power plane from +3VALW to +3VALW_PCH.
0603: 3.Mount D13 follow emc suggestion.
4/24: 1.Change JFANC ,JFANS to ACES_50208-00408-001 follow ME connector list .
1.CV112 change to 0.1uF follow DG. 2.Delete PCIE_WAKE#,PCH_ACIN...reserved pull up signal +3VL for layout concern.
3.Delete QV13 ,Change QV12,QV19 to 2N7002KDWH_SOT363-6 for layout concern.
9/24:
1.Reserve CC31 and CC32 For EMC.
4/28: 0604:
1.unstuff pull up pull down resistor for GPU CMD signal (Single rank no need) 1.Change JUSB30 to C-K_26211-8B19-02 follow ME connector list .
2. Reserve pull down resistor for signal OVERT# 2.Change UG16 to NTSX2102GU8_XQFN8 for cost down.
D 3.reserve pull up resistor for signal MULTI_STRAP_REF0_GND 3.Delete reserved component CC44 for layout concern. 9/25: D
4.update hole symbol. 1.Mount RE254 ,CE339 For EMC.
2.Change RE22 , RE23 ,RC62 ,RC81 ,RC85 ,R909 ,R223,R224 to R short.
3.Change L69,L70 to EXC24CH900U for cost down
4/29: 0606:
1.use buffer for signal CPU_DRAMPG_CNTL 1.Change HDMI part 0.1uF cap to 0402 size Follow DG.
2.Add reserved Caps for keyboard signal follow EMC suggestion.
3.Add reserved Caps for HDA signal follow EMC suggestion 10/13:
1.Change CC23,CC24 to 3.3pF for RTC Time test fail in windows.
5/4:
1.Delete N15VGM@ part for Haydn only support N16S-GT.
0607:
1.Combine EC part resistor for bom quantity concern. 11/11:
1.Change CE339 to 18pF for HSW platform LPC CLK fall slew rate test fail issue.
5/6:
1.VR_ADP_ID change to USB_ID_N
2.EC_ADP_ID_ON# change to DCIN_USB_EN 6/9:
3.Delete GPU CMD signal pull up/pull down resistor 1.Change JHDMI to AHRW0-AK1200 follow ME connector list . 11/13:
4.update EC to LQFP package 2. Change JTP to 50505-00641-001 follow ME connector list . 1.Change R2,R22,R5,R13,RG20,R26,RC107,RC122,RC124,RE214,RE215,RE216 to R short for cost down.
. 3.Change JIO to ACES_51540-04041-001 follow ME connector list . 2. Mount RE50,QE3,Q23,R11,R238,C441 for clear CMOS.
4. Change JWLAN to LOTES_APCI0062-P007A follow ME connector list . 3.Change JWLAN to DEREN_40-42313-06742RHFL follow ME request.
4.Change JUSB30 to DEREN_40-42039-00901RHF-L Follow ME request.
5/8: 6/10:
1. Change YC1,YE1 to 32.768KHZ_12.5PF_200458-PG14 1.Modify JLVDS pin define.
2. Stuff QV7 for GPU +1.05V power 2. Add signal ILIM_SEL for USB charger.
3.Add one BJT on thermal sensor for GPU&VRAM
4. Change YC1 to 32.768KHZ_12.5PF_202740-PG14
6/12:
1.Change LV2 to PBY100505T-300Y-N ,LV1 to PBY100505T-181Y-N For smaller size.
5/9: 2.Reserve RTC_RST# schematic controlled by EC.
1. modify HDMI DATA signal connection . 3.Modify EC pin define(Four signals.)
C
2. renaming GPU command signal C
3.mount RC762, unmount DC27 for cost down .
6/16:
1.Change button switch SW4000,SW4001,SW4002,SW4003,SW4004 to EVQP7L01K_4P.
5/11:
1.Change UE1 to IT8386E-192-CX_LQFP128 for cost down
2.Change YC2 to 24MHZ_6PF_7V24000032 for cost down
3.Change D4,D5,D6,D13 to ESD9N5BL-2-TR_DFN1006-2 for cost down 6/17:
1.Change QV5，QC13，QC12，QV10 to AO5804EL_SC89-6 for layout concern.
2.Change CV22,CC121,CC130,CC131, CV103, CV104, CV105 to SE00000M00J for layout concern.
5/12:
1.Change JWLAN to LCN_DAN05-67146-0102
2.Delete JRTC. 6/18:
3.Change CC130 to SE00000PL0J for cost down 1.Modify GPU power on sequence .
4.Change D31,D32,D33 to AZ1045-04F for cost down 2.Change CV111 to SE00000M00J ,CV60 to SE107475K0J for layout concern.
3.Add thermal protection schematic .
4.Change QC11,Q149 to SB00000XP0J for layout concern.

5/14:
1.Change R105 to 1K ohm. 6/19:
2.Change CC44 to SGA00009900 for layout placement concern . 1.Delete thermal protection schematic dummy components since no space to placement .
3.Change QV8,QV17,QV21 to 2N7002KDWH for layout placement concern .

6/20:
5/15: 1.Add C217,C218,C220,C224,C225,C226 For CLK signal cross moat concern .
1.Change JFANC ,JFANS to 88231-04001 follow ME connector list . 2.Delete JCMOS1 ,add test point for signal RTC_RST#

5/19: SIV
1.Touch Pad change to I2C interface.
B 2.Haydn support two FAN ,connect the two FAN signal to EC . B
3.Delete one debug connector JDB3. 7/21:
4.delete deep S3 schematic part . 1.Delete CG380 For CG380/CG381 function repetition
5.Modify KB pin define . 2.Delete RV70,RV61 +1.35VGS/+1.05VGS Mosfet control signals power level change
3.Change CV54 from 0.1uf to 0.01uf，RV228 from 560ohm to 0ohm，CV506 from 0.1uf to 0.22uf for GPU power sequence change
4.Change touch pad to SMBUS solution.
5/20:
1.Move lid_pad# part schematic to USB DB .
7/29:
1.Delete QC5 (not connect to PCH)
2.Change RE218 from 0ohm to 100ohm for EC_RSMRST# overshot/undershot fail
5/21: 3.Add CC50 0.01uf for VCCST_PG_EC_R undershot fail
1.Change D34 to AZ1045-04F_DFN2510P10E-10-9 follow EMC suggestion . 4.Change RC61 from 0ohm to 100ohm for SYS_PWROK overshot/undershot fail
2.Change D7,D8,D9,D10 to AZ5425-01F follow EMC suggestion . 5.Change CC23,CC24 to 2.7pF ,CV19,CV20 to 12pF follow crystal vendor suggestion.
3.Delete SPI rom power control part schematic since not support DS3 now . 6.Change RE707 to 470K ,CC7 to 15pF follow crystal vendor suggestion.
4.Touch screen part function use the same connector with EDP .
08/05:
1.modfiy EC GPIO (EC_ON)
5/22:
1.Use cost down solution for signal CPU_DRAMPG_CNTL follow G . 08/07:
2.Change U56 to APL3523AQBI-TRG for cost down. 1.JLVDS rotate 180 degree
3.Change JKB to ACES_50506-0260M-001 follow ME connector list .

08/11:
5/26: 1.Change 0 ohm resistor(RC65,R184,RE188,R351,RC761,RD16,RD22，RE32，RC97，R110，R125,R121,R126
1.Change DV5,DV6 to BAT54AW_SOT323-3 for cost down. RC138,RE202,RE217,RC31,R109,R113,R114,RC758,RC759,RC105，RC103,RC99) to jump
2. Reserve JRTC 2. NO stuff CE6 ,CD88
3. modify JLVDS pin define .
4.Delete reserved components QV24,QV25 ,DV5 for signal VGA_PWRGD 08/11:
1.Mount RA27 ,CA25 Follow EMC suggestion.
2. Change JIO to HRS_FH52E-40S-0P5SH follow ME suggestion.
A 5/27: 3.Change JSATA to ELCO_006809610010846 follow ME suggestion.
A
1.Reserve CC110 for signal +1.05VS_DCPSUS4
2.Change JKB to ACES_50519-02601-001 follow ME connector list .
3. Change JTP to ACES_50503-0060N-001 follow ME connector list .
4. Delete WLAN AOAC part schematic .
5. Swap VRAM data group 2 ,group3 and Swap VRAM data group 6 ,group7 for layout routing concern .

5/28:
1.Reserve USB3.0 signal that connected to JIO. Security Classification LC Future Center Secret Data Title
2.Reserve R873,R874 for the possibility to cost down I2C redriver.
3.Change QV10,QV13 to 2N7002KDWH for layout placement concern . Issued Date 2014/01/11 Deciphered Date 2013/11/08 HW_Change_List
4.Swap VRAM data group 4 ,group6 for layout routing concern . THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
5.Change RPC10 to RPC10 and RPC21 for layout concern. Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Yoga3-BDW
Date: Monday, November 17, 2014 Sheet 35 of 45
5 4 3 2 1
 5 4 3 2 1

+5VLP/ 100mA
Silergy
D
SYX196C1QNC +5VALW/5A D
Converter
EN FOR SYSTEM PGOOD

Silergy +3VLP/ 100mA

AC Adapter
SYX196BQNC +3VALW
ANPEC
20V/40W/65W Converter +3VALW/ 5A
+1.5VS/100mA
FOR SYSTEM APL5930KAI-TRG
EN PGOOD EN
LDO
PAGE 42

Silergy
+1.35V/8A
TPS51716RUKR
Converter
+0.68V/1A
FOR DDR3L
EN PGOOD
TI PAGE 40
C C

BQ24715RGRR
B+
Battery Charger Silergy
Switch Mode SYX198DQNC +1.05VS/6A
IO Board / Page7 Converter
EN FOR CPU/PCH PGOOD
PAGE 41

SMBus
Onsemi
NCP81108MNTXG CPU_CORE / 14A
Switch Mode
FOR CPU IMVP7
EN PGOOD
Battery PAGE 43
Li-ion

2S2P /46WH Onsemi

B B

NCP81172MNTWG +VGA_CORE/31A
VIDs
Switch Mode
EN FOR GPU VDDC PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Yoga3-BDW
Date: Monday, November 17, 2014 Sheet 36 of 45
5 4 3 2 1
 5 4 3 2 1

V_PATH

PQ101
ADIN_1 AON6414AL_DFN8-5 PQ102 V_CHG
AON7408L_DFN8-5

1 3 PR101
For EMI request
2 2 PJ101
5 3 1 5 2 1 2 1
2 1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.01_1206_1%

1
PC104

PC105

PC106

PC107
PC101 JUMP_43X79

4
2
@
PC103 0.1U_0402_25V6

2
2200P_0402_50V7K

1
@
@

D D

715_ACN
B+

ADIN_1
9/25: Change PC109,PC110 from SE00000QK0J 10U 25V 0805 H1.25 to SE00000QK00 H0.85.
0.1U_0402_25V6 Add PC137 SGA0000490J 47U.
PR104 PD101

1
Delete PC111 SE00000QK0J.

47U_B2_10V_R70M
PC108

5
PR102 PR103 1 2 1 2 PQ111 1 To fix EE noise issue

PC137
10U_0805_25V6-K

10U_0805_25V6-K
4.02K_0402_1% 1 2

AON6552_DFN8-5

1
430K_0402_1% 10_0805_1% +
RB751V-40_SOD323-2

PC109

PC110
2
2

2
CHG_DH_R 4 2

1
ACDET

1
PC113

1
0.1U_0402_25V6 PC114 If SDV verify fail, need use more strong mosfet

2
PR105 0.1U_0402_25V6

3
2
1
68K_0402_1% CHG_VCC PQ104
V_PATH AO4407AL_SO8 BATT+ PF101 BATT+_2
PU101 PR107 1 8 12A_24V_F1206HB12V024T/M JBATT1
8A
2

1
PL101 2 7 1
PC115 CHG_PAHSE 1 2 2 1 3 6 1 2 2 1
1U_0603_25V6M 2.2UH_PCMB063T-2R2MS_8A_20% 5 EC_SMCA 3 2 9

2
3 GND1

1
1 20 0.01_1206_1% EC_SMDA 4 10
ACN VCC 4 GND2

1
PR108 5 11

4
715_ACP 2 11 BGATE 0_0402_5% PC117 6 5 GND3 12
PR106 ACP BATDRV RTC_VCC 6 GND4

1
CHRG_GND PD102 PQ105 10U_0805_25V6K PC118 7

BQ24715RGRR_VQFN20_3P5X3P5

2
1 2 3 16 REG_CHG 2 1 8 7

AON6414AL_DFN8-5
2
CMSRC REGN 8

1000P_0402_50V7K
RB751V-40_SOD323-2

2
4.02K_0402_1% AGATE 4 17 1 2
ACDRV BTST SUYIN_125022HB008M200ZL

2
ACDET 6 18 CHG_DH PR109 4 ME@
ACDET HIDRV 0_0402_5% PC119
10 0.047U_0402_25V7K

1
CELL

100_0402_1%
EMC@
PR110

100_0402_1%

PR111
19 PC120

3
2
1
PHASE

PR112
PC123 PC121 BGATE 2 1
15 CHG_DL 0.1U_0402_25V6 0.1U_0402_25V6

2
EC_SMB_DAT1 8 LODRV 1 2

2
SDA 0_0402_5%

1
14
EC_SMB_CLK1 9 GND CHRG_GND 0.1U_0402_25V6 CHRG_GND PC122
SCL 1000P_0402_50V7K

2
5 13

POWERPAD
ACOK SRP CHRG_GND
+3VL 7 12 715_SRN
29 VR_ADP_I IOUT SRN
29 EC_SMB_CLK1

1
PC124
100P_0402_50V8J

21
C C
2

REG_CHG
29 EC_SMB_DAT1

MBAT_PRES#_R
PR113 CHRG_GND
100K_0402_5%

1
CHRG_GND PC125 +3VL
1

1U_0402_10V6K
29 VR_ACIN

1
PR114
J101 CHRG_GND 100K_0402_5%
1 2 R_0402
PR115

2
JUMPER 0_0402_5%
1 2
29 BATT_TEMP

CHRG_GND

CMM21T-900M-N_4P
USB20_N7 4 3 USB20_N7_CON +5VALW
4 3 VUSB

USB20_P7 1 2 USB20_P7_CON 2A 0609 220UF change to B2 SIZE

1 2
1

100U_1206_6.3V6M

100U_1206_6.3V6M
PL102 EMC@ C105 1 1 1
.1U_0402_10V6-K
2

C106

C103
C104
.1U_0402_10V6-K
2 2 2
@
U101

PL104 1 8
HCB2012KF-121T50_0805 GND VOUT3
1 2 2 7
AC adapter 20V EMC@ VIN1 VOUT2
ADIN 3 6
VIN2 VOUT1 R103
PL103
PF102 HCB2012KF-121T50_0805 EC_USB_ON# 4 5 2 1
24,29,32 EC_USB_ON# EN/EN FLAG USB_OC3# 9
1 2 1 2
0_0402_5%
F1206HI7000V024TM EMC@
AP2820CMMTR-G1_MSOP8
1

2.2_0805_5%
1
ME@ Low Active 2A
2

PR116
BELLW_80188-2321 PR140 PC127
PR138 470K_0402_5% PC126
B 1 0_0402_5% 0.1U_0402_25V6 0.1U_0402_25V6 B
2

1
9 1 2 USB20_N7_CON 1 2 @ EMC@ EMC@
USB20_N7 9

2
8 GND4 2 3 USB20_P7_CON 1 2
GND3 3 USB20_P7 9

10U_0805_25V6K
7 4 USB_ID @
GND2 4

1
PC128
6 5 PR139
GND1 5 0_0402_5%
AZ5725-01F_DFN1006P2X

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

2
1

PJP1
1

1
PD105
PD103

PD104
2

2
2

ADIN_1
PQ106 PQ107 VUSB
EMC@ EMC_NS@ EMC_NS@ SI4483ADY-T1-GE3_SO8 AO4407AL_SO8 PQ108
8 1 1 8 AO4407AL_SO8
7 2 2 7 1 8
6 3 3 6 2 7
5 5 3 6
+3VL +3VALW
1

5
715_ACN
715_ACP

PC131
4

4
1

1
0.1U_0402_25V6
2

1
PR119 PR120

1
+1.05VS 200K_0402_1% PC133 470K_0402_5% PR148 PR149
0.47U_0402_25V6K 13.7K_0402_1% 13.7K_0402_1%
PC129 +1.05VS @
2

2
1

2 1 PR117 +3VALW

2
10K_0402_5%
2

0.1U_0402_25V6 PC130 @ @

1
+5VALW @ 0.1U_0402_25V6 PR118
1

PC132 10K_0402_5% PR129

1

1
2 1 @ PR128 200K_0402_5%

1
PU102 @ 5,29 CPU_PROCHOT# 2 PR123 1 CPU_PROCHOT# PR127 200K_0402_1% PH101
2
2

0.1U_0402_25V6 10 9 2 PR122 1 200K_0402_1% PR134

2
CSNPROCHOT#

2
PR121 @ 0_0402_5% @ 100K_0402_5% new added For USB 100K_0402_1%_TSM0B104F4251RZ
PD106
2

0_0402_5% 1 8 0_0402_5% @ PR150

2

2
@ CSP RESET PR124 1 2 USB_OPEN 0_0402_5%

2
2 7 1 2 +3VALW USB_ID_N 29
1

PR125 VCC OVSET PR126 +3VALW

1
RB751V-40_SOD323-2
1

+3VALW 1 2 3 6 1 2 2.94K_0402_1% @
ILIM UVSET
2

PC134 PC135 @ 24K_0402_1% @

GND

PD107
1

1
0.1U_0402_25V6 35.7K_0402_1% 2 1 4 5 PR130 set OVP D PQ110A D D PQ109
@ @ EN TMER 10K_0402_1% 5 USB_ID 2 2 USB_OPEN 2 1
DCIN_USB_EN 29
1

0.1U_0402_25V6 PR133 @ G G G
11

2
1

10K_0402_1% PQ110B
RB751V-40_SOD323-2
1

29
NTC_V
PR132 RT9553AGQW_WDFN10_3X3 @ S 2N7002KDWH_SOT363-6 S S 2N7002KW_SOT323-3
2

3
1

A PR131 10K_0402_5% PR136 2N7002KDWH_SOT363-6 PR137 PC136 A

10K_0402_1% @ 124K_0402_1% 200K_0402_5%
1

@ 0.1U_0402_25V6
2

@ 375K for 15uS

2

+3VALW 124K for 5uS

45W current limit 2.8A reverse

65W current limit 3.6A

Title
NVDC charger

Size Document Number Rev

D Paganini 1.0

Date: Monday, November 17, 2014 Sheet 37 of 45

5 4 3 2 1
 5 4 3 2 1

9/25: Change PC202,PC203,PC214,PC216 from SE00000QK0J 10U 25V 0805 H1.25 to SE00000QK00 H0.85.
Reserve PC230 SGA00007I00 220U.
To fix EE noise issue.

B+ B++
PU201
PJ201
2 1
2A 7 2 +3V_PWRGD
2 1 EN2 PG

10U_0805_25V6-K

10U_0805_25V6-K
0.1U_0402_25V6

SYX196BQNC _QFN10_3X3
1

1M_0402_5%
PC204 +3VALW

PC201

PC202

PC203

PR201
JUMP_43X79 8 6 +3VBS 1 2
IN BS
5A

2
@ 0.1U_0603_25V7-M PL201 PJ202
D D
9 10 +3VLX 1 2 +3VALW_P 2 1

2
GND LX 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2.2UH_PCMB063T-2R2MS_8A_20%
PR202

1
1 2 3V_GND +3VALW_EN 1 4 +3VALW_P JUMP_43X79
29 EC_ON EN1 OUT +3VLP

PC205

PC206

PC207

PC208
PR203
0_0402_5% 2.2_0805_5%
100mA @

2
+3VALW_FB 3 5 @
FB LDO

1 2
4.7U_0603_6.3V6K
1

1
PC210
@ PC209 PR204 PC211
0.1U_0402_25V6 1M_0402_5% 1000P_0402_50V9-J

2
@
PTP201

2
PAD

3V_GND 3V_GND
@

PC212
PR205
1 2 1 2

PJ203 0.01U_0402_25V7K 1K_0402_1%

1 2
+3VL
JUMPER +3VLP
PJ204
@ 2 1
2 1
3V_GND
JUMP_43X39

C C

+3VALW

2
PR206
100K_0402_5%

PR207 @

1
+3V_PWRGD 1 2
5A 9/25: Reserve PC230 for acoustic noise issue.
B+ PU202
0_0402_5% @

PJ205 PR208
220U_D_10VM_R25M

2 1 8 2 +5V_PWRGD 1 2
2 1 IN PG
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K
0.1U_0402_25V6

SYX196C1QNC_QFN10_3X3
1
1

+
PC218 0_0402_5% @ +5VALW
PC213

PC214

PC216

PC217

PC230

JUMP_43X79 9 6 +5VBS 1 2
GND BS
6A
2

@ PC219 0.1U_0603_25V7-M PL202 PJ206

2 1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
VCC LX 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
@
@ 1U_0603_25V6M 1.5UH_PCMB063T-1R5MS_10A_20%

1
EC_ON 1 PR209 2 5V_GND +5VALW_EN 1 4 +5VALW_P JUMP_43X79
EN OUT

PC220

PC221

PC222

PC223

PC224

PC225
0_0402_5% @ PR210
100mA +5VLP 2.2_0805_5%
@

2
+5VFB 3 7 @
PR213 1 2 0_0402_5% FB LDO

1 2
29 EC_ON_5V
1M_0402_5%

4.7U_0603_6.3V6K
1

1
1

PR211

PC227
PC228
@ PC226 1000P_0402_50V9-J

2
0.1U_0402_25V6 @
2

5V_GND
B B
5V_GND 5V_GND

PC229 PR212
1 2 1 2

470P_0402_50V8-J 1K_0402_1%
PJ207
1 2 8/1: Change PC229 from 6800pF to 470pF for 5VALW transient response issue with low voltage Vin.
JUMPER

@
5V_GND

3VALWP 5VALWP
VFB=2V TDC 5A
TDC 5A
Fsw=350KHZ Fsw=300KHZ
OCP:7.8A~9.5A OCP:7.8A~9.5A
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/02/20 Deciphered Date 2014/02/20 3VALWP/5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Paganini
Date: Monday, November 17, 2014 Sheet 38 of 45

5 4 3 2 1
 5 4 3 2 1

8/1: Follow EE request to stuff PC303 0.1u_0402_10v7k for EC_SYSON overshot/undershot fail

1
PC301 @
0.1U_0402_10V7K
D D

2
PR301 0_0402_5%
9/25: Change PC304,PC305 from SE00000QK0J 10U 25V 0805 H1.25 to SE00000QK00 H0.85
+3VALW @ 1 2
EC_SUSP# 29,33,40,41
To fix EE noise issue.
1k for 500K
@ 12k for 670K PR302 0_0402_5%
2 1
CPU_DRAMPG_CNTL 5,14

S3_1.35V
10K_0402_1%
PJ301
2A 2

110K_0402_1%
PR303
PR306 0_0402_5% 1.35V_B+ 1
2 1 B+

2 PR305 1

0.1U_0402_25V6
2 1
EC_SYSON 29,33

1
PC302

10U_0805_25V6-K

10U_0805_25V6-K
PR304 JUMP_43X79

1
S5_1.35V
1K_0402_1% @

PC304

PC305
UMA SKU OCP 2 1

2
PR305 change to 54.9K_0402_1% SD00000H88J

2
PC303 0.1U_0402_10V7K @
DIS@

5
20

19

18

17

16
PU301

S5
PGOOD

MODE

TRIP

S3
21 PR307 PC306
PAD 0_0603_5% 0.1U_0603_25V7-M
1
VTTSNS VBST
15 1
BST_1.35V 2 2 1 4 +1.35V
8A
+1.35V
1A 2
VLDOIN DRVH
14 UG_1.35V
PQ301
2A

3
2
1
22U_0805_6.3V6M

22U_0805_6.3V6M
PL301 PJ303
+0.68VSP 3 13 LX_1.35V AON7408L_DFN 1 2 2 1
VTT TPS51716RUKR_WQFN20_3X3 SW 2 1
1

1
PC307

PC308
0.68UH_PCMC063T-R68MN_15.5A_20% 1 @ JUMP_43X118

1
4 12
+5VALW
2

2
VTTGND V5IN

5
PR309 + PC309

1
@ 2.2_0805_5% 220U_D2_2.5VY_R6M

VDDQSNS
5 11 PC310 @
VTTREF DRVL 1U_0603_25V6M 2 3
+VTT_REFP

2
REFIN
1

PGND
VREF

1.35V_SN
GND
C PC311 LG_1.35V 4 C
1U_0402_6.3V6K

10
PQ302

1
10K_0402_1%
VREF AON7506_DFN

3
2
1
PR310
DIS@ PC312

2
1000P_0402_50V9-J

REFIN
PJ304

2
2 1 @
+0.68VSP 2 1 +0.68VS PC313

1
0.1U_0402_25V6
JUMP_43X79

1
@

1
1

PR311
PC314
31.6K_0402_1%
2

0.01U_0402_25V7K
2
+1.35VP
Vout=1.367V
Iocp min=13A fro DIS SKU
UMA SKU Iocp min=6A fro UMA SKU
PQ302 change to AON7408L for 4A output current

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_1.35V/0.68VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Yoga3-BDW
Date: Monday, November 17, 2014 Sheet 39 of 45
5 4 3 2 1
 5 4 3 2 1

D 9/25: Change PC401,PC403 from SE00000QK0J 10U 25V 0805 H1.25 to SE00000QK00 H0.85. D
Stuff PC401.
PR401 To fix EE noise issue.
1 2 1.05V_EN
29 EC_SUS_VCCP

0_0402_5%
B+
PJ401
PU401

1
JUMP_43X39
PR402
PR403 2
2 1
1 B+_1.05V 8
IN EN
1 PC405 +1.05VS

10U_0805_25V6-K

10U_0805_25V6-K
1M_0402_5%

0.1U_0402_25V6
2 1 0.1U_0603_25V7K
29,33,39,41 EC_SUSP#

1
PC404

SYX198DQNC_QFN10_3X3
6 1.05VP_BS1 2
BS PL401 7A PJ402

PC401

PC403
2
0_0402_5%

1
PC402 9 10 1.05VP_LX 1 2

2
@ GND LX

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
0.1U_0402_25V6 4 1UH_PCMB063T-1R0MS_12A_20% PJ_43x79_6

2
FB

1
C_0402 3 +3VALW
ILMT

PC406

PC407

PC408

PC409

PC410

PC411
PR404 7
@ 1 2 BYP PR405
+3VALW

2
2.2_0805_5%

680P_0402_50V7K 1K_0402_1%
@ 100K_0402_5% 2 @
PR406 PG 5 1.05VLDO @ @

2
LDO

PR407
1M_0402_5%

2
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1

1
@ PR408

2
PC413

PC414
100K_0402_1%

1
+3VALW PC416

PC415
1000P_0402_50V9-J

2
@

2
PR409
100K_0402_5%
R_0402 1.05VP_FB
@ PR410 @
2

2 1 680P 1K
C 0_0402_5% C

1
Fsw=800KHZ PR411
133K_0402_1%
Vfb=0.6V
Vout=1.051V

2
OCP:12A

+3VS
2

PR412
10K_0402_5%
@ +1.05VSP_VGA
1

PU402
2.5A
PJ403 PL402 PJ404
+3VALW 2 1 1.05VMP_VIN 4 3 1.05VMP_LX 1 2 2 1 +1.05VGS
2 1 IN LX 1UH_PH041H-1R0MS_3.8A_20% 2 1
22U_0805_6.3V6M

22U_0805_6.3V6M

68P_0402_50V8J
JUMP_43X79 5 2 @ JUMP_43X79
PG GND
1

1
PC417

PC418

@ 6 1 PR413 @
FB EN

PC419
2.2_0805_5%
2

2
SY8032ABC_SOT23-6

1
75K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
PR414
@ FB=0.6Volt @
B B

PC420

PC421
@ @ @
1

2
PC422

2
1000P_0402_50V9-J
2

PR415
2 1 1.05VGS_EN 1.05VMP_FB
18,19,42 EN_VGA
0_0402_5% @ @
1

@
1

PR417
1

PR416 PC423 100K_0402_1%

0_0402_5% 1M_0402_5% 0.22U_0402_10V6K @
PR418 1 2 @
18,20,42 DGPU_PWROK
2

2
2

@
@ Reverse only

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_1.35V/0.68VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Yoga3-BDW
Date: Monday, November 17, 2014 Sheet 40 of 45
5 4 3 2 1
 5 4 3 2 1

D D

+3VALW
+1.5VSP +1.5VS
50mA
50mA
PJ501 PU501 PJ502
2 1 3 4 2 1
2 1 VIN VOUT 2 1

4.7U_0603_6.3V6K

1
2
JUMP_43X39 GND JUMP_43X39 @

PC502
@ 5
SET

1
1 PR502

2
SHDN 21.5K_0402_1% PC503 PC504
220P_0402_50V7K 10U_0603_6.3V6M
APL5325BI-TRG_SOT23-5

2
PR501 @
C 1 2EN_1_5VSP C
29,33,39,40 EC_SUSP#
0_0402_5%
1

1
PC505 PR504
.1U_0402_10V6-K 24K_0402_1%
2

2
VFB=0.8V

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 PWR_VCCSA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Yoga3-BDW
Date: Monday, November 17, 2014 Sheet 41 of 45
5 4 3 2 1
 5 4 3 2 1

+3VGS

2
PR602
10K_0402_5%
@ PD601
RB751V-40_SOD323-2

1
OPT@
16,18 3VGS_PWR_EN 2 1 1 2 EN_VGA EN_VGA 18,19,40
D D
PR603

1
0_0402_5% PC601
N15SGT@ PR604 .1U_0402_10V6-K
100K_0402_5% 2 1 OPT@

2
@
PR605

2
10K_0402_1%
OPT@ +VGA_B+

16 NVVDD_PWM_VID NVVDD_PWM_VID PJ601

2 1 B+
PSI_VGA 2 1
16 PSI_VGA

17 VSSSENSE_VGA VSSSENSE_VGA JUMP_43X79

10U_0805_25V6K

10U_0805_25V6K
0.1U_0603_25V7K
17 VCCSENSE_VGA VCCSENSE_VGA @

1
PC603

PC604
AON6414AL_DFN8-5
NVVDD_PWM_VID

PC602
18,20,40 DGPU_PWROK DGPU_PWROK

2
PQ601
4

PR607 PC605 OPT@ OPT@ OPT@

N15S-GT use config-B 0_0603_5% 0.22U_0603_16V7K

3
2
1
N15V-GM use config-D 2 1BOOT1_2_VGA 1 2 PR608 OPT@
OPT@ 0_0402_5%
2 1 UGATE1_2_VGA PL601 +VGA_CORE
B D 0.24UH_PCME063T-R24MS1R145_35A_20%
reserve 1 2

BOOT1_VGA
N15S-GT N15V-GM

5
10P_0402_50V8J
PQ602 OPT@

1
@
R1 PR9440 20 27

1
AON6554_DFN
PC606
PC607
2700P_0402_50V7-K @ PR609
R2 PR9434 20 7.5

330U_B2_2VM_R15M
1 2 2.2_0805_5%

220U_D2_2.5VY_R6M
1 1
LGATE1_VGA 4 @
C
R3 PR9436 2 0 + +
C

PC609

PC608
reserve follow

1SNUB1_VGA 2
NV suggestion
R4 PR9437 18 6.2 PR610 PR611

1
2 3 2

PSI_VGA

EN_VGA
20K_0402_1% 20K_0402_1% UGATE1_VGA OPT@
R5 PR9431 0 1.74

3
2
1
VREF_VGA 2 1 2 1VIDBUF PR612
N15SGT@ N15SGT@
C(nF) PC1277 2.7 5.6 5.1K_0402_1%

1
@

PHASE1_VGA
PR613

2
2K_0402_1% PC610
PU601

1
PR614 PR615 N15SGT@ 1000P_0402_50V9-J OPT@ OPT@

2
0_0402_5% 18K_0402_1% @

VIDBUF

PSI
VID

EN

HG1

BST1
2
PR616 N15SGT@ 2 1 2 1N15SGT@ reserve for future tune
100_0402_5%
2 1 PC612 1
PC611 2N15SGT@ 7 24
OPT@ 0.01U_0603_50V7K REFIN PH1 PC613
OPT@1 2 2700P_0402_50V7-K VREF_VGA 8 23 4.7U_0603_6.3V6K
PR617 VREF LG1
PR618 2 1OPT@ FS 9 22 1 2 OPT@
0_0402_5% 39K_0402_1% FS PGND
VSSSENSE_VGA OPT@2 1 VSS_SEN 10 21 PVCC_VGA 2 1 +5VS
FBRTN PVCC
PC615 FB_VGA 11 20 PR619
FB LG2
1

PC614 47P_0402_50V8J PR620 PC616 0_0402_5% +VGA_B+

1000P_0402_50V7K 1 2FB1_VGA 1 2 1 2 COMP_VGA 12 19

TALERT#
COMP PH2

PGOOD
PR621 OPT@ 51_0402_1% OPT@ 10P_0402_50V8J
2

TSNS
0_0402_5% OPT@ PR622 OPT@ PC617

BST2
GND

VCC

HG2
VCCSENSE_VGA OPT@2 1 VCC_SEN 1 2 1 2FB2_VGA1 PR623 2

10U_0805_25V6K

10U_0805_25V6K
OPT@ OPT@

0.1U_0603_25V7K
AON6414AL_DFN8-5
10K_0402_1% 100P_0402_50V8J 82K_0402_1%OPT@

25

13

14

15

16

17

18

1
PC619

PC620
OPT@ NCP81172MNTWG_QFN24_4X4

PC618
PR624
100_0402_5% BOOT2_VGA PR625

VCC_VGA

2
PQ603
1 2 0_0402_5%
+VGA_CORE
OPT@ UGATE2_VGA 2 1 UGATE2_2_VGA 4

1
5.9K_0402_1%
PR631
DGPU_PWROK
PR627
B B
10K_0402_5% PR626 PC622 OPT@ OPT@

3
2
1
2 1 +3VS 0_0603_5% 0.22U_0603_16V7K OPT@ OPT@

2
@ 2 1 BOOT2_2_VGA 1 2
OPT@ PL602 +VGA_CORE
VREF_VGA OPT@ 2 1 +5VS 0.24UH_PCME063T-R24MS1R145_35A_20%
PR629 OPT@ PHASE2_VGA 1 2
2.2_0402_5% OPT@

5
PQ604
PC623

1
AON6554_DFN
1U_0402_10V6K
1

OPT@ PR630

330U_B2_2VM_R15M
2.2_0805_5% 1
LGATE2_VGA 4 @
+

PC624
1SNUB2_VGA 2
OPT@ 2

3
2
1
PC625 OPT@
1000P_0402_50V9-J

2
@

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC626

PC627

PC628

PC629

PC630

PC631
A A

2
@ @ @ @
OPT@ OPT@
NC PC631 for cost down

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/08/05 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Yoga3-BDW
Date: Monday, November 17, 2014 Sheet 42 of 44
5 4 3 2 1
 5 4 3 2 1

D D

PR701
130K_0603_1%
1 2 SW3

PR702 28W@

220K_0402_5%_ERTJ0EV224J
165K_0402_1%
1 2

0.047U_0402_16V7K
CSREF

75K_0402_1%

20K_0402_1%
PR704

2
130K_0603_1%

1
PH701

PR703

PC703

PR705
1 2 SW1
PC701 PC702
Place close to 220P_0402_50V7K 220P_0402_50V7K
PR706

2
phase 1 inductir
2

1
CSP3 @ 2 1 SW3
28W@
2K_0402_1%

1000P_0402_50V7K
28W@
+5VS +5VS

2
PC704

0_0402_5%
1

PR738
1

0_0402_5%
PR714
15W@
C CSREF 44 C
PR712 change to 25.5K_0402_1% SD03425528J for 28W CPU
PR710 change to 30.9K_0402_1% SD03430928J for 28W CPU

2
CSP3

0.047U_0402_16V7K
CSREF

20K_0402_1%
CSP2

2
1

PC705

PR707
CSP1

CSSUM
CPU_B+ 29 VR_IMVP_IMON

PR708

2
@

1
CSP1 2 1 SW1
PR710
2

CSCOMP 1 2 2K_0402_1%
PR709
2

0_0402_5%

1K_0402_1%
25.5K_0402_1%
PR711

15W@
1

1
0.01U_0402_25V7K

PC706 PC707
1

PR713 390P_0402_50V7K 10P_0402_50V8J PR712

1 2 1 2 1 2 20.5K_0402_1%
PR715
1
PC708

15W@ PU701 PR717 PC709

27
26
25
24
23
22
21
20
19
49.9_0402_1% 1 2 NCP81108MNTXG_QFN36_5X5 2.2_0603_5% 0.22U_0402_10V6K
2

30.1K_0402_1% 1 2 1 2

CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1

BST3
DRON
PWM2/IMAX
2

PC710
PR716 PC711
1 2 1 2 1 2 2 1 28 18
ILIM HG3 HG3 44
PR718 29 17
IOUT SW3 SW3 44
1K_0402_1% 5.11K_0402_1% 2200P_0402_50V7K 470P_0402_50V8-J 30 16 PC712
VRMP LG3 LG3 44
31 15 1 2 PR719
32 COMP PVCC 14 0_0402_5%
PR721 33 FB PGND 13 2.2U_0603_10V7K 1 2
1 2 VSN_2 34 DIFFOUT LG1 12
LG1 44 +5VS
12 CPU_VSS_SENSE VSN SW1 SW1 44
0_0402_5% 35 11
VSP HG1 HG1 44
36 10
VR_HOT#

B B
VCC BST1
1

VR_RDY

TSENSE
ENABLE

PS1_PH
ALERT#

PC713 1 2 PR722 PC715

ROSC

37
SCLK

1000P_0402_50V7K 2.2_0603_5% 0.22U_0402_10V6K

SDIO

PC714 @ GND 1 2 1 2
2

10 CPU_VCC_SENSE 2200P_0402_50V7K
1
2
3
4
5
6
7
8
9

PR725
1 2 45.3K_0402_1%
VR_HOT#_1

+5VS 1 2
TSENSE
CPU_SVID_ALERT#
2.2U_0603_10V7K

PR724 PR726
CPU_SVID_DAT

CPU_SVID_CLK
VR_RDY

2_0603_5% 0_0402_5%
2
PC716

1 2
10 CPU_VR_ON
TSENSE
2

1 2
1

29 VR_HOT# PC717
PR727 .1U_0402_16V7K
1

0_0402_5%
2

PR728

100K_0402_1%_TSM0B104F4251RZ
32.4K_0402_1%
+1.05VS
1

13K_0402_1%
2

2
PR729

PH702
2

1
130_0402_1%

75_0402_1%

0_0402_5%
54.9_0402_1%

@
2

PR731

PC718
1

1
PR730

PR733

PR734

.1U_0402_16V7K PR732
1

10K_0402_5% Place close to

phase 1 MOSFET
2

2
1

@
A A
CPU_SVID_DAT
10 CPU_SVID_DAT
+3VS

10,29 VR_CPU_PWROK
CPU_SVID_ALERT#
10 CPU_SVID_ALERT#

<BOM Structure>
CPU_SVID_CLK
10 CPU_SVID_CLK
Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01

CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, November 17, 2014 Sheet 43 of 45
5 4 3 2 1
 5 4 3 2 1

D D

CPU_B+
PJ801
2 1
2 1 B+

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6K
PQ801 @ JUMP_43X118

AON6414AL_DFN8-5

1
PC801

PC802

PC803
PR801
2.2_0603_1%

2
2 1 4
43 HG1 +CPU_CORE
@

3
2
1
PL801
1 2
43 SW1

1
0.22UH_SPS-06CZ-R22M-V1_23A_20%
5

PQ802 PR802
43 LG1 2.2_0805_5%
AON6554_DFN @

2
4 2 1

1SNUB_CPU1
CSREF 43
PR803
10_0402_1%
3
2
1

C PC806 +CPU_CORE C
1000P_0402_50V9-J
2

@
40A

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC807

PC808

PC809

PC810

PC811

PC812

PC813
CPU_B+
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K
5

47U_B2_10V_R70M

PQ803

2
AON6414AL_DFN8-5

1
1

1
PC814

PC815

PC816

PC817

PR804 +
2.2_0603_1% 28W@
2

2 1 4
43 HG3 2@ +CPU_CORE
@
28W@ 28W@ 28W@

22U_0805_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0805_6.3V6M
3
2
1

1
PC820

PC821

PC822
28W@

PC819

PC823
PL802
1 2
43 SW3

2
1

0.22UH_SPS-06CZ-R22M-V1_23A_20%
5

PQ804 PR805 @ @
43 LG3 2.2_0805_5% 28W@ 28W@
AON6554_DFN

@
2

PR806
4 2 1 CSREF
SNUB_CPU3

1
10_0402_1%
+

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
28W@ PC824
28W@ 220U_D2_2.5VY_R6M
3
2
1

1
PC829

PC830
2 3

PC826

PC827

PC828
1

B B

2
PC825
1000P_0402_50V9-J
2

@ @ @
28W@

8/15: NC PC819，
，PC823，
，PC826，
，PC827 for cost down.

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC831

PC832

PC833

PC834

PC835
2

2
28W@ 28W@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Yoga3-BDW
Date: Monday, November 17, 2014 Sheet 44 of 45
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/01/11 Deciphered Date 2013/11/08 CPU (1/7) DMI, FDI, PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Yoga3-BDW
Date: Monday, November 17, 2014 Sheet 45 of 45
5 4 3 2 1