A Faster Approach Towards Fault Detection

and Diagnosis in ASICs and FPGAs

By

Sumit Raj
200631006

A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE

REQUIREMENTS FOR THE DEGREE OF

Master of Science (by Research) in VLSI & Embedded Systems

Under the Supervision of

Prof. Satyam Mandavilli

i
Centre for VLSI & Embedded Systems Technologies

International Institute of Information Technology

Hyderabad, India
May 2010

Copyright © 2010 Sumit Raj

All Rights Reserved

ii
 Dedicated to my parents,

C. P. Sinha and Sheela Sinha,

iii
 INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY

Hyderabad, India

CERTIFICATE

Fault detection and diagnosis

in ASICs and FPGAs Sumit Raj (200631006)

iv
Acknowledgements

v
Abstract

vi
vii
viii
ix
x
Contents

Introduction

BASICS of VLSI testing

xi
Literature Survey

Fault location in ASICs using POTG Algorithm

A modified Built in Self Test (BIST) for testing of FPGAs

xii
 Conclusion

Appendix I

Details of ASIC testing

Appendix II
FPGA and its simulator

Bibliography

xiii
List of Figures

xiv
List of Tables

List of Equations

xv
List of Relevant Publications:-

xvi
 fault

diagnosis
 test

vectors
Defect Level T

Eq. 1.1 …………

Y € [0,1]

DL F € [0,1]

T € [0,1]


 Design o
f r Testability

It’s

1. Verification testing
 Production testing:

Burn-in Testing

Incoming Inception:

 Parametric Test:

 Functional Tests:
n n
 fault

failure
netlist



interconnections

single stuck-at
exhaustive testing



test vector is above 22 then it’s
fault diagnosis
 effect-cause diagnosis

fault dictionary.

scheme, faults are located by “looking up”

simulations, most digital simulations have been limited to the “single stuck fault” model.
n
Goel
–
Pseudo-exhaustive testing
 – Verification

Testing m

hardware partitioning

b) sensitized partitioning

Partial hardware partitioning

 6

9
 Verification Testing

m
 in which configuration is set by “burning” internal fuses to

m m

m m

m
 k

2n n = 2k

configuration
 test configuration (TC) test patterns (TPs)

2n


 weight

has been applied to ISCAS’85 Benchmark circuit and results have been obtained.
carried out in which POTG Algorithm has been applied to ISCAS’85 Benchmark circuit and
 r the circuit is fault free or the vector can’t detect. If there is a difference

fault dictionary.


weight

ISCAS’85 benchmark Appendix I

–
Procedure:T

coverage required (say ‘x’). The

Begin
for j input bits ( 0 to 2n)
for i ( 0 to number of faults)
if ( Z != Zif )
test_vector [j] weight function ++ ;
sort_test_vector [ ] = SORT (test_vector [ ])
while (fault coverage != x)
SELECT (sort_test_vector [ ])
END
A typical combinational Benchmark circuit namely ISCAS’85, circuit C499 is analyzed for
 FD  FD

I F

FD 

modified
m n

m n,

weight function

…f
BEGIN

CREATE (fault_dictionary = D[ ][ ])

for i ( 0 to number of faults)

sort_D [i ][ ] = SORT (D[i][ ])

// increasing order based on weight function of test vector

for i (0 to number of fault)

unique_set = sorted_
D[i] [0 : p]

// ‘p’ number of test vector for each fault

END
These vectors T1…