Plateforme Cyclone IV

EDA/SOPC CycloneIV Experiment
Development Platform
Development Manual
（EDA）
Hua Heng Technology Co., LTD
1
Diectory
BASIS EXPERIMENT....................................................................................................... 4
EXPERIMENT 1 SIMPLE EXAMPLES OF QUARTUSII ........................................................ 4

EXPERIMENT 2 GRAY CODE ENCODER VHDL-BASED DESIGN ............................................ 29
EXPERIMENT 3 ZERO WITH ASYNCHRONOUS AND SYNCHRONOUS ENABLE THE ADDITION OF
COUNTER ........................................................................................................................ 34
EXPERIMENT 4 8 X 7-SEG LED DYNAMIC DISPLAY CIRCUIT DESIGN ................................. 39
EXPERIMENT 5 NC DIVIDER DESIGN ................................................................................. 43
EXPERIMENT 6 GRAPHICS AND VHDL MIXED INPUT CIRCUIT DESIGN ............................... 46
EXPERIMENT 7 VARIABLE STEP SUBTRACTION COUNTER DESIGN ....................................... 52
EXPERIMENT 8 4-BITS PARALLEL MULTIPLIER DESIGN ...................................................... 55
EXPERIMENT 9 4-BITS FULL ADDER DESIGN ..................................................................... 59
EXPERIMENT 10 DESIGN OF CONTROLLABLE PULSE GENERATOR ...................................... 63
EXPERIMENT 11 FLIP-FLOP DESIGN ................................................................................. 67
APPLICATION OF THE EXPERIMENTAL SECTION................................................ 70
EXPERIMENT 12 MATRIX KEYBOARD DISPLAY CIRCUIT DESIGN........................................ 70

EXPERIMENT 13 16X16 MATRIX LED EXPERIMENT .......................................................... 77
EXPERIMENT 14 DC MOTOR SPEED TEST ............................................................................ 84
EXPERIMENT 15 STEPPER MOTOR DRIVE CONTROL .......................................................... 91
EXPERIMENT 16 PS2 KEYBOARD AND DISPLAY INTERFACE E XPERIMENT .......................... 97
EXPERIMENT 17 VGA COLOR SIGNAL GENERATOR DESIGN .............................................. 105
EXPERIMENT 18 VHDL DESIGN WITH SEVEN VOTING .................................................... 111
EXPERIMENT 19 DESIGN FOUR RESPONDER WITH VHDL ................................................ 114
EXPERIMENT 20 POSITIVE AND NEGATIVE PULSE WIDTH MODULATION SIGNAL GENERATOR
DESIGN ......................................................................................................................... 117
COMPREHENSIVE DESIGN OF EXPERIMENTS .................................................... 121
EXPERIMENT 21 DIGITAL FREQUENCY METER DESIGN.................................................... 121

EXPERIMENT 22 MULTI-FUNCTION DIGITAL CLOCK DESIGN ............................................ 129
EXPERIMENT 23 DIGITAL STOPWATCH DESIGN ................................................................ 133
EXPERIMENT 24 TAXI METER DESIGN ......................................................................... 137
EXPERIMENT 25 DESIGN OF DIGITAL LOCKS WITH VHDL ............................................... 141
SCHEDULE I：CPU BOARD AND FPGA(EP4CE40) PIN MAPPING ...................... 145
SCHEDULE II：SYSTEM BOARD AND CPU BOARD IO MAPPING ..................... 152
2
Preface
In recent years due to the rapid development of VLSI technology and software to
enable the integration of digital systems into a possible integrated circuit, Altera, Xilinx,
AMD and other companies have launched a very good CPLD and FPGA products, and
for those product design with a design, download the software, which supports graphical
design software in addition to digital systems, but also supports a variety of digital
systems design design language, so that a digital system design much easier. In
small-scale digital integrated circuits would phase out today, as an electronic technician
understand project VHDL language and CPLD, FPGA design elements like the use of
computers in the computer age is not as terrible.
The purpose of this guide book is to help readers learn to design digital systems, and
are familiar with the use of Altera's products and software QUARTUS Ⅱ and other
related software.
The experimental guide books Experiment Subject combinational circuit design
from simple to design complex digital systems, a detailed description of the various
operating systems and software design methods. Readers can design your own digital
circuits through which the experimental instructions.
The experimental guide book written nearly ten representative experiment,
Experiment Subject from simple to complex, so that users can quickly start, while the
experimental guide book can also serve as electronic technology to enhance curriculum
or as an ad hoc division of Electronic Technology reference books.
The experimental guide book with HH-SOC-EP3C40 EDA / SOPC system
development platform series products.
3
Basis Experiment
Experiment 1 Simple examples of QUARTUSII
I. Experiment Object
1、Through a simple one and 3- 8 designs of decoder, know the design
method to make logical circuit up.
2、Understand tentatively QUARTUSII principle picture inputs the whole

course designed.
3、Know that makes the static method of testing of the logical circuit up.
II. Experiment Theorem
The 3-8 decoder has 3 Input, 8 output. , at N, output end mark output the
high level, say, have the signal produce as input signal for output end of N
according to the intersection of binary scale and person who say of way, but
other level for being low show that there is no signal to produce. Because
three the intersection of association and state that input terminus can produce
have 8, so output end have one under the situation of high level only in each
association, can express all input associations. Their truth tables are shown in
Table 1-1
Input Output
A B C D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
4
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
Table 1-1 3-8 Decoder Truth Table
The decoder does not need to point out whether it is effective to export
with an output end like encoder. But can add one into input and can carry to
make to export, is used for pointing out whether to carry on effective decoding
of present input, when can carry to make and instructing the input signal to be
invalid or decoding present signal, output ends are all high level, show that
there is not any signal. It can enable the input terminus to consider in design
of this example, can consider joining and enable being can be at the time of
the input terminus while designing oneself, how does the procedure designs.
III. Experiment Subject

In this experiment, show through the way that three Switch three of three 8
decoders are input (A, B, C) ; Show with 8 LEDs 8 of three 8 decoders are exported
(D0-D7) . Observe result and three 8 truth table of decoder that input by
inputting different values ' Table 1-1) Whether it is unanimous. The
intersection of experiment and stiring switch and the intersection of interface
and the intersection of circuit and picture the following of FPGA 1-1 show,
close as switch in the case When it output to levels low,last high level. Its
circuit is connected with pin of the tube of FPGA and shown in Table 1-2
5
Fig 1-1 DIP Switch and FPGA Circuit
Signal Name FPGA I/O CPU Board Pin Description

K[0] Pin_W6 JP3_62 ‘K1’ Button
K[1] Pin_Y4 JP3_60 ‘K2’ Button
K[2] Pin_U7 JP3_58 ‘K3’ Button
K[3] Pin_V3 JP3_54 ‘K4’ Button
K[4] Pin_P5 JP3_50 ‘K5’ Button
K[5] Pin_AB12 JP3_42 ‘K6’ Button
K[8] Pin_R5 JP3_57 ‘K9’ Button
‘K10’
K[9] Pin_T5 JP3_53
Button
‘K11’
K[10] Pin_P4 JP3_49
Button
‘K12’
K[11] Pin_AA11 JP3_41
Button
Table 1-2 DIP Switch and FPGA Pin
LED lights and FPGA interface circuit as shown in Fig 1-2, when the
FPGA and its corresponding port is a high potential LED will light, and
vice versa LED lamp. Corresponding with the FPGA pin connections as shown
in Table 1-3.
6
Fig 1-2 LED and FPGA Circuit

LED[0] Pin_V10 JP3_68 LED1 display
LED[1] Pin_W8 JP3_67 LED2 display
LED[3] Pin_Y10 JP3_69 LDE4 display
LED[4] Pin_Y13 JP3_72 LED5 display
LED[5] Pin_V11 JP3_71 LED6 display
Table 1-3 LED and FPGA Pin
IV. Experiment Step

Below, to introduce the reader QUARTUSII generated during the
operation of the project files, compile, pin assignment and timing
simulation through this experiment.
7
1、Create Project File
1) Select Start> Programs> Altera> QuartusII8.1> QuartusII8.1
(32Bit), perform QUARTUSII software. QUARTUSII icon or double-click on
the desktop software to perform QUARTUSII appears as shown in Fig 1-3,
if the software is first opened QUARTUSII information may be other prompts,
the user can be set according to their actual situation show as Fig 1-3.
Fig 1-3 QUARTUSII software operates interfaces
2) Select the software menu File> New Project Wizard, create a new
project. As shown in Fig 1-4.
3）Click NEXT to enter in Fig 1-4 working directory name of the project
settings dialog box as shown in Fig 1-5. The first input box for the
project directory input box, the user can enter e :/ eda work as a path
to set the project directory, set up, all of the generated files will
be placed in the working directory. The second input box for the project
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name input box, and the third input box to the top-level entity name input
box. Users can set as EXP1, under normal circumstances the project name
and the entity with the same name. Users can also set their own actual
situation.
Fig 1-4 New Project Wizard
Fig 1-5 Project Name,directory
4）Click NEXT, go to the next Setup dialog box, click on NEXT default
option for component selection dialog box. As shown in Fig 1-6. Here we
select CycloneIII series chips EP3C40F780C8 introduces an example.
9
Depending on the user can use to set the wafer.
Fig 1-6 Device Setting
First select the top left of the dialog box Family drop-down menu Cyclone Ⅲ,
select 8 in the middle of the right side of the Speed grade drop-down menu in the
lower left of the Available devices box, select EP3C40F780C8, click NEXT to
complete the selected components into the EDA TOOL set the interface as shown in
Fig 1-7.
10
Fig 1-7 EDA TOOL
5）By default options, click New Project NEXT appeared all previous
configuration information, as shown in Fig 1-8, click FINISH to complete
the establishment of the new project.
Fig 1-8 New Project Information
2、Create Diagram/Schematic File
1）After creating a good design project, select File> New ... menu appears as
shown in Fig 1-9 new design file type selection window. Here we Create Diagram /
Schematic file as an example, with other design entry method is basically the same.
11
Fig 1-9 The New Project Window
2）In the New dialog box, select (Fig 1-9) Block Diagram Device Design Files
page under / Schematic File, click the OK button to open the Graphics Editor dialog
box, as shown in Fig 1-10. Figure marked commonly used functions of each button.
12
Fig 1-10 QUARTUSII Graphics Editor
QUARTUSII graphical editor also called block editor (Block Editor), used in
the form of a circuit diagram (Schematics) and Structure (Block Diagrams) input and
edit graphic design information. QUARTUSII graphics editor can read and compile
the structure of design files (Block Design File) and MAXPLUSII graphic design
files (Graphic Design Files), you can open the file in QUARTUSII graphic design
software and save it as a structure of the design file.
In QUARTUSII graphic editor window (Fig 1-10), depending on personal
preference, you can always change the Block Editor display options, such as a guide
wire and grid spacing, rubber band function, color and attributes, such as the basic
unit and blocks.
3）Here in order to design a thirty-8 decoder with schematic entry, for example,
describes the steps the basic unit symbol input method. In Fig graphics editor
window as shown in the work area 1-10 double-click the left mouse button, or click
on the symbol drawing tool button or select the menu Edit> Insert Symbol ..., then
jump out as shown in Fig 1-11 the Symbol dialog box.
13
Fig 1-11 Symbol Window
4）Click on the front of the library's "+" sign, expand the library, the user can
select the desired graphics or element, the element is displayed on the right side of
the display element window, the user can enter the name of the component in your
component name you need, click the OK button, the selected element will be
displayed in the graphical editor work area.
5）Illustrated with reference to Fig 1-12, component symbols will be placed in
the selected work area graphics editor, with orthogonal node tool components pick up,
and then define the name of the port. In this example, the definition of the three
inputs A, B, C, is defined as the 8 outputs D0, D1, D2, D3, D4, D5, D6, D7. Users
can also according to their own habits to define these pin name called.
6）After completing the input graphics editing, you need to save the design file
or rename the design file. Select File> Save As ... items, dialog box appears as shown
in Fig 1-13, choose a good file storage directory and file name field, enter the name
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of the design file. If you need to add design files to the current project, the following
dialog box select Add file to current project check box, and click the Save button to
save the file. It should be noted that, throughout the design file is saved in the process,
are required to follow the general rules of design input method.
Fig 1-12 The Design file
Fig 1-13 Storage Design File
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3、Compile Design File
QUARTUSII compiler window contains the whole process of design files
processed. Select Processing in QUARTUSII software> Compiler Tool menu item,
then there QUARTUSII compiler window, as shown in Fig, the figure marked the
function of each module of the whole process of compiling 1-14.
Fig 1-14 QUARTUSII compiler window
It should be noted that during the synthesis and analysis of design files, you can
also open a separate analysis of the consolidation process does not have to be a full
compiler interface. Upon completion of the setting of the window, click the START
button to compile the design of the whole file. If the file is wrong, the software will
prompt at the bottom of the cause and location of the error, which enables users to
modify the design file until no wrong. Entire compilation is complete, the software
will prompt compiled successfully, as shown in Fig 1-15.
Fig 1-15 Compile Successsful
4、Pin assignment
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In front of choosing a suitable target elements (selected for EP3C40F780C8 in
this experiment), a comprehensive analysis of the design process is complete, after
the ad hoc data files, the need for design input and output pins are assigned to a
specific device pin number, specify the pin number is called pin assignment or pin
lock. Here are two ways to pin lock.
1）Click the Assignments menu below Assignment Editor, enter the Pin
assignment window. As shown in Fig 1-16.
Fig 1-16 Pin assignment
The first signal pin to be allocated placed below To. To double-click on the
bottom of the "New", as shown in Fig 1-15 interface appears as shown in 1-17 Fig
Fig 1-17 Signal selection dialog
Select the Node Finder ... enter Node Finder dialog box as shown in Fig 1-18
interface. Fig 1-18 in the example set by parameters. In the Filter window, select Pins:
all, enter "*", click the name of all the signals appear in the Nodes Found List
17
window in the Named window, click button is Selected pin name appears
selected, said bottom Nodes window. Double-click the OK button to complete the
setting. Pin assignment into the window, as shown in Fig 1-19.
Fig 1-18 Node Finder
In Fig 1-19 to lock port A pin-for example, the other port pin lock its basically
the same. Select the corresponding port A is Name Assignment let it turn blue,
double-click it, select the drop-down menu appears, as shown in Fig 1-19 Location
18
(Accepts wildcards / groups) option. Select the corresponding port A Value column,
and let it turn blue, according to Table 1-2 and Table hardware and FPGA pin
connections as shown in Table 1-3 (or appendix), enter the corresponding pin name
AH12, press the Enter key, the software will automatically convert it into PIN_AH12,
while the blue selection bar will automatically jump to the next line Value column,
indicating that the software has been assigned to the input port a FPGA-AH12 pick
feet, as Fig 1-20 shown.
Fig 1-20 Port A Pin assignment
The same way, in accordance with Table 1-2 and hardware and FPGA pin
connections as shown in Table Table 1-3 (or appendix), on the other port for Pin
assignment, as shown in Fig 1-21.
Fig 1-21 All pin assignment after all software window
2）Click the Assignments menu below Pin Planner (also directly click Pin
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assignment button on the toolbar) as Fig selected target chip pinout shown in Figure
1-22 appears.
Fig 1-22 Pinout diagram target wafer
The same way as above, in accordance with Table 1-2 and Table hardware and
FPGA pin connection table (or appendix) as shown in 1-3, as the corresponding
port A pin is AG12, AG12 pin then appear as double-clicking 1-23 dialog box
shown in Fig
Enter the name of the corresponding pin A in Fig 1-23 Node Name dialog box
20
or via the drop-down menu to select the corresponding pin name called A, click the
OK button to complete the port of A Pin assignment.
In the same way, according to the following Table 1-4 for the other port for
Pin assignment, Pin assignment finished, as shown in Fig 1-24.
Fig 1-24 All pin assignment after all software window
Pin Name Module Signal FPGA IO Description

A DIP Switch K1 Pin_AH12
3 Input Of
B DIP Switch K2 Pin_AF14
Decoder
C DIP Switch K3 Pin_AA8
D0 LED1 Pin_AE8
D1 LED2 Pin_J22
D2 LED3 Pin_M24
D3 LED4 Pin_L24 8 Output Of
D4 LED5 Pin_L23 Decoder
D5 LED6 Pin_H23
D6 LED7 Pin_H24
D7 LED8 Pin_F24
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Table 1-4 Pin assignment
In Fig 1-24, the brown pin marked as having been allocated lock pin. Notably,
when Pin assignment must be then completed a full compile, so that the pin
assignment is valid.
5、Design files for Simulation
1）Create of an analog waveform file, select QUARTUSII Software File>
New, conduct new file dialog box. As shown in Fig 1-25. Select dialog Verification
/ Debugging Files tab, select from Vector Waveform File, click the OK button, then
open an empty Waveform Editor window, as shown in Fig 1-26.
Fig 1-25 New Waveform file
Fig 1-26 Waveform editer
2）Setup end time simulation, simulation waveform editor preset end time
1μS, according to the simulation needs, they can set the simulation end time. Select
QUARTUSII software Edit> End Time command, out of line End Time dialog box
at the end of the input analog Time time, click on the OK button to complete the
setting.
3）Add input and output ports, the waveform editor window to the left of Pin
Name list, click the right mouse button and select Insert from the context menu that
appears in> Insert Node or Bus ... command in the pop Insert Node or Bus dialog
box as Fig Figure 1-27 interface click Node Finder ... button.
22
Fig 1-27 Insert Node or Bus
Node Finder interface appears, as shown in Fig 1-28, in the Filter list, select
Pins: all, enter "*", click on the List the names of all signals in the Nodes Found
window appears, click on the window in the middle of button is selected Pin
Name appears below the Nodes window says. Double-click the OK button to
complete the setting and return to Fig Insert Node or Bus dialog box shown 1-27,
double-click the OK button, all the input and output ports will be displayed in the Pin
Name list of the region, such as Fig 1-29 show.
Fig 1-28 Node Finder
23
Fig 1-29 nput the port in the waveform editor
4）Edit input port waveforms, which specifies the input port logic level changes,
as shown in Fig 1-29 waveform editing window, select the input port to the input
waveform such as A port on the left side of the waveform display area Pin Name
According to the simulation needs the input waveform. After completion as shown in
Fig 1-30. Finally, select Software File> Save to save.
Fig 1-30 Edit Input Waveform
5）Specify the simulator settings, there are timing simulation and functional
24
simulation of the points during the simulation, functional simulation presented here.
Select QUARTUSII software Processing> Simulator Tool command, open the
emulator tool window, as shown in Fig 1-31.
Fig 1-31 Simulation Window
Follow the prompts on Fig 1-31, the first to produce functional simulation
netlist file, click on the button Generate Functional Simulation Netlist produce
functional simulation netlist, generating functional simulation netlist, then click the
START button to start the beginning of the simulation to simulate analog progress
until Article 100 percent complete simulation. Click the button to simulate the report
window Report, observed analog waveform. As shown in Fig 1-32.
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Fig 1-32 Simulate Waveform
6、Loading Design File to Device
Completion of the loading element has two forms, one is loading files on the
target elements, one is to configure the chip target elements were loaded. Here we
introduce EP3C40F780C8 be loaded on the target element method.
1) Use USB cable to connect the PC with the experimental system (please refer to
the user manual specifically III USB Blaster installed and used).
2) Select QUARTUSII Software Tool> Programmer command, enter the burn
window, as shown in Fig 1-33, if the hardware is not set to burn, then burn the
hardware type No Hardware, the hardware needs to be set to burn . Click the
Hardware Setup ... button to set burning hardware, be as shown in Fig 1-34 burning
hardware settings dialog box.
Fig 1-33 Program Window
26
Fig 1-34 Program Hardware Setup
3）Click the Add Hardware button Add Hardware dialog box appears, as shown
in Fig 1-35.
Fig 1-35 Add Hardware
4）In the Add Hardware dialog box, select the Hardware type from the list the
type of hardware needed, if it is USB interface, please refer to the user manual of the
USB Blaster installation and use, if you use a parallel cable is selected as Fig 1-36
type of hardware shown, click on the OK button to complete the set of hardware
types. Back burner hardware settings window, click the Close button to exit. In the
burn dialog box will appear burning hardware just choose the type of burner
hardware.
5）If the software has performed a project, then open the window when burning,
27
burning window will automatically appear in this project file to the file you want to
load the target component, if you want to load other files can be added to change
from other places. After selecting the loaded file, and then click Progam / Configure,
Burn Mode Select JTAG mode, click STRAT for file loading until the loading
progress to 100%, the file loaded successfully completed.
V、Experiment Result
After the file is loaded into the target cell, toggle DIP switch, the LED will light
up according to the truth table shown in Table 1-1 correspond. Because after four lights
LED lights module LED9-LED12 is not used, but QUARTUSII software default
settings unused IO is high impedance tri-state, so after four lights LED9-LED12 been
lit.
VI、Experiment Conclusion
1、More familiar with and understand how to use QUARTUSII software.
28
Experiment 2 Gray code encoder VHDL-based design
1、 Understand one yard of principles varied of Grey.
2、 The whole course that operation method and VHDL further familiar
with QUARTUSII software input.
3、 Further grasp the use of the experimental system.

Grey Yard is a kind of dependability code, there is extensive application in the
digital system. It features that only there is a different binary number in two
arbitrary adjacent codes, therefore is difficult to make mistake in increase and
decreasing operation of the number. But Grey whether one have no right yard in
yard, think of the correct and simple one and binary scale yard is changed, must
find out its law.
According to making the logical circuit analytical method up, list its truth
table first and then pass the abbreviation of picture of Kano, it is can very fast
find out on Grey on yard and relations logic between binary scale yard. It
changes the law: High position with,unless similarities and differences of
viewing from the point of it is low to be up toing, whose name is different to
appear ' 1 ', with appearing ' 0 '. That is to say while converting the binary scale
yard to Grey yard, the high position is all the same, the Grey still ' 0 ' in yard,
adjacent two the intersection of binary scale and " different " of yard totally " the
same as " It determines to come. Now citing a simple example proves.

If should convert yard to Grey binary scale yard 10110110, can finish by
following method, method such as Fig 2-1.
29
Fig 2-1 Schematic drawing of the Gray code transformation
So, yard of Grey varying out is 11101101.
III.Experiment Subject
This experiment requires the task finished is that binary scale yard which
varies 12 to yard. Show in the experiment 12 binary scale are input by 8 K1-
K12 which stir the module of switches, show yard of 12 Grey of experimental
result changed with LED1- LED12 of LED module. The experiment LED shows
the corresponding location is that ' 1 ', it shows the corresponding location is
that ' 0 ' that LED kills bright. Result and conversion in the the intersection of
experiment and principle input to observe identical in rule by inputting different
values. Interface circuit which stirs switch, and FPGA in the experiment case, it
is made in the experiment one that LEDis connected with interface circuit and
stiring switch, LED with the pin of the tube of FPGA of FPGA to explain in detail,
are not going into details here.
IV. Experiment Step

1、 Open QUARTUSII software, newly build a project.
2、 After finishing building the project, newly build another VHDL File. Newly
build the course of a VHDL file as follows:
1）Select File>New in QUARTUSII software to order, presents New
communication frame. As shown in Fig 2-2.
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Fig 2-2 New VHDL File
2）In New communication frame ' Fig 2-2) China chooses VHDL File
under Device Design Files page, clicks OK button, turns on VHDL editing
machine communication frame, as shown in Fig 2-3.
Fig 2-3 VHDL Edit Window
3、 According Experiment Theorem and their ideas in writing VHDL VHDL
program edit window, the user can refer to the example provided in the program
CD.
4、 After you have written VHDL program storage. Approach with the experimental
one.
5、 Compile and program for VHDL simulation, modify the program for errors.
6、 After compiling simulation is correct, according to the DIP switch, LED and
FPGA pin connection table (Table 1-1, Table 1-2) or a reference in Appendix Pin
31
assignment, Table 2-1 is an example of the program's Pin assignment table. After
the assignment is complete, and then compile a whole, so Pin assignment to take
effect.

K1 DIP Switch K1 Pin_AH12
K2 DIP Switch K2 Pin_AF14
K3 DIP Switch K3 Pin_AA8
K4 DIP Switch K4 Pin_AB8
K5 DIP Switch K5 Pin_AE4
K6 DIP Switch K6 Pin_AC5 Gray encoder

K7 DIP Switch K7 Pin_AF12 data entry
K8 DIP Switch K8 Pin_AG12
K9 DIP Switch K9 Pin_AA10
K10 DIP Switch K10 Pin_U8
K11 DIP Switch K11 Pin_AE3
K12 DIP Switch K12 Pin_AD4
D1 LED1 Pin_AE8
D2 LED2 Pin_J22
D3 LED3 Pin_M24
D4 LED4 Pin_L24
D5 LED5 Pin_L23
D6 LED6 Pin_H23 Gegere coding
D7 LED7 Pin_H24 encoder output
D8 LED8 Pin_F24
D9 LED9 Pin_E24
D10 LED10 Pin_F22
D11 LED11 Pin_E22
D12 LED12 Pin_F21
32
7、 Download sof file is loaded into the FPGA via JTAG. Observed experimental
results are consistent with their programs.
V. Experiment Result
In reference to the example design, for example, when the design file
is loaded into the target cell, toggle DIP switch, LED will follow
Experiment Theorem in Gray code input correspondence bright or off.
VI. Experiment Conclusion

1, Draw analog waveform, and for illustration.
2, More familiar with QUARTUSII software.
3, Experiment Theorem, the design process, compile and analyze the
results of the analog waveform hardware and test results recorded.
33
Experiment 3 Zero with asynchronous and synchronous
enable the addition of counter
1、 To understand the binary counter works.
2、 More familiar with the use of methods and VHDL input QUARTUSII
software.
3、The clock role in the programming process.

One of the binary counter up applications, features the most comprehensive counter
with asynchronous and synchronous zero enable the addition of specific work
process counter as follows:
In the case of the rising edge of the clock, enable detection of whether the
client is allowed to count, if allowed to count (defined high potential effectively
enable end) then start counting, otherwise enable end signal has been detected. In
the process of re-counting the reset signal is detected asserted (active low), the reset
signal when the function, the count value of zero, proceed detected and counted.
Figure 3-1 shows the timing of their work:
Fig 3-1 Counter Operation Timing
34
The experiment required to complete the task in the role of the clock signal, via
the enable terminal and a reset signal to the counter to complete the addition.
Experiments using a digital clock signal source module 1Hz clock signal with a million
DIP Switch K1 represents enable end signal, said reset signal to reset the switch S1,
with the LED module LED1 ~ LED11 to represent two counts carry results.
Experimental LED light indicates the corresponding bit is '1 ', LED off indicates that
the corresponding bit is '0'. By entering different values simulated counter timing data,
observations count. Experimental tank DIP switch, and FPGA interface circuits, LED
lights and FPGA interface circuit and DIP switches, LED and FPGA pin connections
are made in the experiment described in detail, not repeat them here.
Circuit schematic digital clock signal module shown in Figure 3-2,
Table 3-1 is its clock output and FPGA pin connection table.
Fig 3-2 Digital clock signal module circuit schematic
Signal Name FPGA Pin Name Explanation
Digital clock signal to the

DIGITAL-CLK A14
FPGA-A14
Table3-1 Digital clock output and FPGA pin connection table
Circuit schematic digital clock signal module shown in Figure 3-2,
Table 3-1 is its clock output and FPGA pin connection table.
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Fig 3-3 Key switch module circuit schematic

S[0] Pin_B12 JP1_79 ‘S1’ Switch
S[1] Pin_B11 JP1_77 ‘S2’ Switch
S[2] Pin_V4 JP3_56 ‘S3’ Switch
S[3] Pin_T4 JP3_52 ‘S4’ Switch
S[4] Pin_P3 JP3_48 ‘S5’ Switch
S[5] Pin_AB11 JP3_40 ‘S6’ Switch
S[6] Pin_A12 JP3_78 ‘S7’ Switch
S[7] Pin_A11 JP3_76 ‘S8’ Switch
S[8] Pin_V5 JP1_55 ‘S9’ Switch
S[10] Pin_AA12 JP3_43 ‘S11’ Switch
Table 3-2 Key switch and the FPGA pin connection table
IV. Experiment Step

1、 Open QUARTUSII software, create a new project.
2、 After completing construction projects, then create a VHDL File and
open VHDL Editor dialog box. According Experiment Theorem and their
36
ideas in writing VHDL VHDL program edit window, the user can refer to the
example provided in the program CD.
3、 After finish writing VHDL program storage. Approach with the experimental
one.
4、 4, I have written a program to compile and simulate VHDL, modify the
program for errors.
5、compiled simulation is correct, according to the DIP switch, LED and FPGA
pin connection table（Table 1-1、Table 1-2）Or reference in Appendix Pin
assignment。Table3-3 is Sample programs Pin assignment table。After the
assignment is complete, and then compile a whole, so Pin assignment to take
effect.
CLK Digital signal Pin_T2 Clock is 1Hz
EN DIP Switch K1 Pin_W6 Enable signal
RET Key switch S1 Pin_B12 Reset Signal
CQ0 LED1 Pin_V10
CQ1 LED2 Pin_W8
CQ2 LED3 Pin_W10
CQ3 LED4 Pin_Y10
CQ4 LED5 Pin_Y13
CQ5 LED6 Pin_V11 Count output

CQ6 LED7 Pin_W14
CQ7 LED8 Pin_W13
CQ8 LED9 Pin_Y8
CQ9 LED10 Pin_W7
CQ10 LED11 Pin_Y7
COUT LED12 Carry bit signal

Pin_Y6
of COUT
Table3-3 Pin Assignment Table
37
6、 with the corresponding burner download sof file is loaded into the FPGA via
JTAG. Observed experimental results are consistent with their programs.
is loaded into the target cell, the clock select digital signal source is
1Hz, so DIP Switch K1 is set to a high potential (DIP switch allows up),
four bit LED will follow the Experiment Theorem is lit in sequence, when
applied to the adder 9, LED12 (into the bit signal) is lit. When the reset
button (key switch S1 key) is pressed, the count is zero. If DIP Switch
K1 is set to a low potential (DIP switch down) the adder does not work.

1、 Draw analog waveform, and for illustration.
2、 Write the rules in VHDL programming process should be noted.
3、 Experiment Theorem, the design process, compile and analyze the
4、 Hanging the clock frequency, the experiment to see what will change
phenomenon and try to explain this phenomenon.
38
Experiment 4 8 x 7-Seg LED Dynamic Display Circuit
Design
1、 To understand the working principle of the 7-Seg LED .
2、 Learning segment display decoder design.
3、To learn VHDL CASE statement and multi-level design methods.

Seven segment displays are commonly used in electronic development process
output display device. Used in the experimental system is one of two four bit, 7-Seg LED
common cathode type. Its single static segment display as shown in Figure 4-1.
Fig 4--1 Static Segment Display
As the 7-Seg LED common terminal connected to GND (common cathode type),
when that one segment of the 7-Seg LED is the high potential, the corresponding
section is lit it. On the other hand is not bright. Four bit in a single one of the 7-Seg LED
on the basis of the static segment display added bit select signal port is used to select
which one 7-Seg LED . 8 7-Seg LED of a, b, c, d, e, f, g, h, dp are linked together, 8
7-Seg LED are selected by the respective bit signals to control, selected seven segment
display data, and the rest off.
The experiment required to complete the task in the role of the clock signal input
39
through the key displays the corresponding key on the 7-Seg LED . In the experiment,
the digital clock is selected as the scan clock 1KHz, with four DIP switches as input,
when the four DIP switches set to a binary number, which displays the hexadecimal
value of the 7-Seg LED . Experimental tank DIP switch interface circuit and FPGA,
FPGA's and DIP switch pin connections are made in the experiment described in detail,
not repeat them here.
7-segment display circuit schematic modules such as Fig 4 - 2 as shown
in Table 4-1 is its 7-Seg LED with the FPGA input pin connection table.
Fig 4--2 Digital Clock Signal Module Circuit Schematic

Seg[0] Pin_H15 JP2_22 7-Seg display “a”
Seg[1] Pin_H14 JP2_21 7-Seg display “b”
Seg[2] Pin_H16 JP2_20 7-Seg display “c”
Seg[3] Pin_N16 JP2_19 7-Seg display “d”
Seg[4] Pin_P16 JP2_18 7-Seg display “e”
Seg[5] Pin_R15 JP2_17 7-Seg display “f”
Seg[6] Pin_R14 JP2_16 7-Seg display “g”
Seg[7] Pin_T13 JP2_15 7-Seg display “dp”
SEL[0] Pin_N17 JP2_31 7-Seg COM port setcle
40
SEL[1] Pin_P17 JP2_30
SEL[2] Pin_R16 JP2_29
Table 4-1 7-Seg LED with the FPGA pin connection
IV. Experiment Step

2、 after the completion of the construction project, and then create a
VHDL File, Open VHDL Editor dialog box.
3、 according to Experiment Theorem and their ideas in writing VHDL VHDL
CD.
4、 After finish writing VHDL program storage, approach with the Experimental 1.
5、 To compile and simulate VHDL program, and modify the program for errors.
6、 Compiled simulation is correct, according to the DIP switch, 7-Seg LED with
the FPGA pin connection table (Table 1-1, Table 4-1) or a reference in Appendix
Pin assignment. Table 4-2 is an example of the program's Pin assignment table.
After the assignment is complete, and then compile a whole, so Pin assignment
to take effect.

CLK Digital signal Pin_T2 Clock is 1KHz
KEY0 DIP Switch K1 Pin_W6
KEY1 DIP Switch K2 Pin_Y4

Binary data input
KEY2 DIP Switch K3 Pin_U7
KEY3 DIP Switch K4 Pin_V3
LEDAG0 7-Seg LED A Pin_H15
LEDAG1 7-Seg LED Pin_H14 Hexadecimal data

LEDAG2 7-Seg LED C Pin_H16 output display
LEDAG3 7-Seg LED D Pin_N16
41
LEDAG4 7-Seg LED E Pin_P16
LEDAG5 7-Seg LED F Pin_R15
LEDAG6 7-Seg LED G Pin_R14
LEDAG7 7-Seg LED DP Pin_T13
DEL0 位選 DEL0 Pin_N17
DEL1 位選 DEL1 Pin_P17
DEL2 位選 DEL2 Pin_R16
7、 With the corresponding burner download sof file is loaded into the FPGA via
JTAG. Observed if the experimental results are consistent with their programs.
In reference to the example design, for example, when the design file is loaded into
the target cell, the digital signal is selected as the clock source module 1KHz, four
million toggle DIP switch, it is a value, then 8 Seven-segment DIP switch display
showed a hexadecimal value represented.

1、 draw analog waveform, and for illustration.
2、 shows how the scan clock is working, what happens to change the scan
clock.
42
Experiment 5 NC divider design
1、 NC divider learning design, analysis and testing methods.
2、 Understand and master the method divider circuit implementation.
3、 Master the hierarchical design method EDA technology。

NC divider (Numerical Control Frequency Division Machine)when the input
function is given different inputs, the input clock signal will have a different divider ratio,
NC divider is preset count value addition in parallel counter design is completed the
method is to count the number of pre-loaded with the overflow bit input signal phase
obtained.
The experiment required to complete the task in the role of the clock signal
through the input octet DIP switch input different data, changing the division ratio, the
output port output clock signals of different frequencies, to divide the numerical
results. In the experiment, the digital clock selection 1KHz as the clock signal input
(too frequently observed LED flashing speed), with 12 DIP switches as input data,
when 12 DIP switch is set to a binary number when , the clock signal at the output
port of the corresponding output frequency, the user can change the signal with an
oscilloscope connected to the output module observed frequency. You can also make
the output port connected to LED lights to observe the changes in frequency. In this
experiment we enter the access LED light module. Experimental tank DIP switch,
LED and FPGA interface circuits, and DIP switch, LED and FPGA pin connections
are made in the experiment described in detail, not repeat them here.
IV. Experiment Step

2、 After the completion of the construction project, and then create
a VHDL File, Open VHDL Editor dialog box.
43
3、 According to Experiment Theorem and their ideas in writing VHDL VHDL
CD.
4、 after finishing writing VHDL program storage, approach with the experimental
one.
5、 To compile and simulate VHDL program, modify the program for errors.
6、 compiled simulation is correct, according to the DIP switch, LED and FPGA pin
connection table (Table 1-1, Table 1-2) or a reference in Appendix Pin
assignment. Table 5-1 is an example of the program's Pin assignment table.
After the assignment is complete, and then compile a whole, so Pin assignment
to take effect.
INCLK Digital signal Pin_T2 Clock is 1KHz
DATA0 DIP Switch K1 Pin_W6
DATA 1 DIP Switch K2 Pin_Y4
DATA 2 DIP Switch K3 Pin_U7
DATA 3 DIP Switch K4 Pin_V3
DATA 4 DIP Switch K5 Pin_P5
DATA 5 DIP Switch K6 Pin_AB12

Divide ratio data
DATA8 DIP Switch K9 Pin_R5
DATA9 DIP Switch K10 Pin_T5
DATA10 DIP Switch K11 Pin_P4
DATA11 DIP Switch K12 Pin_AA11
FOUT LED1 Pin_V10 Divide Output
44
is loaded into the target cell, the digital signal is selected as the clock
source module 1KHz, DIP switch toggle octet, it is a value, then the input
clock signal makes LED lights start flashing, changing DIP switch, LED
flashing speed will change according to certain rules.

1、 Enter different values plotted DATA analog waveform, and for
illustration.
2、On the basis of this program is to expand into a 16-bit divider, write
VHDL code.
45
Experiment 6 Graphics and VHDL mixed input Circuit
Design
1、 To learn module generates files in the calling component QUARTUSII
software.
2、 master the rules and methods of connection module component and module
components.
3、 Master file building process from design to module components.

In the hierarchical design files, you often need to have designed the project file to
generate a modular component file as its calling function modules element at the top of
the graphic design elements like any other file in the same macro functional elements
level design can be called repeatedly. The experiment Experiment Theorem is to design
experiments in front of three, four, five through QUARTUSII design software combined
into one file. Experimental realization of three, four, Fifth of all functions.

The experiment required to complete the task with the experimental three, four,
five Experiment Subject basically the same. In the experiment, the clock signal
selection 1KHz as 7-Seg LED of the scan clock, DIP switch input a preset 12-bit, after
NC divider circuit (test five) after crossover to get a lower frequency as addition
counter (experiment III) clock frequency counter adder. Values obtained for the 7-Seg
LED decoder circuit (Experiment IV) displayed on the 7-Seg LED. Experimental box
in digital clock module, thumbwheel switch, key switch, 7-Seg LED, LED and FPGA
interface circuits, and DIP switch, key switch, 7-Seg LED, LED and FPGA pin
connections in Experiment 3 Fourth, Fifth done a detailed description, not repeat them
46
here.
IV. Experiment Step

2、 Copy the experimental 3, 4 and 5 code to the current working directory
and store them.
3、 Select File> Open command, shown in Figure 6-1, opens copied to the
current working directory, and one of the code, such as EXP3.VHD
program.
Fig 6-1 Open a Design File
4、 In the File menu, select Create / Update item, and then select Create
Symbol for Current File, click the OK button, you can create a design
element just open file functions (. Bsf) on behalf of, shown as Fig
6-2. If the file corresponding component file has been created before,
then perform the operation tooltip will pop up and asks whether you
want to overwrite the existing component file. The user can choose
according to their own wishes.
47
Fig 6-2 Create a Module Component Files From the Current File
5、 using the same method to other design files (EXP4.VHD, EXP5.VHD) be
established modular component file.
6、 he modular component file is created, then create a graphics editing
files, open the Graphics Editor dialog box. In the graphic editor window,
double-click the left mouse button work area, or click on the symbol
drawing tool button or select the menu Edit> Insert Symbol ..., then
jump Symbol dialog box shown in Figure 6-3.
48
Fig 6-3 Symbol Symbol Dialog Box
7、 In the Symbol dialog box Project item (Fig 6-3) will be established
in front of the module component file (EXP3, EXP4, EXP5), we can now
call any of these functions module component file.
Fig 6-4 Design Graphic Elements File
8、 Select the module component files placed into the workspace, later transferred to
the module components needed to connect between symbols, as well as placing the
input, output, or bidirectional pin. It should be noted that, in this experiment,
because the input data takes up 12 bit a DIP switch, so as to synchronize the enable
signal EN end we added a VCC signal to the enable signal EN effective end. After
the completion of all design circuit as shown in Fig 6-4.
9、 On this own graphic symbol input file written program for storage, then compile
and simulation, modify the program for errors.
10、 Compiled simulation is correct, according to the DIP switch, LED and FPGA
pin connection table (Table 1-1, Table 1-2) or a reference in Appendix Pin
assignment. Table 6-1 is an example of the program's Pin assignment table. After
the assignment is complete, and then compile a whole, so Pin assignment to take
effect.

49
DATA0 DIP Switch K1 Pin_W6
DATA 1 DIP Switch K2 Pin_Y4
DATA 2 DIP Switch K3 Pin_U7
DATA 3 DIP Switch K4 Pin_V3 Show clock

DATA 4 DIP Switch K5 Pin_P5 control Control
DATA 5 DIP Switch K6 Pin_AB12
DATA 8 DIP Switch K9 Pin_R5
DATA 9 DIP Switch K10 Pin_T5
DATA 10 DIP Switch K11 Pin_P4
DATA 11 DIP Switch K12 Pin_AA11
RET Key switch S1 Pin_B12 Reset Signal

COUT LED1 Pin_V10 Flag is ignored
LEDAG1 7-Seg LED B Pin_H14
LEDAG2 7-Seg LED C Pin_H16

Information
Display
DEL0 CS DEL0 Pin_N17
DEL1 CS DEL1 Pin_P17
DEL2 CS DEL2 Pin_R16
Table 6-1 Pin assignment Table
50
source module 1KHz, struck 12 bit DIP switch to a value, and the 8 7-Seg
LED according to a certain rate began to show "0-F", When 7-Seg LED to
display AF LED1 began to be lit, the display turns off when other values
. Press S1 button to display the values 0 and from the beginning, toggle
octet DIP switch, put the additional information, the display rate 7-Seg
LED will change.

1、 Draw analog waveform, and for illustration.
2、 To own design file, and then through the design files to the converter
module component files, design your own circuit and verify the
experimental system. Further understand this approach.
3、 Written by other methods in the software files to the conversion
process from design module component files.
51
Experiment 7 Variable step subtraction counter design
1． Deepen their understanding of the counter.
2． Learn experiments using VHDL counter process.

Counter counter each time step is the amount of change, such as 74LS169
components, it changes every time either plus 1 or minus 1, therefore, we say this is a
step counter.
n many applications, all hope of the counter variable step size. The so-called
variable step size, the step counter is a fixed value, the specific number depends on the
outside intervention. For example, given its external step is 5, then the counter each
time either plus 5, or minus 5, meaning that every time you change the amount of
counter 5. This step counter variable only has a certain practical significance, such as
the address of the accumulator in DDSF is a step increments the counter variable.

The experimental task is to implement a simple 12-bit counter, the step change in
the amount requested from 0-15 variable in the design using DIP switches K1-K4 as a
step change in the amount of inputs used to control K12 counter subtraction. Specific
requirements: K12 input is high when the potential, the counter increments the variable
counter adder; K12 when input is low, the counter is a down counter variable step size.
The output of the counter with 12 LED lights to indicate its binary code. Experiments
in order to counter it with a clock frequency of 1Hz clock as observed with frequency
stepping. Experimental box in digital clock module, DIP switch, LED and FPGA
interface circuits, and digital clock source, DIP switch, LED and FPGA pin connections
in previous experiments have done a detailed description, not repeat them here.
IV. Experiment Step
52
1、 open QUARTUSII software, create a new project.
2、 fter the completion of the construction project, and then create
a VHDL File, Open VHDL Editor dialog box.
program edit window, the user can refer to the example provided in the
program CD.
4、 After finish writing VHDL program, stored.. Approach with the
experimental one.
6、 compiled simulation is correct, according to several sources, DIP switch,
LED lights and FPGA pin connection table or reference in Appendix Pin
After the assignment is complete, and then compile a whole, so Pin
assignment to take effect.

STEP0 DIP Switch K1 Pin_W6
STEP1 DIP Switch K2 Pin_Y4

Step input data
STEP2 DIP Switch K3 Pin_U7
STEP3 DIP Switch K4 Pin_V3
UD DIP Switch K12 Counter

Pin_AA11
subtraction control
COUNT0 LED D1 Pin_V10
COUNT1 LED D2 Pin_W8

Counter output
display
COUNT3 LED D4 Pin_Y10
53
COUNT5 LED D6 Pin_V11
the target cell, the digital signal is selected as the clock source module 1Hz, toggle
DIP Switch K1-K4, enter a four-element data as a variable the step length was
observed LED lamp 12 is not changing by performing the subtraction step variable.
Slide DIP Switch K12 LED is switched observed not by design ideas during the
addition and subtraction counter.

1、 gives a different multiplier and multiplicand, painted analog
waveform, and for illustration.
2、 on the basis of this program is to design an 8-bit parallel
multiplier.
3、 on the basis of this program, with 7-Seg LED to show the result is
multiplied by a decimal value.
results of the analog waveform hardware and test results
recorded.
54
Experiment 8 4-Bits Parallel multiplier design
1、 To understand four-bits Paralled multiplier.
2、 To understand the idea of four-bits multiplier design.
3、 master basic binary arithmetic method using VHDL.

Methods to achieve parallel multiplier there are many, but boils down to is
basically divided into two categories, one is to rely on a combination of logic circuit,
and the other pipeline implementation. The biggest advantage of parallel multiplier
pipeline structure is fast, especially in the continuous input multiplier, but you can
achieve near-cycle operation speed, but to implement than the combinational logic
circuit is slightly more complicated. Here combinational logic circuit realization
unsigned multiplication method for details.
If there multiplicand A and multiplier B, first with A and B are obtained by
multiplying the lowest S1, then the left one and then A 2 B bit obtained by multiplying
S2, then A left 3 and B is obtained by multiplying the third S3, and so on, until all the
bits B are finished by far, and then the multiplied results S1, S2, S3 ...... i.e., obtained
by adding the multiplication result.
It should be noted that the implementation of the multiplier to multiply is not real,
but to achieve a simple judgment, give a simple example. If A is multiplied with the left
bit first n bits B n, if the B is '1 ', then the result of the multiplication intermediate result
is shifted left by n bits after the A, B, if this is otherwise' 0 ', then multiplying the result
directly in the middle is 0. After all bits are multiplied with the B end, the sum of all the
intermediate results that get results A and B multiplied.

The experimental task is to implement a simple four-bits parallel multiplier,
55
multiplicand A DIP switch module with K1 ~ K4 expressed multiplier B is represented
by K7 ~ K10, the result is multiplied by LED modules LED1 ~ LED12 to indicate,
LED light indicates that the corresponding bit is '1 '. Select 1KHz scan clock signal as
the clock, enter a four-digit DIP switch element multiplicand and a four multiplier
circuit has been designed after the information is obtained by multiplying displayed on
the LED lights. Experimental box in digital clock module, DIP switch, LED and FPGA
interface circuits, and digital clock source, DIP switch, LED and FPGA pin connections
in previous experiments have done a detailed description, not repeat them here.
IV. Experiment Step。

1. Open QUARTUSII software, and create a new project.
2. Create a VHDL File, and open VHDL Editor dialog box.
3. Follow Experiment Theorem and their ideas in writing VHDL VHDL program
edit window, the user can refer to the example provided in the program CD.
4. having written VHDL program storage, approach with the experimental one.
5. Compiled VHDL simulation program, modify the program for errors.
6. Compiled simulation is correct, according to several sources, DIP switch, LED
lights and FPGA pin connection table or reference in Appendix Pin assignment.
Table 7-1 is an example of the program's Pin assignment table. After the
effect.
A0 DIP Switch K4 Pin_W6
A1 DIP Switch K3 Pin_Y4 Multiplicand
A2 DIP Switch K2 Pin_U7 data
A3 DIP Switch K1 Pin_V3
B0 DIP Switch K10 Pin_V7 Multiplier Data
56
B1 DIP Switch K9 Pin_V6
B2 DIP Switch K8 Pin_R5
B3 DIP Switch K7 Pin_T5
COUT0 LED12 Pin_Y6
COUT1 LED11 Pin_Y7
COUT2 LED10 Pin_W7
COUT3 LED9 Pin_Y8
COUT4 LED8 Pin_W13
Two
COUT5 LED7 Pin_W14
multiplication
COUT6 LED6 Pin_V11
result output
COUT7 LED5 Pin_Y13
COUT8 LED4 Pin_Y10
COUT9 LED3 Pin_W10
COUT10 LED2 Pin_W8
COUT11 LED1 Pin_V10
7. By downloading via JTAG programmer sof the corresponding file is
loaded into the FPGA. Observed experimental results are consistent with
their programs.
the target cell, the digital signal is selected as the clock source module 1KHz, toggle
the appropriate DIP switch, enter a four-element multiplier and multiplicand,
displays the result of multiplying the two values of binary digits in the LED lamp.

1. Give different multiplier and multiplicand, painted analog
waveform, and illustrated.
57
2. Design a 8-bits parallel multiplier on the basis of this
program.
3. On the basis of this program, and with the 7-Seg LED to show
the result is multiplied by a decimal value.
4. Experiment Theorem, the design process, compile and analyze
the results of the analog waveform hardware and test
results recorded.
58
Experiment 9 4-Bits Full adder Design
I、 Experiment Object
1、 To understand the basis of Four-Bits full adder.
2、 Master the basic combinational logic circuits FPGA.
3、 Be proficient in Quartus II for FPGA development.

The full adder is composed of two addends Xi and Yi, and to lower the
carry Ci-1 as input, and generates the high-Si-based, and the logic circuit
into the bit Ci. It is not only to complete the standard binary sum of Xi
and Yi, but also take into account the lower one into the bit Ci-1 logic.
For input Xi, Yi, and Ci-1, for the case of Si and Ci output, you can get
full adder according to the law of the binary adder truth table as shown
in Table 9-1:
Xi Yi Ci-1 Si Ci
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 0 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 9-1 Full Adder Tuth Table
Obtained from the truth table after Si and Ci logical expressions through
simplified as:
59
This is just one-bit binary full adder, to complete a four-bits binary full adder, just
put four bytes can be linked together.

In this study, to complete the task is to design a four bit binary full adder. Specific
experimental procedure is to use the DIP switch module K1 ~ K4 as an addend X input,
K7 ~ K10 as another addend Y input on the experimental system, with LED module
LED1 ~ LED12 output as a result of S, LED light indicates output '1 ', LED off means
output '0'.
Experimental tank DIP switch, LED and FPGA interface circuits, and DIP
switch, LED and FPGA pin connections in previous experiments have done a
detailed description, not repeat them here.
IV. Experiment Step

1. Open QUARTUSII software, and create a new project.
2. After completing construction projects, then create a VHDL File,
Open VHDL Editor dialog box.
3. Follow Experiment Theorem and their ideas in writing VHDL VHDL program
edit window, the user can refer to the example provided in the program CD.
4. After you have written VHDL program storage. Approach with the
experimental one.
5. For I have written and compiled VHDL simulation program, modify the
program for errors.
6. Compiled simulation is correct, according to several sources, DIP switch, LED
lights and FPGA pin connection table or reference in Appendix Pin
60

X0 DIP Switch K4 Pin_V3
X1 DIP Switch K3 Pin_U7
Addend data
X2 DIP Switch K2 Pin_Y4
X3 DIP Switch K1 Pin_W6
Y0 DIP Switch K8 Pin_V6
Y1 DIP Switch K7 Pin_R5
Addend data
m_Result0 LED12 Pin_Y6
m_Result2 LED10 Pin_W7
Adding the
results of two
m_Result6 LED6 Pin_V11
summand output
m_Result11 LED1 Pin_V10
7. by downloading via JTAG programmer sof the corresponding file is loaded into
the FPGA. Observed experimental results are consistent with their programs.
61
the target cell, toggle the appropriate DIP switch, enter two four per addend, then
displays the results in the sum of these two values on the LED lights binary digits.

1. Draw different addends, painted analog waveform, and for
illustration.
2. Design an 8-bits full adder.
3. With 7-Seg LED to show the results of multiplying the decimal value.
4. Experiment Theorem, the design process, compile and analyze the
62
Experiment 10 Design of Controllable Pulse Generator
1、 To understand the principle controllable pulse generator.
2、 To observe the FPGA signal with an oscilloscope。
3、 To write the Complex function code by using VHDL.

Pulse generator is to generate a pulse waveform, and pulse generator is controlled
to produce a variable duty cycle and pulse waveform. The principle controllable pulse
generator is relatively simple and can be simply understood as a counter input clock
signal dividing process. By changing the upper limit value of the counter to the
purpose of changing the cycle by changing the potential of the inverted threshold value
to achieve the purpose of changing the duty cycle. Here Here is a simple example to
illustrate how it works.
f there is a counter clock frequency T, the count range from 0 ~ N, the other to
take a
M (0 ≤ M ≤ N), if the output Q, as long as the condition is satisfied then the Q, by
changing the value of N can change the period of the output pulse; changing the value M,
to change the duty cycle of the pulse wave.
1 0T  M
Q
0 M T  N
And duty cycle so that the output pulse wave, respectively:

周期  ( N  1)TCLOCK
M
占空比   100 %
N 1
Period of this experiment task is to design a controllable pulse generator, the
required output and duty cycle pulse wave can be changed. Specific experiment, the
63
clock signal selection of 1MHz clock clock module, and then use the keys S1 and S7
modules to control the cycle of the pulse wave, every press S1, N will continue to
increment at a slow clocked 1 press S7, N constantly diminishing role in the slow clock
1; using S2 and S8 to control the duty cycle of the pulse wave, every press S2, M will
continue to increment in the role of a slow clock, each press S8, M will continue to
decrement a role in the slow clock, S12 is used as a reset signal when you press the
S12, the reset pulse generator inside the FPGA module. The output pulse output
directly to the observed experimental box probe module to change the output with an
oscilloscope waveform.
IV. Experiment Step

1、 open QUARTUSII software, and create a new project.
2、 Then create a VHDL File, Open VHDL Editor dialog box.
program edit window, the user can refer to the example provided in the program CD.
4、 after finish writing VHDL program storage. Approach with the experimental one.
5、 for I have written to compile and simulate VHDL program, modify the program
for errors.
6、 compiled simulation is correct, according to the DIP switch, LED and FPGA pin
connection table (Table 1-1, Table 1-2) or a reference in Appendix Pin assignment.
Table 10-1 is an example of the program's Pin assignment table. After the assignment
is complete, and then compile a whole, so Pin assignment to take effect.
CLK Digital signal Pin_T2 Clock is 1MHz

NU Key switch S1 Frequency Control /
Pin_B12
increase
64
ND Key switch S7 Frequency control /
Pin_A12
reduce
MU Key switch S2 Duty cycle control /
Pin_B11
increase
MD Key switch S8 Duty cycle control /

Pin_A11
reduce
RST Key switch S12 Pin_T1 Reset Control
FOUT Output observation Oscilloscope

Pin_N5
module observation point
Table 10--1 Pin assignment
7、 , with the corresponding burner download sof file is loaded into the FPGA via
V. Experimental Results and Phenomena

source module 1MHz, press the button switch module S12 keys may observation
by observation module output to an oscilloscope a frequency of
approximately 1KHz, 50% duty cycle rectangular wave. S7 S1 key or key is
pressed, the frequency of this square wave will be a corresponding increase
or decrease occurs. S8 S2 key or key is pressed, the rectangular wave duty
cycle will increase or decrease accordingly.

1、 Draw an analog waveform and illustrate.
2、 based on the re-design of the experiment, when the frequency is
changed so that the program does not affect the duty cycle changes.
65
66
Experiment 11 Flip-Flop Design
1. To understand the basic trigger works.
2. To be more familiar with the Quartus II design flow based on circuit diagram.

he basic flip-flop circuit as shown in Figure 11-1. It consists of two cross-coupled
anti-and gates can also be cross-coupled gates by two trans or composition. Now to the
basic flip-flop consisting of two counter and gate.

A A
S 1 R 2
3 Q 1 Q
2 3
B B
4 5
6 Q 4 Q
R 5 S 6
Fig 11-1 Basic flip-flop circuit
For example, to analyze how it works. According to the relationship with the
non-logical, you can get the state triggers the transfer of basic and simplified truth table
truth table, as shown in Table 11-1:
State transition truth table Simplify the truth table
R S Qn Q n1 R S Q n1
0 1 0 0 0 1 0
0 1 1 0 1 0 1
1 0 0 1 1 1 Qn
1 0 1 1 0 0 NC
1 1 0 0
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1 1 1 1
0 0 0 NC
0 0 1 NC
Table 11-1 Basic trigger state transition truth table
According to the truth table, it is easy to write its characteristic equation:
Wherein formula (2) as the constraint condition。
The experimental task is to use schematic entry Quartus II software, resulting in a
basic flip-flop, flip-flop can be in the form of anti-and gate structures, but also can
counter or gate structure. K1 and K3 experiments used to denote key module R and S,
respectively, Q and with LED12 LED modules and LED1. In the case of R and S
satisfy Formula (2), the Q and observed changes.
Experimental tank DIP switch, LED and FPGA interface circuits, and DIP
switch, LED and FPGA pin connections in previous experiments have done a
detailed description, not repeat them here.
IV.Experiment Step
1. Open QUARTUSII software, create a new project.
2. Built after the completion of a project to create a new graphic
element input file, open the graphic elements Editor dialog box.
3. Follow Experiment Theorem and their ideas in writing graphic design
program elements editing window, the user can refer to the example
provided in the program CD.
4. Circuit design is good design program, the saved. Approach with the
experimental one.
5. For I have written a program designed to compile and simulate the circuit for
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programming errors to be modified.
6. Compiled simulation is correct, according to the DIP switch, LED and
FPGA pin connection table or reference in Appendix Pin assignment. Table
11-2 is an example of the program's Pin assignment table. After the
effect.

NR DIP Switch K1 Pin_W6
NS DIP Switch K2 Pin_AA11
Q LED12 Pin_Y6
NQ LED1 Pin_V10
7. By downloading via JTAG programmer sof the corresponding file is loaded
into the FPGA. Observed experimental results are consistent with their
programs.
V.Experiment Result
the target cell, toggle the appropriate DIP switch (ie, R, S), then through the bright
LED lights on and off to show the results of the trigger input. The input and output,
and Table 8-1 basic trigger state transition truth table compares watch are the same.

2、 Draw different R, S analog waveform values and illustrate.
3、 try to design a trigger other functions such as D flip-flop, JK
flip-flop.
69
Application of the Experimental Section
Experiment 12 Matrix Keyboard Display Circuit Design
1、 to understand ordinary 4 × 4 keyboard scanning principle
2、 to further deepen our understanding of 7-Seg LED display process.
3、 the understanding of the input / output ports defined methods.

Realization keyboard has two options: First, using some of the existing chip to
realize the keyboard scan; Then use the software to realize the keyboard scan. As an
embedded system designers will always be concerned about the cost of the product.
There are a lot of chips can be used for keyboard scanning, but the software keyboard
scanning method helps reduce duplication of development costs of a system, and
requires very little CPU resources. Feature embedded controller, and can take
advantage of this resource, here to introduce software implementations keyboard
control.
Fig12-1 Simple keyboard circuit
A keyboard is commonly used in a transient contact switch, and with a simple
circuit shown in Figure 10-1, the microprocessor can be easily detected off. When the
switch is open, through a pull-up resistor processor I / O logic 1 on offer; When the
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switch is turned off, the processor / IO input will be pulled down to get a logic 0. May
Unfortunately, the switch is not perfect, because when they are pressed or released, is
not able to produce a clear 1 or 0. Although the contact points may appear stable and
quickly closed, but with a fast microprocessor execution speed, this action is relatively
slow. When the contact closes, it bounced like a ball. As shown in the pop-up effect
will produce several of Fig12-2 pulse. The duration of the bounce is usually
maintained between 5ms ~ 30ms. If you need more keys, each switch can be connected
to the microprocessor input port of its own. However, when increasing the number of
switches, this method will soon use up all the input ports.
Fig12-2 Key jitter
The most effective way switch array keyboard (or more if needed key 5) is
formed as shown in Fig12-3 a two-dimensional matrix. When the number of rows and
columns, like a long time, which is a square matrix, will produce an optimal way the
cloth out (I / O terminal is connected to the time). A transient contact switch (button)
placed at each intersection of a row and column lines.
Fig12-3 Matrix keyboard
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The number of keys required matrix obviously varies depending on the
application. Each line consists of a driver of an output port, and each column of a
resistor pull and supply an input port.
Keyboard scan implementation process is as follows: For the 4 × 4
keyboard, usually connected to four rows, four, so to identify the key only
needs to know which rows and columns which can, in order to complete the
identification process, the idea is , the first four fixed output high level
behavior, as the low potential and the output 4, the output value is read
in four rows, the high potential would typically be pulled low, if the read
line 4 into a high potential are then definitely no button is pressed,
otherwise, if there is to read four lines into a low potential, then the
corresponding line certainly has a button is pressed, so that we can get
to the line value keys. Similarly, access column values, too, the first
output 4 as high potential, then the behavior of low potential output 4,
read into the column values, what if there was a low potential, then
certainly there is the row corresponding button press next.
Get to the row and column values in the future, a combination of an
8-bit data, depending on the implementation of different encoding then
matched to each button, find the key after displaying the 7-Seg LED.

The experiment required to complete the task is achieved through the program by
pressing keys on the 4X4 matrix keyboard keys to read and complete certain functions
(such as mobile, etc.) in the 7-Seg LED to display. By definition of the keyboard,
press the "*" key in the 7-Seg LED is a display "E" key. Press the "#" key to display
the "F" key on the 7-Seg LED. Other key press on the keyboard to display logo.
In this experiment 7-Seg LED circuit and connecting with FPGA pin connections
72
in previous experiments have done a detailed description, not repeat them here. 4X4
matrix circuit schematic of the experimental box on the keyboard as shown in Fig12-4.
Connection as shown in Table 12-1 and FPGA pin.
Fig12-4 4X4 Matrix keyboard circuit schematics

KEY_R[0] Pin_W15 JP3_75 Keypad row[0]
KEY_R[1] Pin_V14 JP3_76 Keypad row[1]
KEY_R[2] Pin_U10 JP2_3 Keypad row[2]
KEY_R[3] Pin_U11 JP2_4 Keypad row[3]
KEY_C[0] Pin_U16 JP3_79 Keypad col[0]
KEY_C[1] Pin_V15 JP3_77 Keypad col[1]
KEY_C[2] Pin_Y17 JP3_80 Keypad col[2]
KEY_C[3] Pin_V16 JP3_78 Keypad col[3]
Table12-1 4X4 Matrix key FPGA-pin connector and Table
IV. Experiment Step

1、 Open QUARTUSII software and create a new project.
2、 After the completion of the construction project, and then
create a VHDL File, Open VHDL Editor dialog box.
3、 According to Experiment Theorem and their ideas in writing VHDL
VHDL program edit window, the user can refer to the example provided in
73
the program CD.
4、 After finish writing VHDL program storage. Approach with the
experimental one.
6、 Compiled simulation is correct, in accordance with the 4X4 matrix key,
7-Seg LED with the FPGA pin connection table (table or reference in
Appendix Pin assignment. Table12-2 is an example of the program's Pin
assignment table after the assignment is completed, then the whole
compile time, so Pin assignment to take effect.
KR0 4*4 Keyboard R0 Pin_W15
KR1 4*4 Keyboard R1 Pin_V14

LINE signal
KR2 4*4 Keyboard R2 Pin_U10
KR3 4*4 Keyboard R3 Pin_U11
KC0 4*4 Keyboard C0 Pin_U16
KC1 4*4 Keyboard C1 Pin_V15

ROW signal
KC2 4*4 Keyboard C2 Pin_Y17
KC3 4*4 Keyboard C3 Pin_V16
A 7-Seg LED module A Pin_H15
B 7-Seg LED module B Pin_H14
C 7-Seg LED module C Pin_H16

Key Display
D 7-Seg LED module D Pin_N16
E 7-Seg LED module E Pin_P16
F 7-Seg LED module F Pin_R15
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G 7-Seg LED module G Pin_R14
DP 7-Seg LED module DP Pin_T13
7-Seg LED module

SA Pin_N17
SEL0
7-Seg LED module

SB Pin_P17
SEL1
7-Seg LED module

SC Pin_R16
SEL2
Table12-2 Pin assignment
7、 With the corresponding burner download sof file is loaded into the FPGA
via JTAG. Observed experimental results are consistent with their
programs.

is loaded into the target cell, the digital signal is selected as the
clock source module 1KHz, press one key matrix keyboard, the display
corresponds to this in the 7-Seg LED identification of key key, when
pressed again before the second key when a key value in the 7-Seg LED
left. Press "*" key in the 7-Seg LED is displayed "E" key. Press the "#"
key to display the "F" key on the 7-Seg LED.

1、 7-Seg LED analog waveform plotted when different keys, and for
illustration.
2、 Look for there is no other way of scanning the keyboard display.
And draw a flow chart.
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76
Experiment 13 16x16 Matrix LED Experiment
1、 For dot matrix character generator and 16 * 16 dot matrix display
working principle and the principle of the system.
2、 To strengthen the bus generated addresses positioning CPLD achieve
understanding methods.
3、 The master calls the use of the ROM in the FPGA.
This experiment is completed Chinese characters displayed on the LED,
16 * 16 LED dot matrix scanning works similar to the 8 bit scanning 7-Seg
LED, and display the results just not the same. Here's the principle of
the experimental system of the workpiece 16 * 16 dot matrix do some simple
instructions.
16 * 16 dot matrix LED 256 thus formed through the combination of a
permutation matrix LED array 16 rows * 16, commonly known as 16 * 16 dot
matrix. A single LED circuit as shown in Figure 13-1:
Fig 13-1 Single LED circuit diagrams
From the above chart we can see that when the circuit diagram of a single LED Rn
enter a high potential, while Cn input is a low potential to form a loop circuit, LED light.
That is the point corresponding LED dot is lit. 16 * 16 dot matrix is composed of 16 rows
and 16 of the LED, in which all 16 LED's Rn parallel with the end of each line, Cn all 16
LED's in parallel with the end of each column. Rn through to enter a high potential, it is
equivalent to the list of all the LED entered a high potential, then as long as a low-end entry
Cn certain LED's potential, the corresponding LED will be lit. Specific circuit as shown in
Figure 13-2:
77
Fig 13-2 16 * 16 matrix circuit schematics
There must be displayed on the dot matrix character is based on the point of his
character dot matrix display light off as shown in Figure 13-3 expressed:
Fig 13-3 Characters displayed on the matrix
n the figure above, the display is a "Chinese" word, as long as the
bit will be "Chinese" character of the area covered by bright, will appear
in the lattice of a "Chinese" word. We introduce the principle matrix
according to the previous display. When we select the first column, the
first column according to the characters displayed in the corresponding
point needs to be lit Rn is set to a high level, then the first column will
need to be illuminated is illuminated points . And so on, the display of
the second row, third column of the N columns ...... points need to be lit.
Interval point and then according to the visual principles of the human
eye, each column will be set to display a certain value, then we will feel
a complete display flicker characters. You can also follow this principle
to display additional characters. Under Fig 11 - 4 is a display of Chinese
78
characters required timing diagram:
Fig 13-4 Shows the timing diagram
In the figure above, the role of the clock in the system, first select
one of the columns, the columns of data entry so that the LED display its
data (when the LED light is high potential, otherwise not shine). Then
select the next column to display the data of the next column. When finished
after a 16 * 16 dot matrix data entry, select that column count to the last
column, and then began to enter the same data from the first column. So
long as the first row of data shows the first and second display time of
the first row of data is short enough, then the human eye will see the first
row of data is always displayed without pause phenomenon. The same is true
of other columns, 漢 , until the next characters.
In the actual use of them, a Chinese character is composed of multiple
octets of data to form, then you want to display multiple characters, these
data can be stored in accordance with certain rules into memory, when the
characters to be displayed when As long as the corresponding data in memory
to remove the display. The experimental sample program in order to display
a "Welcome embedded SOC development system." Small amount of data, so do
not put the memory, but in the program directly into a 16-bit data
corresponding. The sample program shown in the following diagram format
font file data 13-5：
79
Fig 13-5 Font file format

The experiment required to complete the task is to achieve 16X16 dot matrix
control through the program. Achieve repeat "Welcome embedded SOC development
system," these characters and characters.
6 * 16 dot matrix circuit principle has already been done in the detailed
description, in this experiment, 16 * 16 dot matrix of four 8 * 8 dot matrix, taking
into account the relationship between the LED current power and current
consumption of FPGA adding the drive circuit in the experimental circuit. Specific
circuit as shown in Figure 13-6. Connection as shown in Table 13-1 and FPGA pin.
Fig 13-6 16*16 Dot Diagram
80
DOT_R[0] Pin_T16 JP2_28
DOT_R[1] Pin_R17 JP2_27
DOT_R[4] Pin_M7 JP1_32
DOT_R[5] Pin_G11 JP2_23
Dot array Row
DOT_R[9] Pin_T10 JP2_11 Data
DOT_R[10] Pin_U15 JP2_10

DOT_R[14] Pin_V13 JP2_6
DOT_R[15] Pin_V12 JP2_5

DOT_C0 Pin_V8 JP3_35
DOT_C1 Pin_U9 JP3_34
Select Col
DOT_C2 Pin_U8 JP3_33
DOT_C3 Pin_T9 JP3_32
Table 13-1 16X16 Matrix and FPGA Pin
IV. Experiment Step

1、 open QUARTUSII software and create a new project.
program edit window, the user can refer to the example provided in the program CD.
Schematic entire experiment as shown in Figure 13-7:
4、
81
Fig 13-7 16*16 matrix display circuit block diagram
5、 After finish writing VHDL program storage. Approach with the experimental
one.
6、 for I have written to compile and simulate VHDL program, modify the program
for errors.
7、 compiled simulation is correct, according to the lattice, the clock and the FPGA
pin connections or reference table in Appendix Pin assignment. Table 13-2 is a
sample program in the experimental system Pin assignment table. After the
assignment is complete, and then compile a whole, so Pin assignment to take effect.
CLK Digital signal Pin_A14 Clock is 1KHz
KEYC0-C3 16*16 Matrix Table 13-1 Matrix C0-C4 Port
KEYR0-R15 16*16 Matrix Table 13-1 Matrix R0-R15 Port

source module 1KHz, followed by the dot matrix display module loop "Welcome
to SOC development of embedded systems," each character display is about
0.5 seconds. Time last displayed about 2 seconds, then reappears, "Welcome
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to the SOC development of embedded systems."

1、 On the basis of this program try to write other characters font file and displayed
on the dot.
2、 Thinking how to make the Chinese characters rotate and move around.
3、 Dry to take advantage of the FPGA ROM font file into the ROM, and then
write the program in the form of re-call.
4、 Draw analog waveforms and explain.
83
Experiment 14 DC Motor Speed Test
1、 The master works of DC motor.
2、 Understand the working principle and usage of Hall Switch Sensor.
3、 The principle of the motor speed.

DC motors are commonly used in our daily living. Its internal structure shown
in Figure 14-1:
Fig 14-1 DC Motor Structure
On the diagram to illustrate the working principle of a DC motor. The DC
power supply is turned on through the brushes of the armature winding, the armature
current flowing through the conductors, due to electromagnetic action, so that the
armature conductor will generate a magnetic field. While the magnetic field and the
magnetic field generated by the main magnetic pole generates electromagnetic force,
the electromagnetic force for the rotor, the rotor starts to rotate at a constant speed.
84
Such motors began to work.
To the motor can be measured in a unit of time the number of cycles
of rotation of the rotor, we added a Hall switching original (44E) in
the external circuit of the motor while the rotor wheel electronics
enables adding a Hall Seoul original output generated magnetic field with
magnetic steel sheets. When the motor rotates, the rotary drive plate
rotate together with the magnet when the magnet is rotated to the top
sheet of the Hall element, the output of the Hall element can lead to
a high potential to low potential. When the magnet piece turned Hall above
components, the output of the Hall element resumed high-level output.
Such motor rotates every week, then the output of the Hall element will
generate a low pulse, we can detect by the number of components per unit
time Neihuo Er low pulse output of a DC motor to calculate the speed of
the unit time. DC motors and circuit switching circuit diagram Hall
element as shown in Figure 14-2:
Fig 14-2 DC motor, the Hall element circuit diagram
85
Usually refers to the motor speed of the motor rotation speed per minute, is in
units of rpm, the actual measuring procedure in order to reduce the speed of the
refresh time, typically 5 to 10 seconds are refreshed. If refreshed once every 6
seconds, then the equivalent of only records the number of revolutions of the motor
within 6 seconds of the recorded data that is multiplied by 10 to get a one-minute
speed. Finally, this information will be displayed on the 7-Seg LED.
Finally, because the data is displayed in the data multiplied by 10, which is
followed by a bit of information will add an element to be a bit then, this one will
always be 0. Such as: 45 * 10 becomes 450, that is, the "45" after the addition of a
bit "0." It can be seen, the error of the motor rotation speed is less than 20. To make
the information can be displayed stable at 7-Seg LED, the output of this information
when adding a 16-bit latch, the latch data to the 7-Seg LED to display, so that it will
because in the counting process, the data changes resulting 7-Seg LED to display
constantly changing.

The experiment required to complete the task is achieved through the program
reads the motor rpm, and displayed on the 7-Seg LED. It reads the data and display
data timing relationships are shown in Fig 14-3:
Fig 14-3 Experimental control signal timing diagram
86
In this experiment 7-Seg LED circuit and connecting with FPGA pin connections
in previous experiments have done a detailed description, not repeat them here. DC
motors and circuit schematic of the Hall element, such as Fig 14-2 shows. Connection
as shown in Table 14-1 and FPGA pin.
Signal Name FPGA IO 名 Explanation
PWM signal input to the DC

MT-PWM Pin_F1
motor
Hall element output to the

MT-SPEED Pin_G3
FPGA
Table 14-1 DC motor, the Hall element and the FPGA pin connection table
IV. Experiment Step

1、 Open QUARTUSII software and create a new project.
3、 According to Experiment Theorem and their ideas in writing VHDL VHDL
program edit window, the user can refer to the example provided in the
program CD. Providing a total of four sample program VHDL source code.
Every one of the original program to complete certain functions. The
specific features are as follows Table 14-2:
File Name Functions
Generating a control signal frequency measurement in the role

TELTCL.VHD
of the clock.
CNT10.VHD Decimal counter. 4 used in the experiment to count
16-bit latch, the latch control signal in effect, the count value
SEG32B.VHD
latched
DISPLAY.VHDL Show decodes the information displayed latch.
Table 14-2 Sample program menu
87
4、 after finish writing VHDL program storage. Approach with the
experimental one.
5、 To compile and generate VHDL module component files. To error and
modify the program, and ultimately all programs produced by the compiler
module component files. Please refer to the specific method of experiment
VI.
6、 create a graphics file editor, modular component file into which would have
been generated, and pick up on request edges. Upon completion, as shown
in Fig 14-4:
Fig 14-4 Edited graphic design files
7、 To compile simulation, and error to modify the program, and ultimately
through the compilation.
8、 After compiling simulation is correct, according to the DC motor, the Hall
element, 7-Seg LED with the FPGA pin connections table or reference in
Appendix Pin assignment. Table 14-3 is an example of the program's Pin
assignment table. After the assignment is complete, and then compile a
88
whole, so Pin assignment to take effect.

MOTOR DC Motor module Pin_G3 44E Pulse output

Motor Speed
Display
SEL0 CS DEL0 Pin_N17
SEL1 CS DEL1 Pin_P17
SEL2 CS DEL2 Pin_R16
9、 with the corresponding burner download sof file is loaded into the FPGA
via JTAG. Observed experimental results are consistent with their program.

is loaded into the target cell, the digital signal is selected as the
clock source module 1MHz, the DC motor module mode selector to GND mode,
change the speed of rotation of the potentiometer, so DC motor starts
to rotate, this time in a certain period of time, 7-Seg LED will display
the rpm of the motor current at this time. Slowly increase by reducing
the rate of rotation of the potentiometer or a DC motor, in which case
89
the value of 7-Seg LED will be a corresponding increase or decrease.

1、 To draw analog waveform, and for illustration.
2、 The results of the experimental program will try to write accurate
to bits.
90
Experiment 15 Stepper Motor Drive Control
1. Understand the working principles of the stepper motor.
2. Master timing generated by FPGA drive a stepper motor.
3. To control the stepper motor rotates the entire process with FPGA.

Stepper motor control device is commonly used in industrial control and
instrumentation, such mechanical means can accurately control the rotation angle of
the mechanical device, the moving distance and the like. You can also use a stepper
motor driven screw potentiometer to adjust the voltage or power, in order to achieve
control of the executive machinery. Stepper motor can be driven directly with a digital
signal, very convenient to use. Stepper motor also has a quick start, stop, and
positioning precision stepper characteristics, which are widely used in CNC machine
tools, plotters, printers, and optical instruments.
Stepper motor is actually a data / angle converter, three-phase stepper motor
principle structure as shown in Fig 15-1:
Fig 15-1 Schematic diagram of the 3-phase Stepper motor
As can be seen from the figure, the stator of the motor has six poles aliquots, A, A
', B, B', C, C ', the angle between two adjacent magnetic poles is 60 °, two opposite
form a group of magnetic poles (A-A ', B-B', C-C '), when a current through the
91
windings, the windings of the respective two poles N and S poles are formed on each
magnetic pole have five small rectangular teeth are distributed, there is a small
rectangular teeth 40 uniformly distributed around the circumference between two
adjacent teeth on the rotor angle of the motor 9 °.

⑴ When a phase winding is energized, a magnetic field is generated
corresponding to the magnetic poles, and with a certain angle of rotation of the rotor,
the rotor and stator teeth are mutually aligned. Thus, the wrong tooth is to promote the
stepper motor rotation causes.

For example, in a three-phase three-shot control mode, if the A-phase electricity,
B, C phase is not energized, the magnetic field in the rotor and the stator teeth of phase
A tooth alignment, we as the initial state. A centerline of the magnetic pole provided
with teeth of the aligned rotor teeth number 0, the A-phase and B-phase magnetic poles
away not an integer multiple of 9 °, with 120 ° (120 ÷ 9 = 13 2/3), so in this case the
rotor tooth There are no B-phase stator teeth corresponding to only a small number of
teeth near the centerline 13 of the B-phase poles, away from the center line 3 °, then
suddenly changed if the B-phase power, A, C phase is not energized, the B phase
forcing the 13th pole rotor teeth are aligned with the rotor rotates 3 °, so that the motor
rotor step. If in accordance with A-AB-B-BC-C-CA-A compared to the forward power

order. Usually took the ring pulse distributor generates three-phase six-step pulse.
⑵Running speed control. If you change the width of the ABC three-phase
windings h8 potential, it will lead to power-on and power-off change in the rate of
change, so that the motor speed change, so adjust the pulse cycle operation speed can
be controlled stepper motor.
⑶Rotation angle control. Because the input pulse to the stepping motor of a CP
state changes a phase winding, and a corresponding rotation angle, the rotation angle
of the stepping motor is determined by the number of input pulses CP.

The experimental box used for the 4-phase stepper motor stepper motor, the
minimum rotation angle of 1.8 degrees, the forward rotation of the control sequence is
92
as follows, each pulse control their turn 1.8 degrees.
Reverse rotation control sequence is as follows:

The experiment is designed to complete the task stepper motor control circuit.
Through a DIP Switch K1 to control clockwise and counterclockwise rotation of the
stepping motor; through 8 key switches S1-S8 to control the rotation angle of the
stepping motor.
n this experiment, several modules used in signal source module, the
module DIP switch, key switch, stepper motor modules. Which digital
signal source, thumbwheel switch, key switch and the FPGA pin connector
to connect the circuit and in previous experiments have done a detailed
description, not repeat them here. Stepper motor module experimental
platform located in the upper left, and its working status through a
jumper to choose. The control circuit shown in Fig 15-2 below. With the
FPGA pin connections as shown in Table 15-1.
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Fig 15-2 Stepper motor Driver Schematic
STEP_A Pin_H2 JP1_6
STEP_B Pin_H1 JP1_5
STEP_C Pin_J2 JP1_4
STEP_D Pin_J1 JP1_3
Table 15-1 Stepper motor module Interface with the FPGA pin connection table
IV. Experiment Step

1、 Open QUARTUSII software and reate a new project.
2、 then create a VHDL File and open VHDL Editor dialog box.
3、 The user can refer to the example provided in the program CD and write
VHDL program.
4、 After finish writing VHDL program, to store it. Approach with the
experimental one.
5、 Simulate and modify the program, and then compile.
6、 If compiled simulation is correct, according to the stepper motor, button, DIP
switch and the FPGA pin connections or reference table in Appendix Pin
94
CLK Digital Clock Access 1KHz

Pin_T2
Module clock
KEYORDER DIP Switch K1 Clockwise/

Pin_W6
Clockwise Control
ASTEP Stepper motor A Pin_H2
BSTEP Stepper motor B Pin_H1 Stepper motor
CSTEP Stepper motor C Pin_J2 Control signal
DSTEP Stepper motor D Pin_J1
Key7_5 Key switch S1 Pin_B12
Key15 Key switch S2 Pin_B11
Key30 Key switch S3 Pin_V4
Key45 Key switch S4 Pin_T4 Rotation angle
Key90 Key switch S5 Pin_P3 control
Key180 Key switch S6 Pin_AB11
Key360 Key switch S7 Pin_A12
Key8 Key switch S8 Pin_A11

In reference to the example design, for example, when the file is
loaded into the target component design, digital clock selection 1KHz,
95
press Key switch S1-S8, Stepper motor will rotate in accordance with the
corresponding step angle programming. Slide the DIP switch K1, Stepper
motor rotation direction change will occur.

1、 To draw analog waveform and illustrate.
96
Experiment 16 PS2 Keyboard and Display Interface
Experiment
1、To learn simple communication protocol with FPGA design methods.
2、Learning PS2 works, scan code ASCII code conversion.
3、Learn some VHDL coding tips.
II、 Experiment Theorem

PS2 is a two-way communication protocol synchronous serial
communication protocol. Both ends of the communication through the CLOCK
(clock signal terminal) to synchronize and exchange data via DATA (data port). If
you want to suppress any party to the other party's communication, just put CLOCK
pulled low.
PS2 standards and specifications of each data transmission contains the start bit
(start bit), scan code (scan code), odd parity (odd parity), and the termination bit
(stop bit) a total of 11 bit, and two-way serial data transmission mode, to achieve the
purpose of communication. And when the host (host) or not transferred from the
machine side (slave) or receiving data, the data transfer port, and both will be
exalted frequency potential. Figure 16-1 shows the contents of each packet of data
are the following:
1. start site (“0”)
2. 8-bits data width scan code.
3. odd parity, the scan code and add up the number 1 odd parity is odd.
4. Termination bit (“1”)
97
Fig 16-1 PS2 Serial transmission standards
6-pin Mini-DIN (PS2):

Male Female
1 - Data
2 - Not Implemented
3 - Ground
4 - Vcc (+5V)
5 - Clock
(Plug) (Socket)
6 - Not Implemented
Fig 16-2 PS2 Port Pin Assignment
PS2 control interface to use only two ports, one for the frequency of the port,
the other is the data port as shown in Fig 16-2, and this will be for the tri-state
transfer port (Tri-State) and has a two-way (bidirectional) feature. On PS2
transmission products, common to mouse and keyboard, the driving principle of
both are the same, only the scan code (scan code) is different. So we PS2 keyboard
as an example.
The keyboard is actually a large key matrix, which by the processor
mounted on a circuit board (called "Keyboard Encoder") to monitor the.
Although different keyboard may use different processors, but they are
the same task, namely to monitor what the button is pressed, which keys
are released, and sends this information to the host. If necessary, the
processor handles all to shake, and its 16-byte buffer of data in the
buffer. Host contains a "keyboard controller" and the keyboard processor
communication and the processor decodes the information from the keyboard,
the keys corresponding to the current system and high-speed processing
98
of matter. Communication between the host and the keyboard still using
IBM's agreement.
Keyboard processor spends a lot of time to scan or monitor key matrix.
If you find a button is pressed, or a long press release, the keyboard
sends a "scan code" information to the host. Scan codes are two different
types: "Pass Code" and "break the code." When a key is pressed or long
press time, the keyboard sends a pass code; when a key is released, the
keyboard sends the broken code. Each keyboard is assigned a unique code
and break through the code, so to find a host through a unique scan code
can determine which key is pressed or released. Each key code composed
of a set-off of the "scan code set", and now all the keyboard scan codes
are used second. Since there is no one simple formula to calculate the
scan code, so you know a particular key pass code and break codes, can
be obtained using the look-up table approach. Special attention is needed,
through the key code value represents a key on the keyboard, it does not
mean that the characters printed on the keys, which means there is no
correlation between the pass code and ASCII code.
In addition, the second pass code is only one byte wide, but there
are a few "expand button" pass code is a set of two-or four-byte wide,
the first byte is always such a code 0xE0 . The pass code, each button
when released, the keyboard sends a broken code. Each key also has its
own unique code breaking, but fortunately, there is a definite link
between the broken code and break codes. Most of the second set breaking
yards have two words long, their first byte is 0xF0, the second byte is
the corresponding key pass code. Expansion keys breaking yards are
usually three bytes, the first two bytes 0xE0 and 0xF0, the last byte
99
is the last byte of the key pass code. Table 16-1 lists the keyboard pass
code and break codes.
Breaking Breaking Breaking

Key Pass code Key Pass code Key Pass code
scode scode scode
A 1C F0,1C 9 46 F0,46 [ 54 F0,54
B 32 F0,32 ` 0E F0,0E INSERT 67 F0,67
C 21 F0,21 - 4E F0,4E HOME 6E F0,6E
D 23 F0,23 = 55 F0,55 PG UP 6F F0,6F
E 24 F0,24 \ 5C F0,5C DELETE 64 F0,64
F 2B F0,2B BKSP 66 F0,66 END 65 F0,65
G 34 F0,34 SPACE 29 F0,29 PG DN 6D F0,6D
U
H 33 F0,33 TAB 0D F0,0D 63 F0,63
ARROW
I 43 F0,48 CAPS 14 F0,14 L ARROW 61 F0,61
D
J 3B F0,3B L SHFT 12 F0,12 60 F0,60
ARROW
R
K 42 F0,42 L CTRL 11 F0,11 6A F0,6A
ARROW
L 4B F0,4B L WIN 8B F0,8B NUM 76 F0,76
M 3A F0,3A L ALT 19 F0,19 KP / 4A F0,4A
N 31 F0,31 R SHFT 59 F0,59 KP * 7E F0,7E
O 44 F0,44 R CTRL 58 F0,58 KP - 4E F0,4E
P 4D F0,4D R WIN 8C F0,8C KP + 7C F0,7C
Q 15 F0,15 R ALT 39 F0,39 KP EN 79 F0,79
R 2D F0,2D APPS 8D F0,8D KP . 71 F0,71
S 1B F0,1B ENTER 5A F0,5A KP 0 70 F0,70
T 2C F0,2C ESC 08 F0,08 KP 1 69 F0,69
U 3C F0,3C F1 07 F0,07 KP 2 72 F0,72
V 2A F0,2A F2 0F F0,0F KP 3 7A F0,7A
W 1D F0,1D F3 17 F0,17 KP 4 6B F0,6B
X 22 F0,22 F4 1F F0,1F KP 5 73 F0,73
100
Y 35 F0,35 F5 27 F0,27 KP 6 74 F0,74
Z 1A F0,1A F6 2F F0,2F KP 7 6C F0,6C
0 45 F0,45 F7 37 F0,37 KP 8 75 F0,75
1 16 F0,16 F8 3F F0,3F KP 9 7D F0,7D
2 1E F0,1E F9 47 F0,47 ] 5B F0,5B
3 26 F0,26 F10 4F F0,4F ; 4C F0,4C
4 25 F0,25 F11 56 F0,56 ' 52 F0,52
5 2E F0,2E F12 5E F0,5E , 41 F0,41
PRNT
6 36 F0,36 57 F0,57 . 49 F0,49
SCRN
7 3D F0,3D SCROLL 5F F0,5F / 4A F0,4A
8 3E F0,3E PAUSE 62 F0,62
Table 16-1 PS2 Keyboard scan codes
III、 Experiment Subject

The experimental task is to use PS2 keyboard interface the Pass code will be
displayed on the 7-Seg LED.
Experimental box used PS2 keyboard interface with the FPGA interface
circuit as shown in Fig 16-3. With the FPGA pin connections as shown in
Table 16-2.
Fig 16-3 PS2 Keyboard Interface Schematic

KB_DAT Pin_A9 JP1_29 KeyBoard data
101
KB_CLK Pin_B9 JP1_30 KeyBoard clock
Table 16-2 PS2 keyboard interface with the FPGA pin connection table
IV、 Experiment Step

1、Open QUARTUSII software and reate a new project.
2、then create a VHDL File and open VHDL Editor dialog box.
3、The user can refer to the example provided in the program CD and write.
VHDL Example programs provide two VHDL source code. Every one of the
original program to complete certain functions. The specific features are as
follows Table 16-3:
File Name Completed Funtions
keyboard.VHD PS2 keyboard controller circuit design。
DISPLAY.VHD 7-Seg LED Decoding circuit design。
4、After finish writing VHDL program, to store it. Approach with the experimental
one.
5、To compile and generate VHDL module component files and error and modify
the program. All programs produced by the compiler module component files.
Please refer to the specific method of experiment VI.
6、Create a graphic editing files, modules, components file into which would have
been generated, and pick up on request edges. Upon completion, as shown in
Fig 16-4.
102
Fig 16-4 Edited graphic design files
7、Programs compiled simulation and modify the program. And ultimately
8、Compiled simulation is correct, according to the DIP switch, LED and FPGA pin
connection table or reference in Appendix Pin assignment. Table 16-4 is an
example of the program's Pin assignment table. After the assignment is
complete, and then compile a whole, so Pin assignment to take effect.
CLK Digital signal Pin_T2 Clock 24MHz
RESET Key switch S1 Pin_B12 Reset signal
PS2 Synchronous
KYCOCLK PS2Module clock Pin_B9
Clock
DATA PS2 Module data Pin_A9 PS2 data
A 7-Seg LED A Pin_H15
B 7-Seg LED B Pin_H14
C 7-Seg LED C Pin_H16

Scan code display
D 7-Seg LED D Pin_N16
E 7-Seg LED E Pin_P16
F 7-Seg LED F Pin_R15
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G 7-Seg LED G Pin_R14
DP 7-Seg LED DP Pin_T13
SA DEL0 Pin_N17
SB DEL1 Pin_P17
SC DEL2 Pin_R16
9、Download burner with the corresponding sof file is loaded into the FPGA via
V、 Experimental Results and Phenomena

In reference to the example design, for example, access to the PS2
keyboard interface, PS2 interface. When the design file is loaded into
the target cell, the Digital signal module clock is selected as 24MHz,
press the button on the PS2 keyboard, then in the middle of the 8-7-Seg
LED two experimental platform is the key element will be displayed scan
code. Key pressed to observe whether the scan code corresponding to
one correspondence with Table 16-1. Key switch S1 is stopped by pressing
the keyboard scan codes to scan on 7-Seg LED does not change.
VI、 Experiment Conclusion

1、To draw analog waveform and illustrate.
2、The Experiment Theorem design process, compile and analyze the
104
Experiment 17 VGA color signal generator design
1． Understanding Timing ordinary display correctly displayed.
2． Learn to generate VHDL VGA display timing methods.
3． Further strengthen the FPGA understanding.

Despite the endless stream of new monitors, but CRT (Cathode Ray Tube, cathode
ray tube) basic principle has been in use for decades, until today has not changed much.
The monitor is a complex device, its scalability, and reliability is also very alarming, in
this regard, the electronic control plays a big role, there will be no mechanical wear
and extend the life of electronic order only, or even thousands of hours to adapt work.
CRT's electron gun is a core electron beam emitted hit photosensitive material
(fluorescent) to stimulate phosphor can produce images. In fact, an electron gun and a
large volume, strong power diodes is no different, the principle also applies to
television and oscilloscopes.
CRT is divided into several parts: Deflection Coil (yoke) for positioning the
electron gun emitters, which can generate a strong magnetic field, by changing the
intensity of the electron gun to move. The angle of deflection coils is limited, when the
electron beam is propagated to a flat surface, the target energy is slightly offset, only
part of the phosphor is struck, will produce an image edges are bent. To solve this
problem, the display tube made of a spherical plant, sufficiently to allow the phosphor
receiving energy, the disadvantage is the display will become bent during electron
beam shot by left, top to bottom is called refresh constantly repeat refresh to maintain
the continuity of the image.
Color display screen is composed of RGB (red, green, blue) synthesized three
colored light, we can adjust the hue by three groups of other colors, in many image
105
processing software are provided in the color matching function, you can enter the
three primary color values to the deployment, the software can also be supplied
directly from the palette to select a color. In this part of the function of the
experimental system using a dedicated codec chip to complete. The specific
implementation of the principle will be described in detail in later experiments. In this
experiment only used the RGB tricolor consisting of 8 colors to constitute a color
signal.
VGA monitor display process mainly consists of five control signals, respectively,
R, G, B, HS and VS. Wherein R, G, B three primary colors are used to drive a display
monitor, i.e., red, green, and the basket, HS is the line synchronization signal, VS is the
vertical sync signal. In doing this experiment, since there is no display driver, so the
display in the default state, Resolution: 640 × 480, refresh rate: 60Hz. In this state,
when the VS and HS are low potentials, VGA display is ON, the forward scan is about
26us. After the end of the scan line, the line sync signal HS is set high potential, the
last about 6us, the low potential to high potential during the HS, the display blanking
signal is generated, which is the display retrace process. Upon completion of a scan,
the scan is finished after 480 horizontal and vertical sync signal VS is set high potential
to produce vertical sync, the sync signal can scan line back to the first line of the
display in the first column position. The display shows the timing diagram shown in
Figure 17-1 as follows:
Fig 17-1 CRT Display Timing
106
T1 is a synchronous blanking signal above figure, the pulse width is about 6us, T2
line display process is about 26us, T3 to the line sync signal, a width of two horizontal
synchronizing period, T4 to display the time period of about 480 lines .

The experimental task is to be accomplished through the FPGA show some stripes
or patterns on the display, requiring a CRT monitor can display horizontal stripes,
vertical stripes and checkerboard patterns. Experimental module system clock select
clock 12MHz, with a key module S1 to control the display mode, each press on the
screen to change the pattern of the first, followed by horizontal stripes, vertical stripes
and checkerboard patterns. The output of the experiment is output directly to the VGA
interface, show through CRT monitors.
Experimental box used in digital clock module, Key switch and FPGA
interface circuits, and digital clock source, Key switch and the FPGA pin
connections in previous experiments have done a detailed description, not
repeat them here. VGA interface experimental system video input and output
modules. We can select through a three-element VGA jumper on the module
trichromatic signal is output through the codec chip or directly from the
FPGA output. Its circuit diagram as shown in Figure 17-2:
Fig 17-2 VGA and FPGA circuit connection diagram
107
Table 17-1 is VGA connector connected directly to the FPGA table
Signal Name FPGA IO 名 Explanation
VGA-R Pin_AB13 VGA interface R signal
VGA-G Pin_L6 VGA interface G signal
VGA-B Pin_M5 VGA interface B signal
HSYNC Pin_AB10 VGA synchronous signal
VSYNC Pin_AA10 VGA synchronous signal
Table 17-1 VGA connector is connected directly to the FPGA table after pin.

3、The user can refer to the example provided in the program CD and write
VHDL program.
one.
5、To compile and simulate VHDL and then modify the program for errors.
6、After compiling simulation is correct, according to Digital signal modules, VGA
module, Key switch module and the FPGA pin connections table or reference
in Appendix Pin assignment. Table 17-2 is an example of the program's Pin
assignment table. After the assignment is complete, and then compile a whole,
so Pin assignment to take effect.
CLK Digital signal Pin_T2 Clock 12MHz
KEY Key switch S1 Display mode

Pin_B12
selection
108
R VGA module R
Pin_AB13
signal
G VGA module G
Pin_L6
signal
B VGA module B VGA interface

Pin_M5
signal signal
HS VGA module
Pin_AB10
synchronous
VS VGA module
Pin_AA10
synchronous

In reference to the example design, for example, when the design
file is loaded into the target cell, the system will display the
experimental module for VGA video input and output interface linking
the three million jumpers select all of its module on FPGA (jump to
the lower ), Digital signal clock selection is 12MHz. At this point
the VGA connector on the display screen will appear vertical color
signal. Press Key switch module of the S1 key will change the color
of the horizontal color bars and squares.

2、The Experiment Theorem design process, compile and analyze the
109
3、Programs written test other VGA graphics display.
110
Experiment 18 VHDL Design with Seven Voting
1、 Familiar with VHDL program.
2、 Familiar with the seven voting works.
3、 Understanding the structure of the experimental hardware system.

For the so-called Voting is an act, voted by more than one person, if you agree
with more than half the votes, they think this behavior is feasible; otherwise rejected if
more than half the votes, this behavior is considered invalid.
Seven voting by definition is made up of seven individuals to vote, when the
agreed number of votes greater than or equal 4:00, then that consent; Conversely, when
the rejection is greater than the number of votes equal to or 4:00, then that does not
agree. Experiments using seven DIP switches to said seven people, when '1
corresponding DIP switch input ', this means that people agree; otherwise if DIP switch
input is '0', it means against it. Results of the vote with an LED indicates the result if
the vote was agreed that the LED is lit; Otherwise, if the results of the vote for the
opposition, the LED is not lit. Meanwhile, the number of votes by the 7-Seg LED on
the display.

This experiment is the use of the experimental system DIP switch module and
LED module and 7-Seg LED module to implement a simple seven voting function.
Refers to the switch module in the K1 dial ~ K7 said seven people, when DIP switch
input is '1 ', which means that the corresponding cast votes in favor, or when the DIP
switch input is '0', which means that people vote against the corresponding; LED
module LED1 indicates the result of the vote of seven, when LED1 is lit, which means
111
that this behavior by voting; otherwise when LED1 is off, this behavior is not by vote.
Meanwhile votes to pass displayed on the 7-Seg LED.
In this experiment 7-Seg LED, LED, DIP switch and the FPGA pin connector to
connect the circuit and in previous experiments have done a detailed description, not
repeat them here.
IV. Experiment Step

VHDL program.
4、 After finish writing VHDL program, to store it. Approach with the experimental
one.
5、 Compile and simulate VHDL program, and then modify the program for errors.
6、 Compiled simulation is correct, according to the DIP switch, LED, 7-Seg LED
with the FPGA pin connections or reference table in Appendix Pin assignment.
effect.
K1 DIP Switch K1 Pin_W6
K2 DIP Switch K2 Pin_Y4
K3 DIP Switch K3 Pin_U7
K4 DIP Switch K4 Pin_V3 Seven voting

K5 DIP Switch K5 Pin_P5
K6 DIP Switch K6 Pin_AB12
K7 DIP Switch K7 Pin_V7

m_Result LED module LED1 Pin_V10 Voting Result
LEDAG0 7-Seg LED module A Pin_H15 Voting by
112
LEDAG1 7-Seg LED module B Pin_H14 votes
LEDAG2 7-Seg LED module C Pin_H16
LEDAG3 7-Seg LED module D Pin_N16

LEDAG4 7-Seg LED module E Pin_P16
LEDAG5 7-Seg LED module F Pin_R15
LEDAG6 7-Seg LED module G Pin_R14
LEDAG7 7-Seg LED module DP Pin_T13
JTAG..Observed experimental results are consistent with their program

is loaded into the target cell, toggle the experimental system of the middle
finger DIP switch module K0-K7 seven million DIP switch, if the DIP switch
is "1" (referring DIP switch switch to the upper end of said person by a
vote) is greater than or equal to the number of seasons LED module LED1
is lit, otherwise LED1 is not lit. By voting, while the number displayed
on the 7-Seg LED.

2、Recoded the experiment Theorem, the design process, compile and
analyze the results and the analog waveform hardware and test results.
3、Try this experiment on the basis of an increase in the time to vote,
the voting results are only valid during this time.
113
Experiment 19 Design Four Responder with VHDL
1、Familiar four Responder works.
2、Deepen understanding of VHDL language.
3、Master the basic processes EDA development.

Responder in various competitions nature of the occasion has been widely applied,
it appears, eliminating the original because the human eye is unable to correct the error
and determine the first person to answer in the case.
The principle is relatively simple Responder First Responder allows the flag to be
set a bit, the purpose is to allow or prohibit the answer by pressing the button; If
Responder enable bit is valid, then the first answer by pressing a button will clear it,
but No. Record button, press the corresponding button is the man, the purpose of doing
so is to ban someone and then press the button behind the case. Overall, the Responder
Responder allows the realization that the rear valid, the first person to press the button
to clear it to disable a button is pressed again while recording clear answer button
allows the bit serial number and displayed this is the realization of the principle
Responder.

The experimental task is to design a four Responder, use the button module
allows the S5 to make answer button with S1 ~ S4 to represent the 1st Responder
Responder No. 1-4, but with LED module for LED1 ~ LED4 respectively in
Responder corresponding seat. Specific requirements are: S12 pressed once, allowing
one answer, then S1 ~ S4 in the first press of the button will allow the bit clear answer,
while the corresponding LED lights to indicate the corresponding key answer
successfully. 7-Seg LED shows the corresponding answer in the number of winners.
114
In this experiment 7-Seg LED, LED, Key switch and the FPGA pin connector to
connect the circuit and in previous experiments have done a detailed description, not
repeat them here.
IV. Experiment Step

2、 Then create a VHDL File and open VHDL Editor dialog box.
VHDL program.
one.
6、 Compiled simulation is correct, according to Key switch, LED, 7-Seg LED with
the FPGA pin connections or reference table in Appendix Pin assignment. Table
19-1 is an example of the program's Pin assignment table. After the assignment
is complete, and then compile a whole, so Pin assignment to take effect.
S1 Key switch S1 Pin_B12 1st Responder
S2 Key switch S2 Pin_B11 2st Responder

S3 Key switch S3 Pin_V4 3st Responder
S4 Key switch S4 Pin_T4 4st Responder
START Key switch S12 Pin_T1 Answer key start
DOUT0 LED module LED1 1st Responder

Pin_V10
lights

Pin_W8
lights
DOUT2 LED module LED3 Pin_W10 3st Responder
115
lights

Pin_Y10
lights
LEDAG0 7-Seg LED module A Pin_H15
LEDAG1 7-Seg LED module B Pin_H14
LEDAG2 7-Seg LED module C Pin_H16
LEDAG3 7-Seg LED module D Pin_N16 Answer

LEDAG4 7-Seg LED module E Pin_P16 successful
LEDAG5 7-Seg LED module F Pin_R15 Number Display
LEDAG6 7-Seg LED module G Pin_R14
LEDAG7 7-Seg LED module

Pin_T13
DP

is loaded into the target cell, press the button Key switch of S12,
indicates the start of answer. Then, while pressing the S1-S4, the first
key pressed is displayed Key 7-Seg LED, the corresponding LED lamp is lit.
At the same time, other keys lost Responder role.

2、 Recoded the experiment Theorem, the design process, compile and
116
Experiment 20 Positive and Negative Pulse Width
Modulation Signal Generator Design
1、Learn to master the principles of positive and negative pulse width modulated
digital control signal occurred.
2、 skilled use of probing points waveform on the oscilloscope test box.
3、 To know the basic idea of the timing circuit design.

First, the principle of positive and negative pulse elaborate digital control . The
so-called positive and negative pulse is the direct digital control input the number of
positive and negative pulse width pulse signal number , of course , the number of
positive and negative pulse once finalized, will determine the periodic pulse wave
down . Second, the modulation signal, there are many modulation signal with
frequency modulation , phase modulation, amplitude modulation , etc., in this
experiment, only the output waveform of a most simple digital modulation EDA design
flexibility in addition to the experiment requirements can be The output of non-
modulated waveform , positive and negative pulse modulation pulse modulation.
Non-modulated wave is the original pulse waveform ; positive pulse in the pulse
modulated output is '1 ' the output of another period of the frequency with a square
wave , pulse wave and a '0' or a component of the original waveform ; positive and
negative pulse modulation is just pulse modulation contrast, the pulse wave output is
required in the '0 ' output of the other frequency square wave period, '1 ' is output
during the original waveform . To simplify the experiment , here 's modulation
waveform ( another frequency square wave ) on the use of the original clock signal.
The specific waveform as shown in Fig 20-1 :
117
Fig. 20-1 Modulation waveform

本 The task is to design an experiment positive and negative pulse width
modulated signal digitally controlled generator. Requires the ability to output a digital
pulse width of positive and negative control, the positive pulse and a pulsed negative
pulse waveform of the pulse modulation. Experiment clock signal selects the clock
module of 1MHz signal, with the DIP switch module is K1 ~ K4 as a positive pulse
width of the input, with K7 ~ K10 as a negative pulse width of the input, with Key
switch module in S1 as a model selection keys, each press changes the pulse waveform
output once, followed by the original pulse, positive and negative pulse modulation
wave pulse modulation waveform. Waveform output to the experimental observation
module box probe to an oscilloscope.
In this experiment, the middle finger DIP switch, Key switch, the observed
output terminal connected to the FPGA circuit and pin connections in previous
experiments have done a detailed description, not repeat them here.
IV. Experiment Step

VHDL program.
118
one.
8、 Compiled simulation is correct, according to the DIP switch, Key switch, the
output of the observation point and the FPGA pin connections or reference table
in Appendix Pin assignment. Table 20-1 is an example of the program's Pin
assignment table. After the assignment is complete, and then compile a whole, so
Pin assignment to take effect.
P0 DIP Switch K1 Pin_W6
P1 DIP Switch K2 Pin_Y4 Positive pulse width
P2 DIP Switch K3 Pin_U7 of the input
P3 DIP Switch K4 Pin_V3
N0 DIP Switch K7 Pin_V7
N1 DIP Switch K8 Pin_V6 Negative pulse
N2 DIP Switch K9 Pin_R5 width of the input
N3 DIP Switch K10 Pin_T5
Output mode
MODE Key switch S1 Pin_B12
selection
Observation module Modulated signal

FOUT Pin_N5
output output
V. Experimental results and phenomena
119
is loaded into the target cell, the Digital signal module clock selection
of 1MHz, DIP switch toggle octet, so K1-K4 in at least one of high potential,
K5-K8 at least one of high potential, the output module observation can
be observed with an oscilloscope to a rectangular wave with a duty cycle
of high and low potential of the high potential number K1-K4 and K7-K10
than the number of high potential. After pressing the S1 button,
rectangular wave changes, output such as Fig. 20-1 modulated waveform
shown.

analyze the results and the analog waveform hardware and test
results.
120
Comprehensive Design of Experiments
Experiment 21 Digital Frequency Meter Design
1. Understand and other precision frequency measurement methods and
principles.
2. Master how to design a variety of functions within the FPGA module.
3. In the measurement technique master module VHDL design.

Frequency is the number of so-called periodic signal in the unit time (1s) change.
If the predetermined time interval T (also called the shutter time) was measured
periodically changing the signal repetition frequency is N, the frequency can be
expressed as
f＝N/T
You can see from the above expression, if the time interval T take 1s, then f = N. Since
the start and end time for the gate signal is random, the quantization error will have a
pulse period. Further analysis of measurement accuracy: Set the test signal pulse
period Tx, frequency Fx, when the measurement time is T = 1s, the measurement
accuracy of δ = Tx / T = 1/Fx. It can be seen that the direct measurement method for
measuring the frequency and accuracy of the measured signal frequency, when the
high frequency signal to be measured, the measurement accuracy is high, whereas the
low measurement accuracy. Therefore, this method is only suitable for direct frequency
measurement higher measuring frequency signal, can not be met within the entire
measurement frequency measurement accuracy requirements remain unchanged. To
get the entire measuring frequency measurement accuracy requirements remain
unchanged, other methods should be considered to be precision frequency
121
measurements.
Precision frequency measurement method such as frequency, you can use
Fig. 20-1 block diagram shown to achieve.
Fig 21-1 Achieve equal precision frequency measurement block diagram
Refers to the so-called equal precision frequency meter measured
across the inside of the band, can achieve the same accuracy of measurement,
that measurement accuracy is independent of frequency. Figure preset
threshold signal is typically 1s. Its interior includes a synchronous gate,
the measured frequency standard used to achieve synchronization with the
measured frequency to improve measurement accuracy, reduce the basic error.
The portion of the zero pulse to control the coordination of the two
counters start pulse. Counters 1 and 2 were used to counter and measured
frequency standard digital pulse counting, located at the end of a
synchronous gate control counter counts N1, counter 2 counts N2, assuming
frequency standard frequency of F1, the measured frequency bit Fx, then
we can write the formula:
Fx/N2=F1/N1；…………………（1）
Fx＝（F1/N1）* N2……………（2）
As can be seen from the formula, the accuracy of measurement
independent of the gate with a preset time, the frequency stability is
122
mainly determined F1, so in order to improve the measurement accuracy, the
main target is to increase the frequency stability of the frequency, in
other words, measurement accuracy is substantially similar frequency
Standard stability, frequency stability if the subject is 10-6, the
measurement error can reach 10-6. In this circuit, the frequency standard
in order to ensure full synchronization of the count and the measured
frequency (i.e., on the rising edge of the measured frequency, 1s later,
the measured frequency of edge stops counting), must be controlled by the
burst gate signal under test design methods varied by the students
independently.
In this study, the direct frequency measurement method for frequency measurement.
A fixed gate time is 1s, the gate signal is a square wave of 0.5Hz, the effective period
of the shutter (high potential), the input of the pulse counting time of the falling edge
of the strobe signal latches the current count value to zero and All frequency counters.
Since the gate time is 1s (0.5Hz square wave), so the frequency display is updated
every 1s, the content and the display when the gate is latched on the falling value.
ecause we set the gate time is 1s, so this can only be measured by the frequency
meter frequency greater than or equal to 1Hz case, and the higher the frequency, the
higher the accuracy. Practical applications, frequency meter variable gate time is
available, when the frequency is less than 1Hz, the gate time is necessary to properly
amplified. , A standard clock, as the unit of time: 0.1 seconds of the measured pulse
count signal, the signal is frequency.
In the design frequency meter, when 8 7-Seg LED can display up to 99,999,999
Hz, therefore, when used in the design of 8 4-bit binary code (BCD code) to indicate,
also must have the same 8 four bit binary input frequency to be counted, when the
falling edge of the gate, the latter value is latched into the register. Its signal timing
123
relationships shown in Figure 21-2 follows:
Fig 17-3 Control signal timing relationships

n this study, to complete the task is to design a frequency counter, the system
clock selection 50M clock core board, the gate time is 1s (via the system clock
frequency to be), the gate for the duration of the high potential of the frequency of
the input will be count, when the gate goes low when recording current frequency
value, and zero frequency counter, frequency display is updated once every two
seconds too. Measured frequency through a DIP switch to choose whether to use the
system clock source module digital clock signal or a digital signal input through the
input from the external input and output module of the system frequency
measurements. When the DIP switch is a high potential, digital signal input from the
external measurement, otherwise the digital measuring system clock signal module
digital signal. Its realization block diagram is shown below in Figure 21-3:
124
Fig 21-3 Frequency measurement block diagram realization
In this experiment, the use of the module has Digital signal module,
DIP switch module, 50M system clock source module, 7-Seg LED display
module and so on. Which 7-Seg LED, Digital signal, DIP switch and the
FPGA pin connector to connect the circuit and in previous experiments
have done a detailed description, not repeat them here. Module 50M system
clock source is located in the bottom of the core board EP3C40 50M through
a 50MHz oscillator to generate a clock signal, a detailed description,
please refer to the user manual. With the FPGA pin connections as shown
in Table 21-1.
Signal Name FPGA IO Explanation
System Clock Pin_G1 50MHz Clock
Table 21-1 50M system clock and the FPGA pin connection table
IV. Experiment Step

VHDL program. Example programs provide a total of six VHDL source
code. Every one of the original program to complete certain functions. The
specific features are as follows Table 21-2:
125
File Name Completed Funtions
CLKOUT.VHD Generate the gate signal 1Hz and 1KHz display scanning signal
MUX.VHD Test signal source selection module
Generating a control signal frequency measurement in the role

TELTCL.VHD
of the clock.
CNT10.VHD Decimal counter. 8 used in the experiments to count
32-bit latch, the latch control signal at the role of the count value
SEG32B.VHD
latched
DISPLAY.VHDL Show decodes the information displayed latch.
experimental one.
9、 To compile and generate VHDL module component files and error and
modify the program. Eventually all programs produced by the compiler and
module component file. Please refer to the specific method of experiment
VI.
10、 A new graphical editing files, module component file into which would have
been generated, and pick up on request edges.
11、 Programs compiled simulation and modify the program. And ultimately
12、 Compiled simulation is correct, according to the DC motor, the Hall element,
7-Seg LED with the FPGA pin connections or reference table in Appendix
Pin assignment. Table 21-3 is an example of the program's Pin assignment
table. After the assignment is complete, and then compile a whole, so Pin
126
CLK50M 50M System Clock EP3C40 system board

Pin_G1
clock
CLKIN1 Input and output External test clock input

Pin_AB13
observation module
CLKIN2 Digital signal Internal test clock input

Pin_T2
module
KEY DIP Switch K1 External / internal test

Pin_W6
clock selection

The measured signal
frequency display
SEL0 Bit Select DEL0 Pin_N17
SEL1 Bit Select DEL1 Pin_P17
SEL2 Bit Select DEL2 Pin_R16

is loaded into the target cell, toggle DIP switches K1, it is set to a
127
high potential, input and output from the input observation module input
a frequency greater than 1Hz clock signal, then this clock signal
frequency value is displayed in the 7-Seg LED. Digital signal frequency
clock on the DIP switch if so set to low, is displayed on the display
Seven-segment value system. Digital signal change clock, see the value
displayed is consistent with the standard value.

2、 according to the method precision frequency meter described above,
and other precision frequency meter to write VHDL code.
128
Experiment 22 Multi-function Digital Clock Design
1、 To understand the digital clock works.
2、 Familiar with the use of VHDL language driver 7-Seg LED code.
3、 master VHDL prepared some tips.

Multi-function digital clock should have functions: display - minutes - seconds,
the whole point of time, in hours and minutes adjustable and other basic functions. We
must first know the watch works, watch the entire work should be in the role of 1Hz
signal is carried out, so that each clock signal, second increase in one second, when the
seconds from 59 seconds to jump to 00 seconds, 1 minute minute increase , but when
the minutes from 59 minutes to jump to 00 min, hours increased 1 hour, but note that
the hours range from 0 to 23.

n the experiment, in order to facilitate the display, because the range of minutes
and seconds are displayed from 0 to 59, so you can use a 3-bit binary code display ten
bit, with a four-element binary code (BCD code) display a bit, for the hour as it ranges
from 0 to 23, so you can use a 2-bit binary code display ten bit, using 4-bit binary code
(BCD code) display a bit.
Experiments is due 7-Seg LED scan display, so although the clock is required
1Hz clock signal, but do need to scan a relatively high frequency signal, so in order to
obtain accurate 1Hz signal, the input system clock must be of frequency.
For the whole point timekeeping function, users can be designed according to the
hardware structure of the system and their own specific requirements. The
experimental design was carried out when the whole point of the countdown timer 5
seconds, the LED flashes to prompt the whole point of timekeeping.
129
The experimental task is to design a multi-functional digital clock display format
for the required hours - minutes - seconds, the whole point timekeeping, timekeeping
time is 5 seconds, 5 seconds from the start before the whole point timekeeping tips,
LED starts flashing, cross the whole point, to stop flashing. System clock selection
Clock module of 10KHz, to get 1Hz clock signal, the system must be 10,000 times the
clock frequency. Buttons to adjust the time using the button module S1 and S2, S1
adjust the hours, every time you press, hours increase one hour, S2 adjust minutes,
every time you press, minutes, increases a minute. Also used as a system clock reset
button S12, after resetting all Show 00-00-00.
Experimental box used in digital clock module, Key switch, LED, 7-Seg
LED with FPGA interface circuits, and digital clock source, Key switch,
LED, 7-Seg LED with the FPGA pin connections in previous experiments have
done a detailed description, not repeat them here.
IV. Experiment Step

2、 Then create a VHDL File and open VHDL Editor dialog box.
VHDL program.
experimental one.
5、 Compile and simulate VHDL program, modify the program for errors, until
completely through the compilation and simulation.
6、 ompiled simulation is correct, according to Key switch, 7-Seg LED, LED
lights and FPGA pin connection table or reference in Appendix Pin assignment.
130
effect.

S1 Key switch S1 Pin_B12 Adjust the hour
S2 Key switch S2 Adjustment
Pin_B11
minutes
RESET Key switch S12 Pin_T1 Reset
LED0 LED module LED1 Pin_V10
The whole point
LED1 LED module LED2 Pin_W8
of the
LED2 LED module LED3 Pin_W10
countdown
LED3 LED module LED4 Pin_Y10
DISPLAY0 7-Seg LED A Pin_H15
DISPLAY 1 7-Seg LED B Pin_H14
DISPLAY 2 7-Seg LED C Pin_H16
DISPLAY 3 7-Seg LED D Pin_N16
DISPLAY 4 7-Seg LED E Pin_P16
DISPLAY 5 7-Seg LED F Pin_R15 Time Display

DISPLAY 6 7-Seg LED G Pin_R14
DISPLAY7 7-Seg LED DP Pin_T13
SEG-SEL0 Bit select DEL0 Pin_N17
SEG-SEL1 Bit select DEL1 Pin_P17
SEG-SEL2 Bit select DEL2 Pin_R16
7、 With the corresponding burner download sof file is loaded into the FPGA
via JTAG. Observed experimental results are consistent with their programs.

131
is 1MHz, 7-Seg LED began to show time, beginning from 00-00-00. The whole
point of 5 seconds before the time, LED light module for LED1-LED5 starts
blinking. Once over the whole point, LED stops. Press Key switch of S1,
S2 hour and minute to start stepping adjustment time. Press Key switch
of S12, the display is restored to 00-00-00 restarted display time.

2、將 Experiment Theorem、Recoded the experiment Theorem, the design
process, compile and analyze the results and the analog waveform
hardware and test results.
3、 n the basis of this experiment to try other ways to achieve the
digital clock function, and add other features.
132
Experiment 23 Digital Stopwatch Design
1、To learn the basis of digital stopwatch..
2、More familiar with VHDL language driver 7-Seg LED code.
3、To know VHDL some tips.

Because of its timing stopwatch accurate, high resolution (0.01 seconds), in a
variety of arenas has been widely used.
Works and experimental code table is basically the same fifteen multifunctional
clock, the only difference is that because of a timing clock signal code table, due to its
resolution of 0.01 seconds, so the entire working clock stopwatch clock signal at
100Hz under complete. When the chronograph is less than a little from time to time,
format is mm-ss-xx (mm represents minutes: 0 ~ 59; ss is seconds: 0 ~ 59; xx
represents hundredths of a second: 0 to 99), when the chronograph is greater than or
equal to one hour, and the multi-function display is the same as the clock is hh-mm-ss
(hh is the hour: 0 to 99), due to the function and chronograph timepiece is different, so
hh code table indicates the range is not 0 to 23, but 0 to 99, and this is not the same
place multifunction clock.
In the design of the code table when the clock selection is 100Hz. Variable
selection: Because xx (0.01 seconds) and hh range (hours) that are 0 to 99, so with two
4-bit binary code (BCD code) said; while ss (seconds) and mm (min) represents the
range from 0 to 59, so with a 3-bit binary code and a 4-bit binary code (BCD)
representation. Show time to pay attention to issues that hour judgment, if the hour is
00, the display format is mm-ss-xx, if not 00 hours, it shows hh-mm-ss.

The experimental task is to design a stopwatch, clock module of the system clock
133
selection 1KHz, due to the timing clock signal to 100Hz, so the need for the system
clock divided by 10 to get the reason for choosing 1KHz clock is needed because
7-Seg LED scan display, so choose 1KHz. In addition to easy to control, the need for a
reset button to start and stop the timer button chronograph buttons, key module were
selected experimental box of S1, S2 and S3, press S1, the system is reset, all the
registers of all zero; Press S2, start the stopwatch timing; press S3, stopwatch stop the
clock, and 7-Seg LED shows the current time of time, if you press S2 again, stopwatch
timing continues until press S1, the system can be reset to show all 00-00-00.
LED with FPGA interface circuits, and digital clock source, Key switch,
LED, 7-Seg LED with the FPGA pin connections in previous experiments have
done a detailed description, not repeat them here.

VHDL program.
one.
5、Compile and simulate VHDL program, and then modify the program for errors.
134
CLK Digital signal Pin_A14 Clock is 1KHz
Stopwatch starts
START Key switch S1 Pin_T2
counting
Stopwatch stops
OVER Key switch S2 Pin_B12
counting
RESET Key switch S3 Pin_B11 Reset signal
LEDAG0 7-Seg LED A Pin_V4
LEDAG3 7-Seg LED D Pin_H16
LEDAG4 7-Seg LED E Pin_N16 Stopwatch count
LEDAG5 7-Seg LED F Pin_P16 result output
LEDAG7 7-Seg LED DP Pin_R14
SEL0 Bit Select DEL0 Pin_T13
SEL1 Bit Select DEL1 Pin_N17
SEL2 Bit Select DEL2 Pin_P17

n reference to the example design, for example, when the design
file is loaded into the target cell, the Digital signal module clock
is selected as 1KHz, designed digital stopwatch starts counting seconds
from 00-00-00. Until you press the Stop button (Key switch S2). 7-Seg
LED to stop the seconds. Press the Start button (Key switch S1), 7-Seg
135
LED continue to count seconds. Press the reset button (Key switch S3)
from 00-00-00 to restart the stopwatch count seconds.

2、Recoded the experiment Theorem, the design process, compile and
136
Experiment 24 Taxi meter design
1、Learn taxi meter works.
2、Learn to write correctly 7-Seg LED programming using VHDL.
3、Number of master writing complex function module with VHDL.
4、Further the number of state machines in the system design.

Taxi meter billing are generally in kilometers, which is usually the starting price of
$ xx (xx bit can walk x km), and then is xx bit / km. So to complete a taxi meter, there
should be two counts, one for total kilometers, another one for expenses. Usually have
sensors on the wheels of a taxi, used to record the number of turns the wheels turning,
and the circumference of the wheels is fixed, so we know the number of turns naturally
know the mileage. In this experiment, we must simulate the operation of the taxi meter,
a DC motor simulation taxi wheel through the sensor, the motor can be one pulse per
revolution of the output waveform. Results are displayed with 8 7-Seg LED, the first
four display mileage, after four display costs.
VHDL design program, the first action in the reset signal will be zero for all
registers used, and then start setting the starting price records state, in this state, have
been displayed at the starting price in the specified mileage Pricing starts until the
specified mileage distance than the starting price, the system is transferred to the charge
per kilometer state, then each additional kilometer meter corresponding increase in costs.
Also talk about the process of writing some tips. In order to facilitate the display,
data used in the preparation process of the BCD code to display, so there is the problem
of data format conversion. For example, said a three-digit, four bit respectively, then the
binary code to indicate when the single-digit accumulate more than 9:00, which was zero,
while ten bit figures plus 1, and so on.
137
In this study, to complete the task is to design a simple taxi meter, the requirement is
starting at $ 3, quasi-line one kilometer, after one bit / km. Display portion 7-Seg LED
clock module's scan clock selection 1KHz, jumper motor module selection GND
terminal, so by turning the potentiometer motor module can achieve the purpose of
controlling the motor speed. In addition to using the S1 key module of the whole
system as a reset button, reset each time, billing billing from scratch. DC motor is used
to simulate a taxi wheels, each rotation considered walking one meter, so every lap
rotation 1000 that the car forward one kilometer. System design is needed for detecting
the rotation of the motor per revolution, the counter is incremented by 1 meter. 7-Seg
LED display requirements for the first four displays mileage, after three display costs.
Experimental box used in digital clock module, Key switch, DC motor
module, 7-Seg LED with FPGA interface circuits, and digital clock source,
Key switch, LED, 7-Seg LED with the FPGA pin connections in the previous
experiments have done a detailed description, not repeat them here.

VHDL program.
one.
5、Compile and simulate VHDL program, and then modify the program for errors.
138
MOTOR DC Motor module Pin_G3 44E Pulse output
RST Key switch S1 Pin_B12 Reset signal
DISPLAY0 7-Seg LED A Pin_H15
DISPLAY 1 7-Seg LED B Pin_H14
DISPLAY 2 7-Seg LED C Pin_H16
DISPLAY 3 7-Seg LED D Pin_N16
DISPLAY 4 7-Seg LED E Pin_P16 Meter display costs
DISPLAY 5 7-Seg LED F Pin_R15
DISPLAY 6 7-Seg LED G Pin_R14
DISPLAY 7 7-Seg LED DP Pin_T13
SEG-SEL0 Bit select DEL0 Pin_N17
SEG-SEL1 Bit select DEL1 Pin_P17
SEG-SEL2 Bit select DEL2 Pin_R16

Reference Example In the example design, the design when the file
is loaded to the target device, the clock selection Digital signal
module is 1KHz, the module selected for DC motor "ON", the rotation
speed of a DC motor control knob, the DC motor start rotating observed
7-Seg LED to display the value of the design are the same.
139
140
Experiment 25 Design of Digital Locks with VHDL
I、Experiment Object
1、Understanding digital lock works.
2、Understanding digital lock implementations.
3、Further understand the 4 × 4 keyboard scan implementation process.
II、Experiment Theorem
Also known as a digital lock password lock, it only needs to remember your master
password to unlock, open the door only need to enter the password, you can open the
door, so the core of the problem is that the password lock alignment problem.
If there are six million locks, then after the system reset button 6 times a user to
enter a password string intact, finished sixth after entering the system for comparison, if
you find a password match, then open the door, otherwise require the use of who continue
to enter, if three consecutive strings are wrong password is entered, the system alarm
sounded until the correct password is entered, the alarm sound stops.
Experiments also used 4 × 4 keyboard for a user to enter a password . Systems
need to complete 4 × 4 keyboard scan , after a key is needed to determine access to its
Key, and encode , thus identifying key and press the corresponding Key for display.
Keyboard scan implementation process is as follows: For the 4 × 4 keyboard , usually
connected to four rows , four , so to identify the key only needs to know which rows
and columns which can, in order to complete the identification process , the first output
4 first as a low potential , the other as a high potential , and then read the column value ;
then output 4 second as low potential , read the column values , and so on , continually
loop. System when reading row value will automatically determine if the incoming line
read all of the high potential value , then there is no button is pressed , or if the value of
reading lines incomplete discovery came as high potential , then there must be a
keyboard entire column at least one button is pressed, the value of this time to read the
141
line and current column values , you can determine the current key position. Get to the
row and column values in the future , a combination of an 8- bit data , depending on
the implementation of different coding in the match for each button , find the Key
displayed in the 7-Seg LED.
III、Experiment Subject
The experiment was a need to complete the task locks, taking into account the
system has a keyboard scan, 7-Seg LED display and alarm clock module of the system
clock select 10KHz clock. Keyboard scanning and display are used 1KHz (10 points
on the system clock frequency), when you enter a password, 7-Seg LED from right to
left button corresponding values for each key (0 to 9) once to display the left once,
after the end of the 6th password verification system began after the end of the
verification, 7-Seg LED all off. That is, the time display is the key part of maintaining
six times and check the time. Enter the password incorrectly three times in a row to
start the alarm. Experiment with the LED module is required LED1 indicates the
keyboard state, if a key is pressed, LED1 lights, until you release the button; using
LED2 indicates the status of the door, which is password verification result, if correct
password verification, LED2 lights since, otherwise, if the password validation error
LED2 blinks four times and then turns off, indicating that the password is wrong.
RESET button to reset the system with the core of the board, when reset, 7-Seg LED
are off.
LED, keyboard array and FPGA interface circuits, and digital clock source,
Key switch, speaker interface, LED, 7-Seg LED, keyboard array and FPGA the
pin connections in previous experiments have done a detailed description,
not repeat them here. RESET button to reset the core board, refer to the
user manual for instructions.
142
IV、Experiment Step
VHDL program.
4 、 After finish writing VHDL program, to store it. Approach with the
experimental one.
5、To compile and simulate VHDL, modify the program for errors, until
completely through the compilation and simulation.
6、After compiling simulation is correct, each module used in accordance with
the FPGA pin connections or reference table in Appendix Pin assignment.
V、Experimental Results and Phenomena

is 10KHz, press the keyboard matrix digital key, 7-Seg LED will be
displayed in turn pressed Key. Each time you press a key, LED1 will flash
once. If the input data and program settings data are the same, the LED
D12 is lit. If you make a mistake, then the D12 LED lights flashing.
Continuous input error 3 times 12 LED starts flashing alarm.
VI、Experiment Conclusion
143
3、 On the basis of this experiment on other methods to try to achieve
the digital clock function, and add other features.
144
Schedule I：CPU Board And FPGA(EP4CE40) Pin Mapping
Signal Name FPGA IO Signal Name FPGA IO

CPU Board FLASH（AM29LV128）
A0 W19 A18 V22
A1 AA15 A19 U21
A2 W20 A20 P21
A3 AA21 A21 R22
A4 Y21 A22 U22
A5 Y22 A23 K22
A6 W21 D0 AB17
A7 W22 D1 AA17
A8 V21 D2 AB18
A9 P22 D3 AA18
A10 N21 D4 AB19
A11 N22 D5 AA19
A12 M21 D6 AB20
A13 M22 D7 AA20
A14 L21 WE# R21
A15 L22 OE# AA16
A16 K19 CS# AB16
A17 K21
CPU Board User LED（LED1-LED4）
LED1 AA13 LED3 AA14
LED2 AB14 LED4 AB15
CPU Board 7-Seg LED
A AB9 E AB5
B AA8 F AB8
C AA7 G AB7
D AA4 DP AA5
145
CPU Board SRAM（IDT74V416）
A0 W20 D11 T18
A1 AA21 D12 R19
A2 Y21 D13 R20
A3 Y22 D14 R18
A4 W21 D15 P20
A5 W22 D16 G18
A6 V21 D17 H20
A7 P22 D18 H18
A8 N21 D19 J18
A9 N22 D20 K18
A10 M21 D21 N18
A11 M22 D22 M20
A12 L21 D23 M19
A13 L22 D24 F19
A14 K19 D25 F20
A15 K21 D26 F17
A16 V22 D27 F16
A17 U21 D28 D20
D0 AB17 D29 E16
D1 AA17 D30 D19
D2 AB18 D31 D17
D3 AA18 BE0 N20
D4 AB19 BE1 N19
D5 AA19 BE2 C17
D6 AB20 BE3 C19
D7 AA20 OE# H10
D8 U17 WE# H11
D9 U19 CS# W17
D10 U20 ------ ------
146
CPU Board User Button
BT1 T21 BT3 G21
BT2 T22 BT4 G22
CPU Board 50M Clock
CLK50M G1 ------ ------
CPU Board Reset Button
RESET E4 ------ ------
CPU Board SDRAM
DQ0 C21 A0 B19
DQ1 B22 A1 A19
DQ2 B21 A2 B18
DQ3 C22 A3 A18
DQ4 D21 A4 D15
DQ5 D22 A5 C15
DQ6 E21 A6 E15
DQ7 E22 A7 D13
DQ8 B15 A8 C13
DQ9 A15 A9 E14
DQ10 B14 A10 A20
DQ11 A14 A11 B17
DQ12 B13 A12 A17
DQ13 A13 SD-M0 F21
DQ14 B10 SD-M1 A16
DQ15 A10 SD-BA0 J22
SD-CLK E6 SD-BA1 B20
SD-WE F22 RAS H22
SD-CS J21 CAS H21
SD-CKE B16 ------ ------
147
CPU Board Expension JP1
1 5V 31 M6
2 GND 32 M7
3 J1 33 L7
4 J2 34 K7
5 H1 35 J7
6 H2 36 G7
7 G3 37 H7
8 F1 38 G8
9 F2 39 G9
10 E1 40 F8
11 D2 41 F9
12 C1 42 F10
13 C2 43 E11
14 B1 44 F11
15 C3 45 G13
16 B2 46 F13
17 A3 47 F14
18 B3 48 G14
19 A4 49 F15
20 B4 50 G15
21 A5 51 G16
22 B5 52 J6
23 A6 53 J3
24 B6 54 J5
25 A7 55 J4
26 B7 56 H5
27 A8 57 G5
28 B8 58 G4
29 A9 59 H6
148
30 B9 60 F7
61 E3 71 E9
62 K8 72 E10
63 C4 73 D10
64 E5 74 C10
65 E7 75 E12
66 C6 76 A11（CLK10）
67 D6 77 B11（CLK11）
68 C7 78 A12（CLK8）
69 D7 79 B12（CLK9）
70 C8 80 E13
1 5V 21 H14
2 GND 22 H15
3 U10 23 G11
4 U11 24 /
5 V12 25 T15
6 V13 26 T17
7 U12 27 R17
8 U13 28 T16
9 U14 29 R16
10 U15 30 P17
11 T10 31 N17
12 T11 32 /
13 T23 33 G10
14 T14 34 H8
15 T13 35 J8
16 R14 36 M16
17 R15 37 K17
18 P16 38 J17
19 N16 39 H17
149
20 H16 40 G17
1 5V 31 T8
2 GND 32 T9
3 M1 33 U8
4 M2 34 U9
5 N1 35 V8
6 N2 36 V9
7 P1 37 AA9
8 P2 38 AB10
9 R1 39 AA10
10 R2 40 AB11（CLK14）
11 T1（CLK3） 41 AA11（CLK15）
12 T2（CLK2） 42 AB12（CLK12）
13 U1 43 AA12（CLK130
14 U2 44 AB13
15 V1 45 L6
16 V2 46 M5
17 W1 47 N5
18 W2 48 P3
19 Y1 49 P4
20 Y2 50 P5
21 AA1 51 T3
22 Y3 52 T4
23 AB3 53 T5
24 AA3 54 V3
25 AB4 55 V5
26 N6 56 V4
27 P6 57 R5
28 R7 58 U7
29 R6 59 V6
150
30 T7 60 Y4
61 V7 71 V11
62 W6 72 Y13
63 Y6 73 W13
64 Y7 74 W14
65 W7 75 W15
66 Y8 76 V14
67 W8 77 V15
68 V10 78 V16
69 Y10 79 U16
70 W10 80 Y17
------
151
Schedule II：System Board And CPU Board IO Mapping
EDA/SOPC SYSTEM BOARD 16Bit LCD
D0 Pin_M1 D11 Pin_V2
D1 Pin_M2 D12 Pin_W1
D2 Pin_N1 D13 Pin_W2
D3 Pin_N2 D14 Pin_Y1
D4 Pin_P1 D15 Pin_Y2
D5 Pin_P2 A0 Pin_AA1
D6 Pin_R1 A1 Pin_Y3
D7 Pin_R2 A2 Pin_AB3
D8 Pin_U1 CS Pin_N6
D9 Pin_U2 RD Pin_AA3
D10 Pin_V1 WR Pin_AB4
EDA/SOPC SYSTEM BOARD 7843 Touch Panel Module
DCLK Pin_R6 CS DOUT Pin_T7
CS Pin_T8 PENIRQ Pin_P6
CS DIN Pin_R7
EDA/SOPC SYSTEM BOARD 12 x LED
LED1 Pin_V10 LED7 Pin_W14
LED2 Pin_W8 LED8 Pin_W13
LED3 Pin_W10 LED9 Pin_Y8
LED4 Pin_Y10 LED10 Pin_W7
LED5 Pin_Y13 LED11 Pin_Y7
LED6 Pin_V11 LED12 Pin_Y6
152
AEEDA/SOPC SYSTEM
8x7-Seg LED
BOARD
A Pin_H15 G Pin_R14
B Pin_H14 DP Pin_T13
C Pin_H16 SEL0 Pin_N17
D Pin_N16 SEL1 Pin_P17
E Pin_P16 SEL2 Pin_R16
F Pin_R15
EDA/SOPC SYSTEM BOARD 16*16 Matris LED
R0 Pin_T16 R10 Pin_U15
R1 Pin_R17 R11 Pin_U14
R4 Pin_M7 R14 Pin_V13
R5 Pin_G11 R15 Pin_V12
R6 Pin_T14 C0 Pin_V8
R7 Pin_T12 C1 Pin_U9
R8 Pin_T11 C2 Pin_U8
R9 Pin_T10 C3 Pin_T9
EDA/SOPC SYSTEM BOARD 12 x DIP-Switch
K1 Pin_W6 K7 Pin_V7
K2 Pin_Y4 K8 Pin_V6
K3 Pin_U7 K9 Pin_R5
K4 Pin_V3 K10 Pin_T5
K5 Pin_P5 K11 Pin_P4
K6 Pin_AB12 K12 Pin_AA11
153
EDA/SOPC SYSTEM BOARD 12 x Button
S1 Pin_B12 S7 Pin_A12
S2 Pin_B11 S8 Pin_A11
S3 Pin_V4 S9 Pin_V5
S4 Pin_T4 S10 Pin_T3
S5 Pin_P3 S11 Pin_AA12
S6 Pin_AB11 S12 Pin_T1
EDA/SOPC SYSTEM BOARD 4*4 KeyBoard

C0 Pin_W15 R0 Pin_U16
C1 Pin_V14 R1 Pin_V15
C2 Pin_U10 R2 Pin_Y17
C3 Pin_U11 R3 Pin_V16
EDA/SOPC SYSTEM BOARD COM
RXD Pin_AA9 TXD Pin_V9
EDA/SOPC SYSTEM BOARD PS2 Keyboard
CLOCK Pin_B9 DATA Pin_A9
EDA/SOPC SYSTEM BOARDM PS2 Mouse
CLOCK Pin_B8 DATA Pin_A8
EDA/SOPC SYSTEM BOARD USB&USB HOST
D0 Pin_B1 A0 Pin_C2
D1 Pin_C3 WR Pin_B6
D2 Pin_B2 RD Pin_A7
D3 Pin_A3 CS Pin_B5
D4 Pin_B3 INT Pin_A6
D5 Pin_A4 RESET Pin_D10
D6 Pin_B4 USBH_CS Pin_C1
154
D7 Pin_A5 USBH_INT Pin_B7
EDA/SOPC SYSTEM BOARD Ethernet
NET_INT Pin_H17 NET_SCK Pin_E13
NET-SO Pin_C10 NET_CS Pin_G17
NET_SI Pin_E12 NET_RST Pin_D10
EDA/SOPC SYSTEM BOARD Audio CODEC
AUDIO_SDIN Pin_K17 AUDIN_DIN Pin_H8
AUDIO_SCLK Pin_M16 AUDIO_DOUT Pin_M6
AUDIO_CS Pin_J17 AUDIO_LRC Pin_G10
AUDIO_BCLK Pin_J8
EDA/SOPC SYSTEM BOARD SD Card
CS Pin_AB10 DO Pin_AA10
CLK Pin_N5 WP Pin_L6
DI Pin_AB13 CD Pin_M5
EDA/SOPC SYSTEM BOARD Serial ADC
SCLK Pin_C4 CS# Pin_E7
DOUT Pin_C6
EDA/SOPC SYSTEM BOARD Serial DAC
SCLK Pin_D6 CS# Pin_C8
DIN Pin_C7
EDA/SOPC SYSTEM BOARD VGA
R Pin_AB13 HS Pin_AB10
G Pin_L6 VS Pin_AA10
B Pin_M5
EDA/SOPC SYSTEM BOARD RTC
RTC_RST Pin_F2 RTC_IO Pin_E1
155
RTC_CLK Pin_D2
EDA/SOPC SYSTEM BOARD Parallel ADC
D0 Pin_G9 D6 Pin_G13
D1 Pin_F8 D7 Pin_F13
D2 Pin_F9 D8 Pin_F14
D3 Pin_F10 D9 Pin_J6
D4 Pin_E11 CH Pin_G16
D5 Pin_F11 CLK Pin_F15
EDA/SOPC SYSTEM BOARD Parallel DAC
D0 Pin_K8 D7 Pin_J5
D1 Pin_H6 D8 Pin_G15
D2 Pin_F7 D9 Pin_G14
D3 Pin_G5 CH Pin_E5
D4 Pin_J4 CLK Pin_G4
D5 Pin_H5 WR Pin_E3
D6 Pin_J3
EDA/SOPC SYSTEM BOARD Digital temperature sensor
DS18B20 Pin_D7
EDA/SOPC SYSTEM BOARD IIC EEPROM
IICSDA Pin_E10
IICSCL Pin_E9
EDA/SOPC SYSTEM BOARD Step Motor
STEP_A Pin_H2 STEP_C Pin_J2
STEP_B Pin_H1 STEP_D Pin_J1
EDA/SOPC SYSTEM BOARD DC Motor
MT_PWM Pin_F1
156
MT_SPEED Pin_G3

EDA/SOPC SYSTEM BOARD Adjustable digital clock module CLK
CLK Pin_T2 24MHz～1Hz
Analog signal
Connect to the internal input of AD
source
EDA/SOPC SYSTEM BOARD FPGA external input/output ports
FPGA_INPUT Pin_AB13
FPGA_OUTPUT Pin_N5
EDA/SOPC SYSTEM BOARD ExpensionJP4
1 GND 21 Pin_F7
2 GND 22 Pin_H6
3 / 23 Pin_K8
4 / 24 Pin_E3
5 VCC 25 Pin_E5
6 VCC 26 Pin_C4
7 / 27 Pin_C6
8 / 28 Pin_E7
9 +12V 29 Pin_C7
10 +12V 30 Pin_D6
11 / 31 Pin_C8
12 / 32 Pin_D7
13 -12V 33 Pin_E10
14 -12V 34 Pin_E9
15 Pin_J5 35 Pin_C10
16 Pin_J3 36 Pin_D10
17 Pin_H5 37 Pin_E13
18 Pin_J4 38 Pin_E12
157
19 Pin_G4 39 Pin_H17
20 Pin_G5 40 Pin_G17
EDA/SOPC SYSTEM BOARD ExpensionJP5
1 Pin_F15 21 /
2 Pin_G14 22 /
3 Pin_G16 23 Pin_B9
4 Pin_G15 24 Pin_A9
5 Pin_J6 25 Pin_B8
6 Pin_F14 26 Pin_A8
7 Pin_F13 27 -12V
8 Pin_G13 28 -12V
9 Pin_F11 29 /
10 Pin_E11 30 /
11 Pin_F10 31 +12V
12 Pin_F9 32 +12V
13 Pin_F8 33 /
14 Pin_G9 34 /
15 Pin_G8 35 VCC
16 Pin_H7 36 VCC
17 Pin_G7 37 /
18 Pin_J7 38 /
19 Pin_K7 39 GND
20 Pin_L7 40 GND
158
159

Plateforme Cyclone IV

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EDA/SOPC CycloneIV Experiment

Hua Heng Technology Co., LTD

EXPERIMENT 1 SIMPLE EXAMPLES OF QUARTUSII ........................................................ 4

APPLICATION OF THE EXPERIMENTAL SECTION................................................ 70

EXPERIMENT 12 MATRIX KEYBOARD DISPLAY CIRCUIT DESIGN........................................ 70

COMPREHENSIVE DESIGN OF EXPERIMENTS .................................................... 121

EXPERIMENT 21 DIGITAL FREQUENCY METER DESIGN.................................................... 121

SCHEDULE I：CPU BOARD AND FPGA(EP4CE40) PIN MAPPING ...................... 145

SCHEDULE II：SYSTEM BOARD AND CPU BOARD IO MAPPING ..................... 152

computers in the computer age is not as terrible.

The experimental guide books Experiment Subject combinational circuit design

circuits through which the experimental instructions.

The experimental guide book written nearly ten representative experiment,

or as an ad hoc division of Electronic Technology reference books.

The experimental guide book with HH-SOC-EP3C40 EDA / SOPC system

development platform series products.

Experiment 1 Simple examples of QUARTUSII

2、Understand tentatively QUARTUSII principle picture inputs the whole

Table 1-1 3-8 Decoder Truth Table

III. Experiment Subject

inputting different values ' Table 1-1) Whether it is unanimous. The

intersection of experiment and stiring switch and the intersection of interface

Signal Name FPGA I/O CPU Board Pin Description

Table 1-2 DIP Switch and FPGA Pin

Signal Name FPGA I/O CPU Board Pin Description

Table 1-3 LED and FPGA Pin

IV. Experiment Step

operation of the project files, compile, pin assignment and timing

simulation through this experiment.

1) Select Start> Programs> Altera> QuartusII8.1> QuartusII8.1

(32Bit), perform QUARTUSII software. QUARTUSII icon or double-click on

the desktop software to perform QUARTUSII appears as shown in Fig 1-3,

if the software is first opened QUARTUSII information may be other prompts,

Fig 1-3 QUARTUSII software operates interfaces

project. As shown in Fig 1-4.

Fig 1-4 New Project Wizard

Fig 1-5 Project Name,directory

select CycloneIII series chips EP3C40F780C8 introduces an example.

Fig 1-6 Device Setting

configuration information, as shown in Fig 1-8, click FINISH to complete

the establishment of the new project.

Fig 1-8 New Project Information

2、Create Diagram/Schematic File

software and save it as a structure of the design file.

In QUARTUSII graphic editor window (Fig 1-10), depending on personal

unit and blocks.

jump out as shown in Fig 1-11 the Symbol dialog box.

displayed in the graphical editor work area.

5）Illustrated with reference to Fig 1-12, component symbols will be placed in

are required to follow the general rules of design input method.

Fig 1-12 The Design file

Fig 1-13 Storage Design File

QUARTUSII compiler window contains the whole process of design files

processed. Select Processing in QUARTUSII software> Compiler Tool menu item,

function of each module of the whole process of compiling 1-14.

Fig 1-14 QUARTUSII compiler window

will prompt compiled successfully, as shown in Fig 1-15.

Fig 1-15 Compile Successsful

this experiment), a comprehensive analysis of the design process is complete, after

lock. Here are two ways to pin lock.

assignment window. As shown in Fig 1-16.

Fig 1-16 Pin assignment