DESIGN OF FREQUENCY MEASUREMENT

BASED ON FPGA AND MCU

A SEMINAR REPORT SUBMITTED IN PARTIAL FULFILLMENT OF
THE REQUIREMENTS FOR THE AWARD OF THE DEGREE OF
Bachelor of Technology
In
Electronics and Telecommunication
By
ARUNDHATI DASH
Roll No: 136012
Regdn. No.:1301211146

Under the Guidance of

Prof. Sachikanta Mohapatra

Department of Electronics and Telecommunication Engineering

Orissa Engineering College
Orissa-752050
2016

i
 ORISSA ENGINEERING COLLEGE
BHUBANESWAR

CERTIFICATE

This is to certify that the thesis titled “Design Of Frequency Measurement Based
On FPGA And MCU ” submitted by Arundhati Dash in partial fulfillment of the
requirements for the award of Bachelor of Technology degree in Electronics &
Telecommunication Engineering during session 2016-2017 at Orissa Engineering
College, Bhubaneswar is an authentic work by him under my supervision and
guidance.

H.O.D. Professor Professor

Dept.of Electronics and Seminar Incharge Seminar Guide
Telecommunication Engg.

ii
 Acknowledgement

I would like to express my gratitude to my thesis guide Prof. Sachikanta Mohapatra for
his guidance, advice and constant support throughout my thesis work. I would like to
thank him for being my advisor here at Orissa Engineering College, Bhubaneswar.
Next, I want to express my respects to Prof.S.K Bisoi, Prof K Mohanty, Prof.
D.P. Moharana, Prof.M.M Das, Prof.P Mohapatra, for teaching me and also helping
me how to learn. They have been great sources of inspiration to me and I thank them
from the bottom of my heart.
I would like to thank all faculty members and staff of the Department of
Electronics and Telecommunication Engineering, O.E.C. Bhubaneswar for their generous
help in various ways for the completion of this thesis.
I would like to thank all my friends and especially my classmates for all the
thoughtful and mind stimulating discussions we had, which prompted us to think beyond
the obvious. I’ve enjoyed their companionship so much during my stay at OEC,
Bhubaneswar.
I am especially indebted to my parents for their love, sacrifice, and support. They
are my first teachers after I came to this world and have set great examples for me about
how to live, study, and work.

. Arundhati Dash
Roll No: 136012
Regn. No.: 1301211146
Dept of ENTC,OEC, Bhubaneswar.

iii
 ABSTRACT

Traditional frequency measurement based on MCU is benefit from its low-cost,

however, disadvantage which includes low precision and narrow frequency
range also exist in this kind of system.

This paper demonstrates a project which combines FPGA with MCU, fully
exert the high speed property of FPGA, the easy-calculate quality and flexible
control of peripheral of MCU, using method of equal precision.

The product offers perfect performance of frequency range of 0.01Hz~10MHz.

At the same time, this system has advantages of short reflect time and high
reliability.

iv
 Contents
ABSTRACT .................................................................................................................................. iii
Chapter 1 ....................................................................................................................................... 1
1.1 INTRODUCTION:......................................................................................................2
Chapter 2 ......................................................................................................................................... 7
2.1 MEASUREMENT THEORY: ….................................................................................8
Chapter 3 ....................................................................................................................................... 14
3.1 SYSTEM DESIGN

3.1.1 Frequency measurement

3.1.1.1 Fixed Threshold Frequency Measurement

3.1.1.2 Equal Precision Frequency Measurement

3.1.2 FPGA Module

3.1.2.1 Device Select

3.1.2.2 Device Connect

3.1.2.3 Module Describe

3.1.3 MCU Module

3.1.3.1 Device Select

3.1.3.2 Device Connect

3.1.4 ADC Module

3.1.5 Software Design

3.1.5.1 Verilog Program

3.1.5.2 MCU C Program

3.2 VALIDATION

3.3 CONCLUSION AND FUTURE WORK

3.4 ACKNOWLEDGEMENT

v
 List of Figures

Figure1. Counter And Timing Diagram

Figure2. Hardware Design

Figure3. Top Layer Structure of FPGA

Figure4. Trunk Structure Of AT89S52

List of Tables
Table1. Structure Of Hardware Of Frequency Measurement

Table. Several Signals Had Been Tested Based On This Device

vi
 CHAPTER -1

INTRODUCTION

A field-programmable gate array (FPGA) is a semiconductor device that can be

configured by the customer or designer after manufacturing.

FPGA are programmed use a logic circuit diagram or a source code in a hardware
description language (HDL) to specify how the chip will work.

FPGA especially find applications in any area or algorithm that can make use of
the massive parallelism offered by their architecture.

A microcontroller unit (MCU) is a small computer on a single integrated circuit

consisting of a relatively simple CPU combined with support functions such as a
crystal oscillator, timers, watchdog, serial and analog I/O etc.

Microcontrollers are used in automatically controlled products and devices.

We can find that our design purpose can be divided into two parts. First part can be
handled by FPGA which is good at massive parallelism operation. MCU deal with
the second part, which calculates the result and control the LCD to display it.

vii
 CHAPTER-2

MEASUREMENT THEORY

As shown in Figure 1, the theory of a counter is to set a threshold time and count
how many signal cycles have been included

viii
 CHAPTER-3
SYSTEM DESIGN

For hardware designs, as shown in figure 2.We combines FPGA and MCU to be
the core of the system. Data wire,control signal and address bus connect these two
maindevices.

The input signal gets into the FPGA through an A/D. FPGA will generate an inside
permanent clock and compare with the exterior input signal. Results will be sent to
MCU, then be calculated and be displayed though a LCD.

A. Frequency measurement
To hardware designs. We have two optional methods about frequency
measurement .
 Fixed threshold frequency measurement.

This is a normal method which set a permanent time to count how many cycles of
input signal in this period. Unfortunately, if the moment the threshold is closed is
not the time input signal level change. This would make a count error of 1 in
register. In high frequency circumstances, this error is acceptable as it have no
obvious effect on result; however in low frequency, this is a serious problem which
ix
leads to unacceptable error.

 Equal precision frequency measurement

A D flip-flop is designed with a clock of input signal; another input of D flip-flop

is EN. Therefore, the D flip-flop assign the value of EN to q, when q=1, all the
counters is enabled, on the country, when q=0, all the counters disabled.
By this D flip-flop, the counters is synchronized which avoid the error. In
summary, we decide to adopt equal precision frequency measurement.

B. FPGA Module
 Device Select
Xilinx and Altera are two main FPGA manufactures among the word. However,
consider about the cost, we chose ProASIC3 from ACTEL whose price is more
reasonable, and the chip resource is just full fill our need. The IDE(independent
development environment ) of ProASIC3 provides a complete, multiplatform
design environment that easily adapts to our design needs.

 Device Connect
The top layer structure of FPGA is shown in figure 3

x
  Module Describe
In this module, there are three 32-bit registers:
counter base (the basic clock counter with overflow bit), counter half (the basic
half-clock counter with overflow bit), counter_f_in (the counter of input signal), a
D flip-flop, a clock divider (to implement half-clock), a data selection
multiplexer (output the data in serial), a flag bit of count
finish.
The source clock we connect to FPGA is 48MHz. After the count process has been
finished, the program checks the overflow bit of counter half. If set, then set error
bit, otherwise, read data of all the counter register. Suppose that the value of
counter base is A, the value of counter half is B, likewise, counter_f_in is C. If the
overflow bit of counter base is set, the frequency of input signal is F=
24000000 * (C / B); on the country, F= 48000000 * (C / A).
As the frequency range is as wide as 0.01Hz~10MHz, if we adopt the cycle
measurement or frequency measurement independently, the precision of result
would not be desirable. Therefore, we use cycle measurement in low frequency
range, and frequency measurement is used in high frequency range. To realize this
scenario, the software deal with signal EN and q, the two modes can be switched
automatically. The step is as follow: after the system’s reset, set EN, delay a little
time (we set 120ms), wait until q is set, clear EN, Wait until q is clear. When the

xi
input signal is in high frequency, there is at least 1 cycle in this delay period, this is
frequency measurement, we can use computational formula above.
However in low frequency, delay time is not enough to get the trigger of input
signal, so we have to wait a little longer to get the change of q, therefore we get at
least 1 cycle of input signal. The counter_base register count how many 48MHz
clock have in this 1 cycle, this belong to cycle measurement.

C. MCU module
 Device Select
According to the project need, we choose AT89S52 as the MCU which is easy to
program. Because of continuously usage before, we could complete design in short
time.
 Device Connect
As shown in figure3, the connection of AT89S52 is divided into two parts. The
signal which control LCD and the signal communicate with FPGA.
The control signal of LCD is defined as R/S, R/W, E, also, the 8-bit data bus
provide the write address and data.
The signal communicate with FPGA include RST, SEL, out, error, EN, carryout,
which can be corresponding to the connection of FPGA.

D. ADC module

Since ADC module is not the innovate part of this design, it is omitted here
because of the length of paper.

E. Software design

 Verilog Program
as shown in table 1, verilog program establish the structure of hardware of
frequency measurement.

xii
  MCU C program
Figure 4 is the trunk structure of program of AT89S52

xiii
VALIDATION

xiv
As we establish the whole system, several signals had been tested based on this
device. As shown in table 2.

The left volume is the set value of function generator, the middle volume is the
value of frequency measurement machine in lab, and the right volume is the
performance of our system. The unit is Hz. From the data shown before, we can
find that, at most of the time, our system is better than the device in lab.

xv
CONCLUSIONS AND FUTURE WORK

As undergraduates, when we took over this project, our heart is in fear and
trembling, as we have no acquaintance with FPGA. After theory learning and a
large number of testing, our production meets the requirements. The perfect
performance of FPGA in high frequency makes the work easier, and completes the
function which discrete components can’t achieve. To simplify the system and
reinforce the reliability, further work can be done on the Soft-Core Processor like
NIOS II from ALTERA which could make a processor in a FPGA. With more
flexible configuration and compact system, the precision can be increased and the
reaction time could be reduced.

xvi
 REFERENCES

[1]. http://en.wikipedia.org
[2]. Samir Palnitkar, Verilog HDL A Guide to Digital Design and
Synthesis Second Edition, Prentice Hall PTR , March 20

xvii