Sei sulla pagina 1di 74

Introduction to Electronics

Part - II

Mrinal K Mandal
mkmandal@ece.iitkgp.ernet.in
Department of E & ECE
I.I.T. Kharagpur. 721302.
www.ecdept.iitkgp.ernet.in
1
Bipolar Junction Transistor (BJT)
• One of the most important inventions (John Bardeen, Walter Brattain and
William Shockley at AT & T Bells lab, got Nobel in 1956).
• It has three layers (npn or pnp): two pn junctions.
• A three terminal device: emitter, base and collector.
• Main applications: amplifiers, oscillators, switches, logic gates.

Bardeen n n p
p

Base
E C

p n p
B Emitter Collector
Brattain
Shockley
BJT
The first transistors. 2
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Bipolar Junction Transistor (BJT)
B (base) B
Base
E p n p C E n p n C

(emitter) (collector)
emitter collector
C C
Conventional
B current flow B
direction
E E
Analogy with a water tap point.
pnp- transistor npn- transistor

E
E

BJT with a heat sink


Different types of transistors. 3
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
BJT
• Two pn junctions: barrier voltages are negative on the p-side and positive on
the n-side.
• Bipolar device: two types of charge carrier are involved in the current flow.
• The base region (mid-layer) is thin and lightly doped.
• The emitter emits electron in npn, holes in pnp and collector collects them.
• In normal operation, the emitter-base junction is forward-biased: carrier
injection.
• The collector-base junction is reverse-biased, its depletion region penetrates
deep into the base.
emitter base collector C

+ - C
E B
+ -
p n p
+ - E
+ -
VEB VBC pnp- transistor

Holes are the majority charge


carriers in an pnp device.
pnp- transistor biasing 4
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
BJT Operation
emitter base collector C
- + C
E B
- +
n p n
- +
- E
VBE + VCB
npn- transistor

Electrons are the majority


npn- transistor biasing charge carriers in an npn device.

• Forward bias base-emitter junction works as a diode: majority carriers electron


in n-type emitter drift into p-type base.
• Holes also drift from base into emitter small because the base is thin and
lightly doped.
• The electrons diffused into the collector-base depletion region they are
drawn across the collector-base junction collected at the collector terminals
(~96-99.5%).
• In the bas region, a small percentage of the injected electrons recombines
with holes base current. 5
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
BJT Voltages and Currents
IC IC
RC RC
- IB C + +
IB C - B
B VCC
VCC + VCE
- - VEC -
VBB RB VEB + + VBB RB VBE -
+ E IE
+ E IE -

pnp-transistor biasing: common npn-transistor biasing: common


emitter (CE) configuration. emitter (CE) configuration.

Applying KCL, I E  I C  I B
IE IC
Common emitter current gain:  dc  I C I B .
+ RC +
Common base current gain:  dc  I C I E . VCC
VEE RB
 IB IB
IC    IC  I B   IC  . - -
1
  npn-transistor biasing: common base
IC   I B     . (CB) configuration.
1  1 6
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Different Configurations
IC
RC IC
+ IE
IB C +
B VCC + RC +
+ VCE
- VEE RB VCC
VBB RB VBE - IB
E IE - -
-

Common base (CB) configuration.


Common emitter (CE) configuration.

IE
RC
IB E + +
B VCC
+ VCE
-
VBB RB VBE -
C IC
-

Common collector (CC) configuration.


7
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
BJT Characteristics: Input Characteristics
IC 30
A
RC 20
RB + IB (μA)
IB + 10
VCC
+ A V VCE
- 0
+ - 0 0.3 0.6 0.9
VBB VBE V IE
A VBE(V)
- -
Input characteristics of a npn-
transistor in CE configuration.
npn-transistor in common emitter (CE)
configuration.
30

• Input parameters: I B , VBE 20


IB (μA)
• Output parameters: I C , VCE 10

0
 VBE  0 -0.3 -0.6 -0.9
• Base current: I B  I B 0 exp   VBE(V)
 T 
V
Input characteristics of a pnp-
transistor in CE configuration.
8
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
BJT Characteristics: Output Characteristics
Input loop: DC load line
VCC /RC IB = 40 μA
Applying KVL,
VBB  I B RB  VBE 15 = 30 μA
Saturation
region Active
Output loop: 10 = 20 μA region
IC (mA)
Applying KVL,
Q-point = 10 μA
VCC  I C RC  VCE 5
V V = 0 μA Cut-off
 I C   CE  CC . load line region
RC RC 0
0 4 8 12 VCC
At I C  0, VCE  VCC and VCE (V)
VCC Output characteristics for a npn
at VCE  0, I C  . transistor in CE configuration.
RC
• Active region: base-emitter junction is in FB but base-collector junction is in
RB., Saturation region: both junctions are in FB, Cut-off region: both are in RB.

IC

IE
IC
• A saturation current component IC = ICBO flows even for IB = 0.    

B
O
• Consider VCE|sat = 0.2 V, if the transistor in saturation. 9
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Some Important Characteristics
• In active region, collector current IC is almost independent of VCE: constant
current source.
• IC can be tuned by IB (linear model, function of VBE): voltage controlled current
source.
• IC is mostly due to the flow of charges injected from a high-concentration
emitter into the base where there are minority carriers that diffuse toward the
collector: a minority-carrier device.
• When using as an amplifier, the DC source supplies the energy required to
amplify a signal: fix the dc operating point (Q-point) first.
• Linear approximation (output is an exact replica of the input signal) is valid only
for small signal amplitudes.

Non-linear device:
Does not have a linear relationship between current and voltage.

Examples: diode, transistors.


I
I0

V
VT
e
x
p

  
10
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Voltage Amplification
• A BJT works as an amplifier Saturation
only in active region and under region
VCC /RC IB = 40 μA
proper biasing condition.
• In a class A amplifier, Q-point is IC (mA) 15 = 30 μA
so selected that a BJT always Active
remains in the active region. ic ib
10 = 20 μA region
• Slope of the load line and
t (mS) = 10 μA
hence voltage amplification
5
depends on RC.
= 0 μA Cut-off
• In CE configuration, when the region
0
input voltage (vbe) increases, 0 4 8 12 VCC
the output voltage (vce) VCE (V)
vce
decreases.
t (mS)
Output characteristics for a npn transistor in
CE configuration.

• Maximum possible variation in VCE =


VCC - 0.2 V
11
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Why Need Biasing?

In the following circuit, IB changes by 10 μA because of a VBE change by 20 mV.
Calculate the change in VCE. Given that β = 100.
IC
Solutions: RC = 6 kΩ
I C  I B  100  20  A  2 mA. VCC =
VCE  I C RC  2  6 VBB = 0.7 V VCE 20 V
12 V . vb  20sin t mV
VBE
IE

40
Linear
approximation • Biasing: to set the dc
IB (μA) operating point.
• IC = βIB, only in active region.
0
0.7
VBE(V) In lab. experiment, don’t forget to
switch on the dc power supply.
Input characteristics of the BJT.
12
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
BJT in Saturation

In the previous example, recalculate the change in VCE if RC is changed to 12 kΩ.

IC
Solutions: RC = 12 kΩ

I C  I B  100  20  A  2 mA. VCC =


VCE  I C RC  2  12 VBB = 0.7 V VCE 20 V
 24 V ( VCC )  wrong . VBE
vb  20sin t mV IE

High IB drives the BJT in saturation.


Considering maximum possible variation,

VCE max  VCC  0.2


 19.8 V Neglecting the contribution of ICBO.

13
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
BJT In Saturation
IC
Calculate IB and IC. Given that β = 100, RB =
10 kΩ, RC = 1 kΩ, VBB = 5 V and VCC = 12 V. RC
IB C + +
Solutions: B VCC
+ VCE
Applying KVL in the input loop, -
VBB RB VBE -
E IE
VBB  I B RB  VBE -
VBB  VBE 5  0.7
 IB    0.43mA.
RB 10k
+VCC
 I C   I B  43mA  IC
 wrong. RC
 VCE  VCC  I C RC  12  43  31 V ?
IB +
So, the transistor is in saturation. +VBB VCE
RB VBE -
Applying KVL in the output loop, IE

VCC  VCE 12  0.2


IC    11.8 mA. npn-transistor in CE configuration.
RC 1k
14
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
BJT Biasing
• Biasing: setting up the dc operating point (quiescent point).
• Minimize number of dc sources, increase stability of the circuit (eg. VBE and ICBO
depend on temperature, β varies widely from transistor to transistor).
• Three popular biasing schemes:
1. Base bias
2. Collector-to-base bias
3. Voltage divider bias.

Analysis objectives:
• Draw the dc load line (apply KVL for the input and output loops, assume
suitable VBE value)
• Identify Q-point (IBQ, ICQ, VCEQ)
• Estimate the maximum variation of the output voltage.

15
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
1. Base Bias
Input loop: +VCC
R
IB IB
VCVC

V VB
 
B

C C

B
E
IB IC

.

E
RB
  RB RC
vout
+
In forward active region: vin VCE
+
ICVB

IB0
, 7

VBE -

.
V
S
i
,
0
.
3
V
G
e
.
- IE
 ︵ ︶ ︵ ︶
E

Base bias configuration (npn-BJT).


Output loop:
R
IC IC
VCV

VCV

  DC load line I = 40 μA
C

C C

E C

VCC /RC B

C

E
RC C

 
Q

15 = 30 μA
VC

VC

R
IC
.

   = 20 μA
E
Q

10
IC (mA)
A
t
IC VC

VC IC

VCVCRC

Q-point
0
,

= 10 μA
Load line:   5
E

C
VCR

VCR

= 0 μA
IC

0
,

.
.

C
E

C C

    0
E

0 4 8 12 VCC
C

VCE (V) 16
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Base Bias
Calculate the Q-point values (β = 100). +18 V
IC
IB
Solutions:
VC

VB A.
2.2 kΩ
IB

1
8

0
.
7
 
C

470 kΩ
RB

  +
Q

3
4
7
0

1
0
 VCE
Assuming +
-
3
6
.
8 IB

  active condition. VBE


IC

m
A

IE
3
.
6
8

-
 
Q

Q
VC

VC9

R
IC

1
8
3
.
6
8
2
.
2
    
E
Q

C
. 9
V
.

Assumption is correct.

Recalculate the Q-point values for β = 50.


1
.
8
4
m
A
. 3
I C VC

I B VC

A BJT with the same number


 
Q

may have wide variation of β


R
I

1
.
9
5
V
.

   (high manufacturing tolerance)


E
Q

C
C

VCEQ changes by 41% when β changes by 50%.


17
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Base Bias
-18 V +18 V
+ IE
IB IC VEB +
2.2 kΩ - VEC
470 kΩ - -
IB
VEC
-
+ 470 kΩ IC 2.2 kΩ
VEB
+ IE

pnp transistor in base bias configuration.

In the above circuit, Vcc is changed to 12 V. Calculate the new Q-point (β = 100).
VC

VC6

R V
IC

1
2
2
.
4
2
.
2
VC

VB

R B RB
IBVB

E
Q
    

C
 
C

. 7
2
.
VC A

1
2
0
.
7


IB

 
C

4
7
0
1
0

  
Q


2
4
.

  The transistor is working in the


forward active region.
2
.
4
m
A
.
IC

IB

 
Q

18
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Base Bias Circuit Design
Determine the resistor values for the specified Q- +VCC
value.
IB IC
Input loop: RB RC
R
IB RB

VC VC

VB VB
vout
  +
B

IC
vin VCE

IB
p
u
t

.
   +

Q
C

-
IB

  

Q
 VBE
 
Q

 - IE
In forward active region:
VB

0
.
7
V
S
i
,
0
.
3
V
G
e
. Base bias configuration (npn-BJT).
 ︵ ︶ ︵ ︶
E

Output loop:
VC

VC Q
R
IC

VC

VC

RC

.

C

E
Q
IC

   
C

E
Q

Design a base bias circuit using a Si transistor with β = 100 to set the Q-point at
ICQ = 5 mA and VCEQ = 6 V. Use VCC = 12 V.
IC
IB

VB

RB

RC
5
0
μ
A
.

0
.
7
V
.

2
2
6
k
a
n
d

1
.
2
k
.
Q

Solution:        
E


19
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
2. Collector-To-Base Bias
+VCC DC load line I = 40 μA
VCC /RC B

RC (IC+IB)
15 = 30 μA
IB
RB 10 = 20 μA
vout IC (mA)
+
Q-point = 10 μA
vin VCE 5
+
VBE - = 0 μA
- IE 0
0 4 8 12 VCC
npn transistor in collector-to- VCE (V)
base bias configuration. Output loop:

VC

R
IC C
IBV 1 R

V
   

C
E
C
V
Input loop:

IC

C1

C
E
RC V
 

Q
load line
Applying KVL,   
VC IC V C

IC
1
1

.
     
VC

RC
ICV
I B RC

RB 1
IB .
VB

E
Q

CV
C

C VC
 
A
t
  
0
,
C

E
VB

 

C IC
E

C
IC

IB
.
IB

VC1

VCR

C
C

E
RB

0
,

.
  where 

C
  
RC

1
   
E

  

C
20
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Collector-To-Base Bias
+VCC DC load line I = 40 μA
VCC /RC B

RC (IC+IB)
15 = 30 μA
IB
RB 10 = 20 μA
vout IC (mA)
+
Q-point = 10 μA
vin VCE 5
+
VBE - = 0 μA
- IE 0
0 4 8 12 VCC
npn transistor in collector-to- VCE (V)
base bias configuration.

The change in resistor position improves bias stability.

Negative feedback effect:


• IF IC increases above the design level, VCE decreases.
• The reduced VCE level causes IB to be lower than the design value.
• Because IC = βIB, IC tends to decrease.
21
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Collector-To-Base Bias
+18 V
Calculate the Q-point values for β = 100. Calculate
the new values if β is changed to 50. (IC+IB)
2.2 kΩ
IB
Solutions:
270 kΩ vout
+
For β = 100: For β = 50: vin VCE
+

VC 3

VB
VC 1

VB

IB
VBE
IB

E

C

RB4

RCA B 8

1
 IE
RB5

RCA

 -
       

5
.
μ
.
3
.
μ I
.

npn transistor in collector-to-


 
IC

I
2
.
3
1 IC
m
A
. IB
base bias configuration.
IC

3
.
5
1 IC
m
A
. IB

  
Q

  
Q

VC

VC1

RCV
VC

VC1

RC.

      
E
Q

C.
  
E
Q

C.

2
2
.
0
2
V

 

• Observe that the change in Q-point values in comparison to base-bias case is


much smaller.
• In this case IB is also a function of β.
22
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Collector-To-Base Bias
In the above circuit, Vcc is changed to 12 V. +12 V
Calculate the new Q-point values (β = 100). +
IE
VBE +
Solutions: vin -
VEC
VC μ

VB
IB

270 kΩ IB

C

-
RB3

RC. B 9

1
 vout
   
2
A

(IC+IB) 2.2 kΩ

IC

I
2
.
3
m IC
A
. IB

  
Q
VC

VC6

RCV

pnp transistor in collector-to-


    
E
Q

C8

base bias configuration.


.

23
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
R
IB Collector-To-Base Bias Circuit Design
VC

VB V B
  +VCC
B

E
Q

E
Q

IC
p
u
t

0
.
7
V
f
o
r
S
i
,
IB

VB
VC
 

Q
(IC+IB)

.
RB

  RC

E

E
Q

E
Q
 
IB
   IB

0
.
3
V
f
o
r
G
e
 
Q

  RB
VCI

VCIC

vout
.

+
RC


C B

E Q
Q

 vin +
VCE

Q

VBE -
- IE

npn transistor in collector-to-


base bias configuration.

Design a collector-to-base bias circuit using a Si transistor with β = 100 to fix the
Q-point at ICQ = 5 mA and VCEQ = 6 V. Use VCC = 15 V.

Solution:
IC
IB

VB RC
5
0
μ
A
.

0
.
7
V
.
Q

   
E


RB
1
0
6
k
a
n
d

1
.
7
8
k
.

   
24
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
3. Voltage Divider Bias
• Most stable biasing scheme among the +VCC
three.
• R1 and R2 form a voltage divider. I1 R1 RC IC
IB
• I2 >>IB  VB remains almost constant. +
VB
+ VCE
+VCC VBE -
-
I2 R2 RE IE

I1 R1
I1 = I2
VB VTh npn transistor in voltage divider
bias configuration.
I2 R2 RTh

The voltage divider and its Thevenin equivalent.


R 1R 1
R 2R

R2
RT

R1
R2

VT

VC
|
|

a
n
d

.
R1
R2

   
h

 
2

25
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Voltage Divider Bias: Analysis
Input loop: +VCC
VT

RT
Ih
VB hR

RE E
IB
IC
RC IC
     
h

E
VT

VB

IC

IB
IB

.
 IB +
RT

1
  where 
    +
h

VTh VCE
VBE -
-
RTh RE IE
Output loop:
VC

R
IC R CV
VC CR

RE E1
IB
ICVCR
     
C

E
VC

VC1

VCR .B Voltage divider bias using the


IC VC

 
C CR

E
   Thevenin equivalent.
Q

load line
    
E

E
RC

RE
IC

     
E
Q

C
C

E
A
t
IC V C

VC I C

VC
0
, 0

 
E

VCRC

VC
,

.
C1

C
RE

RE

RC
1

  
E

    

26
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Voltage Divider Bias

DC load line I = 40 μA
VCC /(RC+RE) B

15 = 30 μA

10 = 20 μA
IC (mA)
Q-point = 10 μA
5
= 0 μA
0
0 4 8 12 V
CC
VCE (V)
Load line and the Q-point on the
output characteristics.

27
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Voltage Divider Bias
Calculate the Q-point values for β = 100. +18 V
Recalculate the values for β = 50. A Si
transistor has been used. 1.2 kΩ IC
33 kΩ
IB
Solution: +
For β = 100: + VCE

R2
VBE
RT

R 1 V h.
R2

VT

VC
|
|

8
.
8
k
Ω
a
n
d

=
4
.
8
V
.
-

R1
R2
   
h

C
12 kΩ 1 kΩ IE

VB A R
IB

3
7
.
3
μ
A
.

T
h

E
RT 3

RE m

 
    npn transistor in voltage divider
IC

7
3

  bias configuration.
VC

VC

RE
IC
RE
IB
9
.
7
6
V
.

VB a
VB a

VBRE
      IC
IE r

IC n

IE t

.
E
Q

 

E
REs

VB    
e
m
i
n
l
m
o
s
t
c
o
s
t
a
n
.
For β = 50: 
IB V C

IC
6
8
.
6
μ
A
.

3
.
4
3
m
A
.

   Introduction of an emitter resistor RE


1
0
.
3
9
V
.

 greatly improves the biasing stability.


E
Q

28
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Voltage Divider Bias Design
+VCC

IC RC
I1 R1 RC R1
IB VC IB
+
VB
+ VCE
VBE - VE
-
I2 R2 RE R2 RE
IE

npn transistor in voltage divider Equivalent circuit as seen by


bias configuration. any AC source.

• VB should be stable  I2>>IB.


• Avoid low input impedance  choose low I2 (because R1||R2 w.r.t. the input
terminals).
• VE>VBE.

29
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Voltage Divider Bias Design
Approximations: +VCC
I 2I 1 RE
ICI 2

VE
1
. 2

1
0

3
.

3 5
V V
f
o
r t
V Ce

5 e
V
  

Cw
IC
.

o
h
r
i
s
.
I1 R1 RC
 
IB VC
VEIE C

+
, VI 1

  VB
+ VCE
Q
VC VBI 2 VC

VE

VBE - VE
R

  -
C E 0
E
Q


C

I2 R2 RE IE
Q
VB

VE

 
R


E
QI
Q

 
2

npn transistor in voltage divider


C
QV

VBIC

VE
VB

bias configuration.
 
R

1
0

 
C
C

E
Q
C

Q
I2

 
1

Design a voltage divider bias circuit using a Si BJT with β = 100. Fix the Q-point at
ICQ = 5 mA and VCEQ = 5 V. VCC = 15 V.
Answers:
RE

k 4
R ,

k 8
1 1
, k

1 1
, 6

     Choose nearest available values of


C
R2

R1

k
1
.

resistors.
    30
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Bias Stability
250C
• VBE decreases by 1.8 mV (Si) and 2.02 mV
30
(Ge) for 10C rise in temperature. 500C 00C
• ICBO doubles for every 100C rise in 20
temperature IB (μA)
10
• β (hFE) widely varies from transistor to
0
transistor. 0 0.3 0.6 0.9
VBE(V)
Effects:

1. Q-point is changed. +VCC


2. Thermal runway.
R1 ICBO RC
Thermal runway:
IC

IE
IC

+
 
B
O

+ VCE
If ICBO increases, IC increases  increases VBE -
-
temperature of the device  cumulative effect  R2 RE
can permanently damage the device (burn out).
• Rule of thumb: take ∆vcemax < VCC/2.
31
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Thermal Stability
+VCC
• Change in ICBO can permanently damage the
device  ICBO is the most important parameter. IC
I1 R1 RC
IB VC
Stability factor: +
ICIC

VB
S

 + VCE
 VBE
 -
B
O

- VE
I2 R2 RE IE
• S depends on the circuit configuration and
the bias resistors.
npn transistor in voltage divider
• S should be as small as possible. bias configuration.
S

• Base bias:  1 R C RE


S


RC

RB
1

• Collector-to-base bias: 
   
1
S

• Voltage divider bias: 


RE

R1
R2
1

|
|


   
32
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Thermal Stability
+18 V +18 V
+18 V
2.2 kΩ 33 kΩ 1.2 kΩ
2.2 kΩ
470 kΩ +
+ 270 kΩ + + VCE
VCE
+ VCE VBE
- +
VBE - -
VBE
- 12 kΩ 1 kΩ
-

Base bias configuration. collector-to-base bias voltage divider bias


configuration. configuration.

Calculate the stability factor for the three biasing schemes. In each case, the
same Si transistor with β = 100 has been used.

• Base bias: S = 101


• Collector-to-base bias: S = 56
• Voltage divider bias: S = 9.
33
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Diode Compensation
VCC
The diode can compensate for the changes in VBE.
VB

VRVB

VDVE V
 
2

R1 RC
 
E

+
VDR
VB
IC
IE

  +
R

E
2

   + VCE
VD
E

VBE
VRR

- - -
.
2 E

R2 RE
 [If the two junctions have similar
characteristics]
voltage divider bias
configuration with diode
compensation.

34
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
AC Analysis of BJT Circuits
+VCC +VCC +VCC

R1 RC R1 R1 RC
IB IB
C1
VB
+ +
vs vs vs
VBE VBE
- -
R2 RE Rs R2 R2 RE
Rs Rs

Signal source incorrectly VB is changed by the Signal source capacitor-


direct-coupled to the direct-coupled signal coupled to the circuit.
circuit. source.

Direct-coupled: Capacitor-coupled:

R2
RS

R2 |

VB

VC

.
VB

VC

|
|RS

R1
R2
(DC condition)  C
R1

R2
.


C


|


• Always use a coupling capacitor C1
• Signal source changes the Q-
to avoid the change in Q-point by
point.
the signal source. 35
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
AC Analysis of BJT Circuits
+VCC +VCC +VCC

RC
R1 RC RC VC R1 C2
C1 C1

RL vs RL
vs RL

R2 RE RE Rs R2 RE
Rs

Load is incorrectly direct- VC is changed by the Load capacitor-coupled to


coupled to the circuit. direct-coupled load. the circuit.

Direct-coupled: Capacitor-coupled:
VC

VC

IC
RC
.
RL
VC

VC

 

C
RC

RL


C


• Always use a coupling capacitor C2
• Direct-coupled load changes the
to avoid the change in Q-point by
Q-point.
the load.
36
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Negative Feedback and AC Degeneration
 If IC increases above the design level, VCE +VCC
decreases. RC
 The reduced VCE level causes IB to be lower RB /2 RB /2
than the design value.
 Because IC = βIB, IC tends to decrease.
 So, voltage change at the collector is fed back
to the base, where it tends to partially cancel CB
the signal.
 For collector-to-base bias RB and for voltage +VCC
divider bias RE are the feedback resistors.
RC
 The above effect produces good bias stability. R1 C2
C1
• The same reaction occurs when an ac signal
RL
is applied to the circuit for amplification. CE
RE
 very low voltage gain. Rs R2
• AC bypass capacitors are connected to avoid
the above effect. Corrected circuits.
37
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
AC and DC Equivalent Circuits
+VCC +VCC

RC RC
R1 C2 R1

C1
RL vs RC||
vs R1||
CE RL
RE R2
Rs R2 Rs R2 RE

The amplifier circuit. AC equivalent circuit of the DC equivalent


amplifier. circuit of the
amplifier.
• AC equivalent circuit: replace all the capacitors by short circuits (assume the
capacitance to be high).
• DC equivalent circuit: replace all the capacitors by open circuits (capacitors
block dc signal).
• RC acts as a load in the ac equivalent circuit when external load RL is absent.
• Draw a new load line for the ac source: ac load line. 38
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
AC Load Line
AC load line
Q-point is fixed for the AC as well as DC load line I = 40 μA
B
DC load lines. VCC /(RC+RE)
15 = 30 μA
Consider extreme scenario:
ICI
W
h VCA
e
n

c
h
a
n
g
e
s
t
o
z
e
r
o
,
10 = 20 μA
IC (mA)
Q

RC

RL
c vc
o
n
s
i
d V
e
r

. RC
Q-point = 10 μA
     5
Et

C
Q
i

IC
0

.
= 0 μA
    
c

e
Q

C
E
Q

Q 0
0 4 8 12 VCC
VCE (V)
VCEQ + ICQRC

DC and AC load lines on the output


characteristics.

• DC load line remains the same as before.


39
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
AC Load Line
Draw the DC and AC load line for the following +18 V
amplifier (Si BJT with β = 100).

Solutions: 33 kΩ 1.2 kΩ

DC load line: +
VC

VC1

VCR V

VCR
IC A

  + VCE
CR

E
RC 0

 
Q t

VBE
    
E

E
-
IC VC

VC RE
, 0

1
8

12 kΩ 1 kΩ
  
C IC
E

CV

1
8 1
,

8
.
1
8
m
A
.
C
C
RC
1
.
2

   
E

  voltage divider bias


configuration.
AC load line:
Calculate the Q-point values first.
ICVc

m IC3
A
a RC
n
d
VC
3
.
7 Q7
3

, Q7 .

9
70
.
6.
V
.
 
Q

E
Q

From slide 26:


A
t
ic

VC9

RL
0
,

      
e

V
.
6
.
3
1
.
2

  
1
4
.
2
4
V

 40
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
AC Load Line (cont...)
AC load line
DC load line I = 40 μA
8.18 B +VCC
vC
= 30 μA vB (V)
(mV) RC vo
R1 C2 (V)
3.73 = 20 μA
vs
Q-point = 10 μA (mV) C1 vE
IC (mA)
(mV) RL
= 0 μA vs
RE CE
0 R2
0 9.76 18 Rs
VCE (V)
14.24

DC and AC load lines on the output The amplifier circuit.


characteristics.

• Note that under any condition IC cannot be more than 8.18 mA (assuming
biasing circuit remains unaltered).

41
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Hybrid-π Model

VBvBvb
:
D
C
v
a
l
u
e
,
E
• Assume linear device: only for small signal

:
t
o
t
a
l
i
n
s
t
a
n
t
a
n
e
o
u
s
v
a
l
u
e
,
 Valid only in forward active region.

E
:
i
n
s
t
a
n
t
a
n
e
o
u
s
A
C
v
a
l
u
e
.
e
Small signal parameters:
1. Input resistance rπ (Ω),
• Input parameters: ib, vbe.
2. Current gain β (dimension less),
• Output parameters: ic, vce.
3. Output resistance r0 (Ω),
4. Transconductance gm (Ω-1). ic

1. Input resistance rπ: +


c
h
a
n
g
e
i
n
i
n
p
u
t
v
o
l
t
a
g
e

ib
r
c
h
a iB B
n
g
e
i
n
i
n
p
u
t
c
u
r
r
e
n
t

  vce
+
Q
-
p
o
i
n
t
1r 1r

vbe
ie
 - -
v



E
Q
-
p
o
i
n
t


ibvb

BJT as a two-port
 device.
e
Q
-
p
o
i
n
t


42
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Hybrid-π Model

VT
vbib
r

VT
,

i
s
t
h
e
t
h
e
r
m
a
l
v
o
l
t
a
g
e
,
30
e 

IC
    IBQ 1/rπ

Q
Q
-
p
o
i
n
t
20

VTIC
IB (μA)
r
re
,e

c
a
l
l
e
d
t
h
e
e
m
i
t
t
e
r
r
e
s
i
s
t
a
n
c
e
.
10
  Q

0
0 0.3 0.6
VBEQ
• rπ is also called the diffusion resistance. VBE(V)
• It is a function of the Q-point. Calculation of rπ from the
input characteristics.
2. Current gain β: IB = 40 μA
c
h
a
n
g
e
i
n
o
u
t
p
u
t
c
u
r
r
e
n
t

15 = 30 μA
c i i icib
h
a
n
g
e
i
n
i
n
p
u
t
c
u
r
r
e
n
t


Q
-
p
o
i
n
t

10 = 20 μA
IC (mA)
Q-point = 10 μA

C B

 5
= 0 μA

Q
-
p
o
i
n
t .

0
0 4 8 12 VCC
VCE (V) 43

Q
-
p
o
i
n
t

Calculation of β.
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Hybrid-π Model
3. Output resistance r0: IB = 40 μA
c
h
a
n
g
e
i
n
o
u
t
p
u
t
v
o
l
t
a
g
e
r0

15 = 30 μA
c
h vi
a
n
g
e
i
n
o
u
t
p
u
t
c
u
r
r
e
n
t

= 20 μA

Q
-
p
o
i
n
t
IC (mA) 10
Q-point = 10 μA

C C
E

5
 = 0 μA

Q
-
p
o
i
n
t

0
12 VCC
vcic V IC

0 4 8
VCE (V)
e


Q
-
p
o
i
n
t h

Calculation of r0.
VA
w
e
r
e

i
s
t
h
e
E
a
r
l
y
v
o
l
t
a
g
e
.
A Q

• Consider r0 as infinite if unspecified.

44
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Hybrid-π Model
4. Transconductance gm:
c
h
a
n
g
e
i
n
o
u
t
p
u
t
c
u
r
r
e
n
t
30
gm

IBQ
c iCvB
h
a
n
g
e
i
n
i
n
p
u
t
v
o
l
t
a
g
e
 1/rπ
20

Q
-
p
o
i
n
t
IB (μA)
 10


E
Q
-
p
o
i
n
t

0
0 0.6
i

0.3
VBEQ
c
vb ICVT1 re

 VBE(V)
e
Q
-
p
o
i
n t

Calculation of rπ and hence gm


VT
w
h
e
r
e
i
s
t
h
e
t
h
e
r
m
a
l
v
o
l
t
a
g
e
Q

from the input characteristics.



1000
βdc
.

 100 0.707βdc
|β(jω)|
ICVT
VT C
r r
gm gm

10
N
o
w
,


Q
I

   
Q
.

1 fβ 1000
0 500 fT
  
Freq. (kHz)
• Three parameters are required. Frequency variation of β.
45
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Hybrid-π Model
ic
ib ic
+ B C
ib + +
vce βib= gmvπ
+ vbe rπ vπ g v r0 vce
m π
vbe
ie E
- - - -

BJT as a two-port device. Small signal hybrid model of a npn


transistor in CE configuration.
ic
ib ic
- B C
ib - -
vce gmvπ
- vbe rπ r0 vce
vbe vπ
ie E
+ + + +

BJT as a two-port device. Small signal hybrid model of a pnp


transistor in CE configuration. 46
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Calculation of Voltage Gain
+VCC

RC RB
B C
RB + +

vi rπ vπ gmvπ r0 RC v0
vi
E
- -

BJT amplifier. AC equivalent circuit using the small


signal hybrid-π.

Analysis steps:
• Draw the AC equivalent circuit.
• Replace the BJT by its small signal equivalent model.
• Calculate the input impedance, output impedance and voltage gain of the
circuit.

47
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Calculation of Voltage Gain

r
v
vi

. |
r gm gm v 0vi RB

RBr 0R
  
B C
  + +
v0

RC
 |   rπ vπ gmvπ r0 RC v0
r 0r 0

r
vi
vi

.
CR

E
r
RB
  
- -
 
C


Av

AC equivalent circuit using the small


  signal hybrid-π.
r
RCR

r
gm gm
0
r 0 RC

r
RB

  
 
C
r

 r0
f
o
r

.
r
RB

  

 

• Parallel combination: 5 k||200 k = 4.87 kΩ.

48
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Hybrid-π Model
+18 V
Draw the small-signal hybrid-π equivalence of the
following circuit (Si BJT with β = 100 and VA = 500 V).
33 kΩ 1.2 kΩ
Solutions:
IC

3
.
7
3 VTIC 7
m
A
c 0
a
l
c
u
l
a
t
e
d
p
r
e
v
i
o r 0 gm
u
s
l
y V ICICV
.
 ︵ ︶
Q

2 3
6
r

1
0

1
3
4
k
.
A Q Q T
.
7
3
       
Q

12 kΩ 1 kΩ

m
6
9
.

1
4
3
.
5

.
1
    
voltage divider bias
configuration.

RB C
B
+ +

vi R1||R2 rπ vπ gmvπ r0 RC v0
E
- -

AC equivalent circuit using the small signal hybrid-π.


49
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Analysis of CE Amplifier
+VCC

RC
R1 C2
C1
vs RC||
RL R1|| RL
vs R2
RE CE Rs
Rs R2

AC equivalent circuit of the


The amplifier circuit. amplifier.
RS B C
+ +

vi R1||R2 rπ vπ gmvπ r0 RC||RL v0


E
- -
AC equivalent circuit using the small signal hybrid-
π model.
50
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Analysis of CE Amplifier
RS B C
+ +

vs R1||R2 rπ vπ gmvπ r0 RC||RL v0


E
- -
AC equivalent circuit using the small signal hybrid-
π model.

v 0vs g g
R 1|
R 2|
r
|
| R 2r

| r RC
|

AV
v
vs

 

L
R 1vm

RsR
|

| |

  

R 1|
R 2|
r
|
| 20 | re

|r n
|

v0

|
|

r0 R
RC R R

RL f
| |
| |
   

R 1R
R

Rsr 0
|

| a RL
  
L
0

m
R 1|
R 2|
r


|
| R2

|r
|


gm
r0
RC

RL

vs
|
|
|
|

. 

|
|

ro

d .

,
 
R1

Rs
|

 
     

sR

|

 

RC
|
|

C
 
r
 

L

• Voltage gain without RL:
R 1|
R 2|
r

RCre
|
| R2

|r
|
Av

gm
r0
RC

gm
RC

RC
|
|

.

 
R1

Rs

r
|

 
  
0

  
51
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Analysis of CE Amplifier
ii RS ib B C ic iL
+ +

vi R1||R2 rπ vπ gmvπ r0 RC RL v0
E -
-

AC equivalent circuit using the small signal hybrid-


π model.

r0 |
RCR |

RL
|
|
|
|
Current gain:
ioii ii

 

io
gm
v r0
N
o
w
,
Ai

. R

  

LR
R
|

RBi .
r
|
|r
R 2r r |
r
|
|
|
|

 

Ai
gm
v

CRLR

L
 
ib

    

b

RCRL

ii
ib

RB

R1
R2
,

w
h
e
r
e

|
|

BR
RC

r
  
RB
r
|

  

      

B
 
Ap

Av
Ai
.

• Power gain:  
52
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Analysis of CE Amplifier
RS B C
+ +

vi R1||R2 rπ vπ gmvπ r0 RC v0
E
- -
Ri Ro
AC equivalent circuit using the small signal hybrid-
π model.

• Input resistance is the resistance seen by the AC source.


• Output resistance is the resistance seen by the load.
Rie

R1
R 2|
r
I
n
p
u
t
r
e
s
i
s
t
a
n
c
e

|
| r

| RC
|
.


Ro

RC
O
u
t
p
u
t
r
e
s
i
s
t
a
n
c

.

 
0

• Voltage gain mainly depends on RC and RL. We may end with attenuation
instead of amplification if RL is too small.
53
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal Analysis of CE Amplifier
12V
Calculate the input and output impedances
and the small signal voltage gain of the
68 kΩ 3.9 kΩ
amplifier (Si BJT with rπ = 2.1 kΩ, β = 75, ro 100 μF
= 1 MΩ). 100 μF
Solutions: 82 kΩ
• If unspecified, the small signal equivalent 47
56 kΩ 4.7 kΩ μF
parameters are to be calculated from the
DC biasing condition.
Rie

R1
R 2|
r
I
n
p
u
t
r
e
s
i
s
t
a
n
c
e

|
| r

| RC
|

1
.
9
7
k
.
   The amplifier circuit.
Ro
O
u
t
p
u
t
r
e
s
i
s
t
a
n
c

3
.
9
k
.

  
0

AV

RC |

1
3
9
.
3
.

r RC

Voltage gain without the load:  



AV

RL
|

1
3
3
.

 
r

 
L

Voltage gain with the load:


Recalculate the gain if the load is changed to 8 Ω (e.g. a sound box speaker).
AV

r
RL

0
.
2
9
a
t
t
e
n
u
a
t
i
o
n
.
Answer: Voltage gain with the load:     ︵ ︶
L

 54
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
CE Amplifier With an Emitter Resistor
+VCC

RC
R1 C2
C1
vs RC||
RL R1|| RL
vs R2
RE CE Rs RE
Rs R2

AC equivalent circuit of the


The amplifier circuit. amplifier.
RS B C ic
+ +
ib
R1||R2 rπ vπ gmvπ r0 RC||RL
vs v0
E

RE βib+ib
- -

Equivalent small signal hybrid-π model. 55


Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
CE Amplifier With an Emitter Resistor
RS B C ic
+ +
+ ib
R1||R2 rπ vπ gmvπ r0 RC RL
vs vi v0
E

RE βib+ib
- - -
Ri Rib Ro
Equivalent small signal hybrid-π model.
A
p
p
l
y
i
n
g
K
V
L
,
vi
ib
r vi t
ib r s R o

ib
RE 1

    
Ri E R i o

RE
.
i br

      
b m


i
t
e
r
e
i
s
t
a | RC
n Ri.
c
e
i
s
m
u
l
t
i
p
l
i
e
d
b
y
a
f
a
c
t
o
r

1
.
   
R
|
| r
|

,b
a
n
d

 
1|

2
R

RC
|

  Output resistance remains almost


unchanged but input resistance increases.
56
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
CE Amplifier With an Emitter Resistor
RS ib B C ic
+ +
+
R1||R2 rπ vπ gmvπ r0 RC RL
vs vi v0
E

RE βib+ib
- - -
Ri Rib Ro
Ri v 0v

Equivalent small signal hybrid-π model.


vi

vs
.
Ri 0
Rs



ibv
RC

Ri
Av

AV 1

RC

RL Ri

RC
F
o
r

,
p
u
t

|
|

i
n
s
t
e
a
d
o
f

 
Ri Rs
Rs

     
L


s

i
ibviRC

Ri
RC

RC 0
Ri

r a

RE R E

Ri r
Rs
1

     
      
Rs
f
o
r

n
d

,

  
RE
1

  
   
RCRE
.

 Voltage gain decreases.


57
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
CE Amplifier With an Emitter Resistor
12V
Calculate the input and output impedances
and the small signal voltage gain of the
68 kΩ 3.9 kΩ
amplifier (Si BJT with rπ = 2.1 kΩ, β = 75, ro 100 μF
= 1 MΩ). 100 μF
Solutions: 82 kΩ
Rin

r r

RER e
1 c

3
5
9
.
3
k
.
      
b

R1
R2
Ri

I O
p u
u
t
e
s
i
s
t
a
n
e

|
| r

| RC
|

2
8
.
3
k
.
56 kΩ 4.7 kΩ
  
i

b
Ro
t
p
u
t
r
e
s
i
s
t
a
n
c

|
|

3
.
9
k
.
  
0

The amplifier circuit.

RC1
AV

0
.
8
2
.

RE
Voltage gain without the load:  
  

58
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Small Signal h-Parameter Model
ic
ib ic
B C
+ + +
ib
hie (rπ) hfeib
vce +- 1/hoe vce
+ vbe hrevce (gmib)
vbe (r0)
ie - E
- - -

Small signal hybrid model of a npn transistor


BJT as a two-port device. in CE configuration and approximate
relationship with rπ parameters.

• Input voltage and output current are expressed in terms of input current
and output voltage.
vbic

hi
ib
hr
vc c

 
e

eib

ev
e
hf

ho

 
e

e
e

59
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
mkmandal@ece.iitkgp.ernet.in
60

.
3

0
-
1
~
Small Signal h-Parameter Model

o .
i
t

a
r 6
-

k 0
c 1
. a ~
b
d e

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur


Ω e

c

k e
f n
~ a
e t
e g c
c a u

n t
l d
a . o n
t n
i v o
s
i a r c
s g o t
u
e
r t o p
t n i
t t
u e
r a u
p r r o
n
i u e l
a
l c s
r n
a l
a e g
n n v i
s
g
i g s l
s i n l
l s a
r a
l
a l
l t m
m a e s
s m s
e s r
e
vc ce v ,
ev ,
r e ro
hr e , r 1
ho





0
ib 0 0 0

eib


e


c i b


i b
v
hi


e
c
v e
vbib icib vbvc i v
e e e
hf e c c

e





vbic hi
e e
hf e
hr ho
e
Amplifier
P A
o
w
e
r 1
g l
a
i
n
d
B popi v
,
︵ ︶
vi (mV)

d
B
0
o
g
  io (po)

p

1
0

 
RLRi d   ii Ri vo (V)
2 o 2 i vovi ioii

d
B
1
0
l
o
g

  (pi) Ro
v


1
0

 
 
B

Ri

RL
2
0
l
o
g

o
n
l
y
w
h
e
n

,
 
    Representation of an amplifier.
1
0

 
 
d
B

Ri

RL
2
0
l
o
g1

o
n
l
y
w
h
e
n

.
 
   
0

 
 

Half-power points:
po

pi

i
e
vo
vi
w
h
e
n

2 pi 2
.
.

2
,

   
2
Ap
1
0
l
o
g1

 
pi


0

 
 
1
0
l
o .
g 10
1

  
0
3
1

3
d
B
.

 
61
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Frequency Response of an Amplifier

• fc1 and fc2 corresponds to the half-power


30 3 dB
points and known as the lower and
higher cut-off frequencies, respectively. Ap (dB) 20 Half-power
• The output voltage vo = 0.707vi at the bandwidth
10
cut-off frequencies. fc1 fc2
0
• The difference (fc1 - fc2) is known as the 0 100 200 300 400
half-power bandwidth of the amplifier. Freq. (kHz)

• f0 = (fc1 - fc2)/2 is called the mid-band Frequency response of an amplifier.


frequency or center frequency of the
amplifier.
1000
βdc
100 0.707βdc
|β(jω)|
10

1 fβ 1000
0 500 fT
Freq. (kHz)
Frequency variation of β.
62
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
High Frequency Limitation of BJT
High frequency limitations: ic
ib Cbc
1. Junction capacitances: base-emitter B C
+ +
and collector-base junctions are
associated with junction capacitances. vbe rπ Cbe gmvπ r0 vce
2. Transit time: charge carriers take E
- -
finite transit time.

• Limitation is represented by a cutoff High frequency small signal equivalent


frequency fα where voltage gain falls circuit of a npn transistor in CE configuration.
to 0.707 of the mid-band value.
• Common-emitter cutoff frequency: β • Cbc: capacitance of the reverse-
falls to 0.707 of the mid-band value biased C-B junction.
at fαe (sometimes fβ). • Cbe: capacitance of the forward-
• Common-base cutoff frequency: α biased B-E junction.
falls to 0.707 of the mid-band value
at fαb (sometimes fα).
f

f
.e


b

 
63
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
High Frequency Limitation of BJT
Unity gain frequency: VCC

fT : in CE configuration, where short-circuited current gain RC


is unity.
fT

f
g
a
i
n
×
b
a
n
d
w
i
d
t
h

.b
Cbc
  

• For a given device, the gain-bandwidth product Cbe


is a constant term that cannot be changed.
• Cbe and Cbc are in pF range and their values
depend on the Q-point values.
IE T
6
.
1f

Representation of the
Cb

junction capacitances.

e

64
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
C
Miller Effect
o
n
s
i
d
e
r
i
n
g
a
m
p
l
i
f
i
e
r
d
r
a
w
s
n
o
c
u
r
r
e
n
t
,
Vi

Av
1
Vi
Vo  
Ii T

.

Z

Z n
 

V iI i

ZA
Zi C
h
e
i
n
p
u
t
i
m
p
e
d
a
c
e s

.
1
 

n

v
Z . v
F Z
o
r
c
a
p
a
c
i
t
o
r
,

. 
1 1
s
C


i
n

  
• If there is any capacitance (Cio) between the input and output terminals of an
inverting voltage amplifier (-Av), then the equivalent input capacitance (CM)
increases.
CM

Ci

Av
1

   
o

65
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Miller Effect
VCC VCC
RC RC

Cbc

Cbe CM Cbe

Miller effect.
Vo g

V
C
h
a
n
g
e
i
n
o
u
t
p
u
t
v
o
l
t
a
g
e

b
e
c
a
u
s
e
o
f
a
c
h
a
n
g
e
i
n
i
n
p
u
t
v
o
l
t
a
g
e

,i
 
Vo T

Av c
V
. t

  
i
o
t a
l
o
l
l
e
c
o
r
-
b
a
s
e
v
o
l
t
a
e
r
e
d
u
c
t
i
o
n
,


VC o

Vi r
Av Q
Vi C

Vi n

Av v
1 e

. l

       
B, h

In CE configuration, total input


N
w
c
h
a
g
e

c
h
a
g
i
n
o
t
a
g
e
.

  capacitance is
C
a
r
g
e
s
u
p
p
l
i
e
d
t
o
t
h
e
i
n
p
u
t
.

Ci

Cb

Av
Cb
1


n    
e

c
Q
Cb C

Av

Vi
1 V

     
c

.i

 
M

66
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Frequency Response of a CE Amplifier
+VCC

RC
R1 C2
C1
+ C1
+
vs Avvi RL
Rin vin Cs RL vo vs
RE CE
Rs Ro R2
- - Rs

RC highpass filter. RC lowpass filter. BJT in CE configuration.

• The coupling capacitors (C1 and C2) block low frequency signal: highpass

1 Ri
filtering.

fc

C1
2

1
• For the input side, the corresponding cutoff frequency:

n
• The input capacitance Cin + stray capacitance (a few hundred pF together)
bypasses high frequency components: lowpass filtering.
• Miller effect does not occur in common-base configuration: operates to a much
higher frequency. 67
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Noise in BJT Circuit
Thermal noise: because of random thermal motion of electrons in a metal.

• Resistors are the main source of noise


• rms value of this noise voltage is
h
f
B
R
4 p
en

k
T
B
R

h
f
k
T
4

V
o
l
t
,
f
o
r

<
<
 
h
f
k
t
e
x


︵ ︶ 1 

h k T B R
w
h
e
r
e

6
.
6
2
6
1
0
J
-
S
i
s
P
l
a
n
c
k
'
s
c
o
n
s
t
.
3
4

 

1
.
3
7
1
0
J
/
K
i
s
B
o
l
t
z
m
a
n
n
'
s
c
o
n
s
t
.
2
3

 
t
e
m
p
e
r
a
t
u
r
e
K
 ︵ ︶

f
b
a
n
d
w
i
d
t
h
,
-
c
e
n
t
e
r
f
r
e
q
u
e
n
c
y
H
z
 ︵ ︶
r
e
s
i
s
t
a
n
c
e
Ω
 ︵ ︶

• Some other noises: Shot noise (independent of f and T), Flicker noise (1/f),
Transit-time noise (at high frequencies) etc.
SiSo
NiNo
F
N
o
i
s
e
f
i
g
u
r
e

1
a
l
s
o
e
x
p
r
e
s
s
e
d
i
n
d
B
n

 ︵ ︶
ut

u
t

68
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Power Dissipation
• When designing a circuit, consider worst case (maximum) power dissipation.
• Add some safety margin.
• All the resistors and the BJT generates heat.
• dc power dissipated by a resistor: VI = V2/R
• Instantaneous ac power dissipated: v(t)*i(t)
• Average ac power dissipated over a cycle:

• Average dc power dissipated by a BJT: PDC = VCEQ xICQ

• Average ac power dissipated by a BJT: Pac = VCEQ xICQ/2

• The BJT power rating should be at least VCEQ xICQ

• Considering the safety margin, suggested power rating is PD = VCC xICmax (some
designer prefer 10xVCEQ xICQ)

Note that actual power dissipation in a BJT is


PDC =VBEQIBQ+VCEQICQ ≈VCEQICQ.
69
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Power Dissipation

Theorem (voltage divider bias): the power dissipated by the transistor is not larger
than ¼ of the power that would be dissipated by the two resistors RC and RE if they
were directly connected.

Calculate the minimum power rating of the device (β = 100).


Answer: 12 V
PD
V C5

I C2

IC
  
E
Q

E.
Q4

IB
m
W
. 12
9

2.2 kΩ
 
m
W
. 2
7

470 kΩ +
 VCE
+
VBE -
Considering safety margin, suggested value - IE
is VCC xICmax = 12x5.45 = 65.4 mW.
70
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Switching Circuit
• OFF state (Vout = VCE ≈ VCC): VCC
Vi is low/ negative  IB ≈ 0
RB RC
 the BJT is in cutoff,
+
 IC = ICBO. VCE
vs +
-
• ON state (Vout = VCE ≈ 0.2 V): VBE
-
Vi is high  IB = IBmax
 the BJT is in saturation,
Capacitor-coupled switching
 IC ≈ VCC /RC. circuit.
Design equations: VCC /RC IB = 40 μA
ViVC
O
f
f
s
t
a
t
e
:
c
h
e
c
k

c
u
t
-
i
n
v
o
l
t
a
g
e
.

 12
= 30
m
i
n
RC

IC
O
n
s
t
a
t
e
:

c
h
o
o
s
e

=
1
m
A
i
f
u
n
s
p
e
c
i
f
i
e
d
C a

  RC = 1 kΩ
IC


m
a
x

8 = 20
m
x

IC (mA)
VC

Vi B C

VCR

  = 10
N
o
w
IB
IC
,


C

4
m
a
x

C
R

   = 3 kΩ
m
a
x

=0
C
ViV

ViV

0
1 2
RB

RC

RB

RC
1

h
o
o
s
e

    0 3 6 VCC = 12
m
a
x

m
a
x

         VCE (V)
C
C

C
C

    71
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Switching Circuit
Design a capacitor-coupled stitching circuit using +6 V
base-bias configuration. IC should not exceed 1 mA.
The input is a positive square wave of amplitude 5 V 50 kΩ 6 kΩ
with a PRF = 10 kHz, VCC = 6 V, a Si-BJT with β = +
100 is to be used. VCE
vs +
VBE -
Solutions:
VC C

-
RC

k
6
. 5 6
C a
I

  
m 0
x

Direct-coupled switching circuit.


RB
1
0
6 0 5
1 . k

 
     VCC
 
R

k 0
1 RB
0

  
B

RC
T
a
k
e

RB
  +
C
VCE
+
VBE -
-

Capacitor-coupled switching circuit.


72
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Differential Amplifier
• Differential input: vd = (v1 – v2) Ro
vi1
• Common-mode input: vcm = (v1 + v2)/2 Ri +
(non-inverting) vdep vo
• v1 = vcm+ vd/2 and v2 = vcm - vd/2 -
vi2
For v1 = 10 μV, and v2 = -10 μV: (inverting)
vd = 20 μV and vcm = 0. Differential amplifier.

• Differential-mode output voltage: v0d = Ad(v1 – v2) VCC


• Common-mode output voltage: v0c = Acm(v1 + v2)/2
• vc1 = Acmvcm+ Advd
RC RC
• vc2 = Acmvcm - Advd VC1 VC2

• Common-mode rejection ratio: |Ad /Acm| + +


+ vB1 vB2 +
• CMRR is a measure of how well the differential - -
- -
amplifier rejects the common-mode.
ICQ
Considering identical BJTs, and VB1 = VB2:
-VCC
IC1 = IC2 ≈ IE1= IE2 = ICQ/2.
Differential amplifier using BJT.
vC1 = vC2 = VCC -RC IC1/2. 73
Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur mkmandal@ece.iitkgp.ernet.in
Thank you

?
mkmandal@ece.iitkgp.ernet.in
Ph. – +91-3222-283550 (o)
Department of E. & E.C.E.
I.I.T. Kharagpur, 721302.
74