DSD & DICA LAB (Master Copy)

1.
LOGIC GATES
AIM:
Develop VHDL models for 74LSXX Series Gates and simulate and synthesize the
same.
EQUIPMENT REQUIRED:
1. Xilinx ISE software

2. Personal Computer
BLOCK DIAGRAMS:
AND GATE (Quad 2-Input 74LS08)
Connection Diagram
FUNCTION TABLE
OR GATE(Quad 2-Input 74LS32)
Connection Diagram
DIET – DSD&DICA Lab Manual ………………………………………………………….. 0

FUNCTION TABLE
NOT GATE(Quad 2-Input 74LS04)
Connection Diagram

FUNCTION TABLE
NOR GATE(Quad 2-Input 74LS02)
Connection Diagram
FUNCTION TABLE

NAND GATE(Quad 2-Input 74LS00)
Connection Diagram
FUNCTION TABLE
EXOR GATE(Quad 2-Input 74LS86)
Connection Diagram

FUNCTION TABLE
PROCEDURE:
1. Mount the required IC on to the borad.

2. Connect Vcc +5V to 14th pin & ground to 7th pin in every IC.
3. Give the input values as in the truth table & observe output values.
4. Verify truth table for every gate.
5. Note the readings.
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity logic gates is
port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y_nota : out STD_LOGIC;
y_and : out STD_LOGIC;
y_or : out STD_LOGIC;
y_nand : out STD_LOGIC;
y_nor : out STD_LOGIC;
y_xor : out STD_LOGIC;
y_xnor : out STD_LOGIC);
end logic gates;
architecture Behavioral of logic gates is
begin
y_nota <= not a;
y_and <= a and b;
y_or <= a or b;
y_nand <= a nand b;
y_nor <= a nor b;

y_xor <= a xor b;
y_xnor <= a xnor b;
end Behavioral;
TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_vhd IS
END tb_vhd;
ARCHITECTURE behavior OF tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT logicgates
PORT( a : IN std_logic;
b : IN std_logic;
y_nota : OUT std_logic;
y_and : OUT std_logic;
y_or : OUT std_logic;
y_nand : OUT std_logic;
y_nor : OUT std_logic;
y_xor : OUT std_logic;
y_xnor : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';

SIGNAL b : std_logic := '0';
--Outputs
SIGNAL y_nota : std_logic;

SIGNAL y_and : std_logic;
SIGNAL y_or : std_logic;
SIGNAL y_nand : std_logic;
SIGNAL y_nor : std_logic;
SIGNAL y_xor : std_logic;
SIGNAL y_xnor : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: logicgates PORT MAP(

a => a,
b => b,

y_nota => y_nota,
y_and => y_and,
y_or => y_or,
y_nand => y_nand,
y_nor => y_nor,
y_xor => y_xor,
y_xnor => y_xnor);
a<='0','1' after 20 ns;

b<='0','1' after 10 ns,'0' after 20 ns,'1' after 30ns;
END;
SIMULATION OUTPUT:
RESULT: The truth table of OR,AND,NOR,NAND & EX-OR are verified.

2. 3 To 8 DECODER USING IC-74LS138.
AIM:
Develop VHDL model for 74LS138 3 x 8 decoder and simulate and synthesize the
same.
EQUIPMENT REQUIRED:

BLOCK DIAGRAM:
Connection Diagram:
FUNCTION TABLE:

PROCEDURE:
1. Connect circuit as shown in figure.

2. Apply Vcc to pin 16 of IC 74 LS 138.
3. Pins 4,5,6 are enable inputs.
4. Connects inputs to pins 1,2,3.
__ __
5. When E1 is high, E2, E3 are low / high then all outputs are high
irrespective.
__ __
6. Similarly when E2 is high ,all outputs are high irrespective of E1 & E2 &
inputs.
__ __
7. When E3 is low, all outputs are high irrespective of E 1, E2 are inputs.
__ __
8. With E1, E2 low and E3 high when all inputs are low, then
__
outputs Qo will be low and other outputs will be high.
9. Similarly by changing two inputs Ao, A1, A2 we get one ouput low
& others high every time.
__
10. When inputs are high , o/p O , will become low and others become
high.
VHDL CODE:
library ieee;
use ieee.std_logic_1164.all;
entity decoder3x8 is
port(G1,G2,C,B,A:in std_logic;
Y:out std_logic_vector(0 to 7));
end decoder3x8;
architecture decoder3x8 of decoder3x8 is
signal S:std_logic_vector(2 downto 0);
begin
S<=C&B&A;
process(G1,G2,S)
begin
if G2='1' then Y<="11111111";
elsif G1='0' then Y<="11111111";
elsif G1='1' and G2='0' and S="000" then Y<="01111111";
else Y<="UUUUUUUU";
end if;
end process;
end architecture decoder3x8;
TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_vhd IS
END tb_vhd;
COMPONENT decoder3x8
PORT(
G1 : IN std_logic;
G2 : IN std_logic;
C : IN std_logic;
B : IN std_logic;
A : IN std_logic;
Y : OUT std_logic_vector(0 to 7)
);
END COMPONENT;
--Inputs
SIGNAL G1 : std_logic := '0';

SIGNAL G2 : std_logic := '0';
SIGNAL C : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL A : std_logic := '0';
--Outputs
SIGNAL Y : std_logic_vector(0 to 7);
BEGIN

uut: decoder3x8 PORT MAP(
G1 => G1,
G2 => G2,
C => C,
B => B,
A => A,
Y => Y
);
G1<='0','1'after 20 ns;
G2<='1','0' after 20 ns;
C<='0','1' after 60ns;
B<='0','1' after 40 ns,'0' after 60 ns,'1' after 80 ns;
A<='0','1' after 30 ns,'0' after 40 ns,'1' after 50 ns,
'0' after 60 ns,'1' after 70 ns,'0' after 80 ns,
'1' after 90 ns;
END;
SIMULATION OUTPUT:
RESULT: operation of 3-8 decoder using IC 74 LS 138 is verified.

3. 8x1 MULTIPLEXER USING IC 74 LS 150
AIM:
I. Develop the model for 74LS150- 8X1 Multiplexer and simulate and synthesize the
same.
EQUIPMENT REQUIRED:

PROCEDURE:
1. Connections are made as per the circuit diagram.

2. Connect the i/p D0 to D7.
3. Give the data inputs and verify the outputs according to truth table.
BLOCK DIAGRAM:
Connection Diagram
FUNCTION TABLE:

VHDL CODE:
library ieee;
entity mux8x1 is
port(C,B,A,G_L:in std_logic;
D:in std_logic_vector(7 downto 0);
Y,W:out std_logic);
end mux8x1;
architecture mux8x1 of mux8x1 is
signal s:std_logic_vector(2 downto 0);
begin
s<=C&B&A;
process(S,G_L)
begin

if G_L='1' then Y<='0';W<='1';
elsif S<="000" and G_L='0' then Y<=D(0);W<=not D(0);
else Y<='U';W<='U';
end if;
end process;
end architecture mux8x1;
TEST BENCH:
LIBRARY ieee;
ENTITY tb_vhd IS
END tb_vhd;
COMPONENT mux8x1
PORT(
C : IN std_logic;
B : IN std_logic;
A : IN std_logic;
G_L : IN std_logic;
D : IN std_logic_vector(7 downto 0);
Y : OUT std_logic;
W : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL C : std_logic := '0';

SIGNAL B : std_logic := '0';
SIGNAL A : std_logic := '0';
SIGNAL G_L : std_logic := '0';
SIGNAL D : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs

SIGNAL Y : std_logic;
SIGNAL W : std_logic;
BEGIN
uut: mux8x1 PORT MAP(

C => C,
B => B,
A => A,
G_L => G_L,
D => D,
Y => Y,
W => W
);
C<='0','1' after 50ns;

B<='0','1' after 30ns,'0' after 50ns,'1' after 70ns;
A<='0','1' after 20ns,'0' after 30ns,'1' after 40ns,'0' after 50ns,'1' after
60ns,'0' after 70ns,'1' after 80ns;
G_L<='1','0' after 10ns;
D<="11101101";
END;
SIMULATION OUTPUT:
VHDL CODE for 1 to 4 Demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux1t4 is
Port ( s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0);
en_l : in STD_LOGIC;

x : in STD_LOGIC);
end demux1t4;
architecture Behavioral of demux1t4 is

signal z :STD_LOGIC_VECTOR (3 downto 0):= "0000";
begin
process(s,x,en_l,z)
begin
if en_l ='0' then
if(s = "00" ) then
z(0) <= x;
z(1)<=’0’;
z(2)<=’0’;
z(3)<=’0’;
elsif(s = "01" ) then
z(0) <= ‘0’;
z(1)<=x;
z(2)<=’0’;
z(3)<=’0’;
elsif(s = "10" ) then
z(0) <= ‘0’;
z(1)<=’0’;
z(2)<=x;
z(3)<=’0’;
elsif(s=”11”) then
z(0) <= ‘0’;
z(1)<=’0’;
z(2)<=’0’;
z(3)<=x;
else
z<=”0000”;
end if;
end if;
y <= z;
end process;
end Behavioral;
TEST BENCH
LIBRARY ieee;
ENTITY tbdemux1t8_vhd IS
END tbdemux1t8_vhd;
ARCHITECTURE behavior OF tbdemux1t8_vhd IS
COMPONENT demux1t4
PORT(

s : IN std_logic_vector(1 downto 0);
en_l : IN std_logic;
x : IN std_logic;
y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL en_l : std_logic := '0';
SIGNAL x : std_logic := '0';
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic_vector(3 downto 0);
BEGIN

uut: demux1t4 PORT MAP(
s => s,
y => y,
en_l => en_l,
x => x
);
en_l <= '1','0' after 10 ns,'1' after 50 ns;

x <= '1';
a <= "00","01" after 20 ns,"10" after 30 ns,"11" after 40 ns;
END;
SIMULATION OUTPUT:
RESULT: The operation of 8 X 1 multiplexer using IC 74 LS 150 and 1X4

demultiplexer are verified.

4. 4 -BIT COMPARATOR
AIM:
Develop the VHDL model for 74x85 4-bit comparator and simulate and synthesize the
same.
EQUIPMENT REQUIRED:

BLOCK DIAGRAM:
Connection Diagram
PROCEDURE:
1. Connections are made as per circuit diagram.

2. Give the inputs A [ A3 ,A2 ,A1 ,A0 ] , B [ B3 ,B2 , B1 , B0 ] according to the
function table and gives corresponding inputs IA>B , IA<B, IA=B and verify
the output.
3. Tabulate the inputs and outputs according to the function table.

VHDL CODE:
library ieee;
entity comparator4bit is
port(A,B:in std_logic_vector(3 downto 0);

AeqB,AlsB,AgrB:out std_logic);
end comparator4bit;
architecture comparator4bit of comparator4bit is
begin
process(A,B)
begin
if A(3)>B(3) then AgrB<='1';AeqB<='0';AlsB<='0';
elsif A(3)<B(3) then AgrB<='0';AeqB<='0';AlsB<='1';
elsif A(3)=B(3) and A(2)>B(2) then AgrB<='1';AeqB<='0';AlsB<='0';
elsif A(3)=B(3) and A(2)<B(2) then AgrB<='0';AeqB<='0';AlsB<='1';
elsif A(3)=B(3) and A(2)=B(2) and A(1)>B(1) then
AgrB<='1';AeqB<='0';AlsB<='0';
elsif A(3)=B(3) and A(2)=B(2) and A(1)<B(1) then
elsif A(3)=B(3) and A(2)=B(2) and A(1)=B(1) and A(0)>B(0) then
elsif A(3)=B(3) and A(2)=B(2) and A(1)=B(1) and A(0)<B(0) then
else AgrB<='0';AeqB<='1';AlsB<='0';

end if;
end process;
end comparator4bit;
TEST BENCH:
LIBRARY ieee;
ENTITY tb_vhd IS
END tb_vhd;
COMPONENT comparator4bit
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
AeqB : OUT std_logic;
AlsB : OUT std_logic;
AgrB : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL A : std_logic_vector(3 downto 0) := (others=>'0');

SIGNAL B : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL AeqB : std_logic;

SIGNAL AlsB : std_logic;
SIGNAL AgrB : std_logic;
BEGIN
uut: comparator4bit PORT MAP(

A => A,
B => B,
AeqB => AeqB,
AlsB => AlsB,
AgrB => AgrB
);

A<="1100","1010" after 20ns,"0101" after 40ns;
B<="1001","1101" after 20ns,"0101" after 40ns;
END;
SIMULATION OUTPUT:
RESULT: The operation of 4 – bit comparator using IC 74 LS 85 is verified.

5. D FLIP-FLOP USING IC-7474
AIM:
Develop VHDL model for 74LS74 D-Flip-Flop and simulate and synthesize the
same.
EQUIPMENT REQUIRED:

BLOCK DIAGRAMS:
PROCEDURE:

1. Connections are made as per circuit.
2. Connect the preset terminal to logic -1 & then clear the circuit by
connecting the clear terminal to logic – 0 & observe Q, Q .
4 .Now apply +ve edge tiggered CLK & change values of ‘D’ to 0 &1
And verify the change values of Q & Q.
5. All values are noted in truth table.
VHDL CODE:
library ieee;
entity dflipflop is
port(PR,CLR,CLK,D:in std_logic;
Q,Q_L:out std_logic);
end dflipflop;
architecture dflipflop of dflipflop is
signal tq,tqb:std_logic;
begin
process(PR,CLR,CLK)
begin
if PR='0' and CLR='1' then tq<='1';tqb<='0';

elsif PR='1' and CLR='0' then tq<='0';tqb<='1';
elsif PR='0' and CLR='0' then tq<='1';tqb<='1';
elsif PR='1' and CLR='1' and CLK'event and CLK='1' then
tq<=D;tqb<=not D;
elsif PR='1' and CLR='1' and CLK='0' then tq<=tq;tqb<=tqb;
end if;
end process;
Q<=tq;
Q_L<=tqb;
end architecture dflipflop;
TEST BENCH:
LIBRARY ieee;

ENTITY tb_vhd IS
END tb_vhd;
COMPONENT dflipflop
PORT(
PR : IN std_logic;
CLR : IN std_logic;
CLK : IN std_logic;
D : IN std_logic;
Q : OUT std_logic;
Q_L : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL PR : std_logic := '0';

SIGNAL CLR : std_logic := '0';
SIGNAL CLK : std_logic := '0';
SIGNAL D : std_logic := '0';
--Outputs
SIGNAL Q : std_logic;
SIGNAL Q_L : std_logic;
BEGIN
uut: dflipflop PORT MAP(

PR => PR,
CLR => CLR,
CLK => CLK,
D => D,
Q => Q,
Q_L => Q_L
);
PR<='0','1' after 10ns;

CLR<='1','0' after 10ns,'1' after 20ns;
D<='0','1' after 20ns,'0' after 30ns;
process
begin
CLK<='1';
wait for 5ns;

CLK<='0';
wait for 5ns;
end process;
END;
SIMULATION OUTPUT:
RESULT: The truth table of D -Flip – Flop using IC 7474 was verified.

6. DECADE COUNTER USING IC-7490
AIM:
Develop VHDL model for 74LS90 Decade Counter and simulate and synthesize the
same.
EQUIPMENT REQUIRED:

BLOCK DIAGRAM:
FUNCTION TABLE(74LS90)
BCD Count Sequence

Note: Output QA is connected to input B for BCD Count

PROCEDURE:
1. Connect the circuit as shown in the figure.

2. Clock pluse given to pin 14 of IC 7490.
3. Vcc supply given to pin 5 of 7490.
4. Pins 12 and 1 are shorted.
5. Pins 2 and 3 are master reset inputs and pins 6 and 7 are master inputs.
6. Pins 13 and 4 has no connection.
7. Pins 2,3,6 and 7 are inputs and always ‘0’.
8. Pins 12,9,8,11 are outputs.
9. Feed MR with ‘1’ and master set terminals with ‘0’ and
apply clock then output varies between 0 &9.
VHDLCODE:
library ieee;
use ieee.std_logic_unsigned.all;
entity decadecounter is
port(CLK,R,S:in std_logic;
Q:out std_logic_vector(3 downto 0));
end decadecounter;
architecture decadecounter of decadecounter is
signal count:std_logic_vector(3 downto 0);
begin
process(CLK,R,S)
begin
if R='1' then count<="0000";

elsif CLK'event and CLK='1' and R='0' then
if count="1001" and S='1' then count<="1001";

elsif count="1001" and S='0' then count<="0000";
else count<=count+"0001";
end if;
end if;
end process;
Q<=count;
end decadecounter;
TEST BENCH:
LIBRARY ieee;
ENTITY tb_vhd IS
END tb_vhd;
COMPONENT decadecounter
PORT(
CLK : IN std_logic;
R : IN std_logic;
S : IN std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs

SIGNAL R : std_logic := '0';
SIGNAL S : std_logic := '0';
--Outputs
SIGNAL Q : std_logic_vector(3 downto 0);
BEGIN
uut: decadecounter PORT MAP(

CLK => CLK,

R => R,
S => S,
Q => Q
);
R<='1','0' after 10ns;

S<='0','1' after 150ns;
process
begin
CLK<='1';
wait for 5ns;
CLK<='0';
wait for 5ns;
end process;
END;
SIMULATION OUTPUT:
RESULT: The Working of Decade Counter using IC 7490 is studied.

7. 4-BIT COUNTER USING IC-7493
AIM:
Develop VHDL model for 74LS93 Binary Counter and simulate and synthesize the
same.
EQUIPMENT REQUIRED:

BLOCK DIAGRAM:
FUNCTION TABLES(74LS93
Note: Output QA is connected to input B

PROCEDURE:
1. Connect the circuit as shown in the figure.

2. The clock pulse is given to pin 14 of IC 7493.
3. The Vcc supply is given to pin 5 of IC 7493.
4. pin 12 and pin 1 are to be shorted.
5. pin 2, pin 3, are master reset inputs.
6. pins 12,9,8,11 are outputs.
7. Feed the MR terminals with ‘0’ and apply clock and then the
output varies let the value 0 to 15.
VHDL CODE:
library ieee;
use ieee.std_logic_unsigned.all;
entity binarycounter is
port(CLK,R:in std_logic;
Q:out std_logic_vector(3 downto 0));
end binarycounter;
architecture binarycounter of binarycounter is
signal count:std_logic_vector(3 downto 0);
begin
process(R,CLK)
begin
if R='1' then count<="0000";

elsif CLK'event and CLK='1' and R='0' then
if count="1111" then count<="0000";
else count<=count+"0001";
end if;
end if;
end process;
Q<=count;
end binarycounter;

TEST BENCH:
LIBRARY ieee;
ENTITY tb_vhd IS
END tb_vhd;

COMPONENT binarycounter
PORT(
CLK : IN std_logic;
R : IN std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs

SIGNAL R : std_logic := '0';
--Outputs
SIGNAL Q : std_logic_vector(3 downto 0);
BEGIN
uut: binarycounter PORT MAP(

CLK => CLK,
R => R,
Q => Q
);
R<='1','0' after 10ns;

process
begin
CLK<='1';
wait for 5ns;
CLK<='0';
wait for 5ns;
end process;
END;

SIMULATION OUTPUT:
RESULT: Thus the operation of 4 – bit counter using IC 7493 was studied.

8. SHIFT REGISTER USING IC-74LS95
AIM:
I. To verify the following function of Shift Register using IC 7495.
1. Clearing the Register.

2. Serial I/P / Parallel O/P.
3. Parallel I/P / Parallel O/P.
4. Parallel I/P / Serial O/P.
II. Develop VHDL model for 74LS95 register and simulate and synthesize the same.
EQUIPMENT REQUIRED:

BLOCK DIAGRAM

PROCEDURE:
1. Mount IC 7495A on logic trainer and make required connections.

Pins 2,3,4,5 are connected to logic switches SW1, SW2, SW3, SW4
for applying high and logic at these inputs.
2. Serial input is given to pin 1 and mode CTRL to pin6.
3. pins 8,9 shorted, given to clock.
4. Connect Vcc to 5v to pin and 7th pin grounded.
1.Clearing function:
1. set mode CTRL switch to low.

2. set serial input switch to low.
3. set parallel inputs A,B,C,D to logic ‘0’.
4. To clear the register apply clock pulses till the output is 0000.
2.serial input / parallel output:
1.After register has cleared any 4 bit serial no. can be loaded
into the register.
2. set mode CTRL switch to low.
3.set serial input switch to high.
4.Apply clock pulse which shift serial input 1 into reg Qn will be 1.
5.we can load any 4 bit number into reg.
3.Parallel I/P / Parallel O/P:
1.set mode CTRL switch to high.

2.Apply input 1011 to A,B,C,D.
3.It we apply clock pulse the word is loaded in to the reg.

4.Parallel I/P / Serial O/P:
1.set mode CTRL switch to low.

2.set serial input pin 1 to low.
3. As you apply CLK pulses the word will be shifted out serially from
Qo after 4 CLK pulses the register will be cleared.
VHDL CODE:
library ieee;
entity shif_95r is
port( CLK,MODE, SER : in std_logic;
PALL : in std_logic_vector(3 downto 0);
Q_A,Q_B,Q_C,Q_D : inout std_logic
);
end entity shif_95r;
architecture bhe of shif_95r is
begin
process(CLK,MODE,SER,PALL)
variable O : std_logic_vector(3 downto 0);

variable P : std_logic_vector(3 downto 0);
begin
p := Q_A & Q_B & Q_C & Q_D;
if( CLK = '1' and clk'event) then

if( MODE ='1') then O := PALL;
elsif( MODE ='0' ) then O := SER & Q_A & Q_B & Q_C;
else O:="UUUU";
end if;
end if;
Q_A <= O(3);

Q_B <= O(2);
Q_C <= O(1);
Q_D <= O(0);
end process;
end architecture bhe;

TEST BENCH:
LIBRARY ieee;
ENTITY tb_vhd IS
END tb_vhd;
COMPONENT shif_95r
PORT(
CLK : IN std_logic;
MODE : IN std_logic;
SER : IN std_logic;
PALL : IN std_logic_vector(3 downto 0);
Q_A : INOUT std_logic;
Q_B : INOUT std_logic;
Q_C : INOUT std_logic;
Q_D : INOUT std_logic
);
END COMPONENT;
--Inputs

SIGNAL MODE : std_logic := '0';
SIGNAL SER : std_logic := '0';
SIGNAL PALL : std_logic_vector(3 downto 0) := (others=>'0');
--BiDirs
SIGNAL Q_A : std_logic;

SIGNAL Q_B : std_logic;
SIGNAL Q_C : std_logic;
SIGNAL Q_D : std_logic;
BEGIN
uut: shif_95r PORT MAP(

CLK => CLK,
MODE => MODE,
SER => SER,
PALL => PALL,
Q_A => Q_A,
Q_B => Q_B,

Q_C => Q_C,
Q_D => Q_D
);
PALL <= "0000";
process
begin
CLK <='1';
wait for 10 ns;
CLK <='0';
wait for 10 ns;
end process;
MODE <= '1','0' after 20 ns;
SER <= '1','0' after 100 ns;
END;
SIMULATION OUTPUT:
RESULT: The functions of shift register using IC 7495 is verified

9. UNIVERSAL SHIFT REGISTER USING IC 74 LS 194
AIM:
Develop VHDL model for 74LS94 Universal Shift register and simulate and
synthesize the same.
EQUIPMENT REQUIRED:

BLOCK DIAGRAM:
Note: SR-> Shift Right

SL-> Shift Left

PROCEDURE:
1.Connections are made as per circuit diagram.

2.Connect Vcc +5v to 10th pin & ground the 8th pin.
3.Connect mode control I/p’s S1, S0 to pins 9,10.
4. Connect pin 11 to +ve edge pulse.
5. Connect register shift pin to 2 & use pin 7 for left shift operation.
6.Apply mode control I/P’s and verify the result according to truth table.
VHDL MODEL:
library ieee;
entity univ_sreg is
port( CLR,CLK,S_L,S_R : in std_logic;
A,B,C,D : in std_logic ;
S : in std_logic_vector(1 downto 0);
);
end entity univ_sreg;
architecture behv of univ_sreg is

begin
process(CLR,CLK,S_L,S_R,A,B,C,D,S)
variable P : std_logic_vector(0 to 3);
variable O : std_logic_vector(0 to 3);
begin
P := Q_A & Q_B & Q_C & Q_D;
if ( CLR = '0') then

O := "0000";
elsif ( CLR = '1') then
if( CLK ='0' and clk’event) then
O := P;
elsif( CLK ='1' and clk'event) then
if( S ="11") then O :=A & B& C & D;
elsif ( S="01" and S_R ='1') then O := '1' & Q_A & Q_B & Q_C;
elsif ( S="01" and S_R ='0') then O := '0' & Q_A & Q_B & Q_C;
elsif ( S="10" and S_L ='1') then O := Q_B & Q_C & Q_D & '1';
elsif ( S="10" and S_L ='0') then O := Q_B & Q_C & Q_D & '0';
elsif( S="00") then O :=P;
end if;
end if;
end if;
Q_A <= O(0);
Q_B <= O(1);
Q_C <= O(2);
Q_D <= O(3);
end process;

end behv;
TEST BENCH:
library ieee;
entity test is
end entity test;
architecture test_sftreg of test is
component univ_sreg
port( CLR,CLK,S_L,S_R : in std_logic;
A,B,C,D : in std_logic ;
S : in std_logic_vector(1 downto 0);
);
end component;
signal CLR,CLK,S_L,S_R,A,B,C,D,Q_A,Q_B,Q_C,Q_D : std_logic;
signal S : std_logic_vector(1 downto 0);
begin
U0:univ_sreg port map(CLR,CLK,S_L,S_R,A,B,C,D,S,Q_A,Q_B,Q_C,Q_D);
CLR <= '0','1' after 20 ns;
A <= '0';
B <= '0';
C <= '0';
D <= '0';
process
begin
clk<='1';
wait for 5 ns;
clk<= '0';
wait for 5 ns;
end process;
s<= "11","01" after 50 ns, "10" after 90 ns,"00" after 130 ns;
s_l<= '1','0' after 110 ns;
s_r<= '1','0' after 70 ns;
end architecture test_sftreg;
SIMULATION OUTPUT:

RESULT: The functions of IC 74 LS 194 universal shift register is verified
10. RAM(16X4) – 74189(Read and Write Operations).

AIM:
Develop the model for 74LS189- 16 x 4 Ram and simulate and synthesize the same.
EQUIPMENT REQUIRED:

BLOCK DIGRAM:
FUNCTION TABLE:
PROCEDURE:

1.Connect the inputs to a binary counter 7493IC
2.Connect the four data inputs to toggle swithes
3. Connect the data outputs to four 7404 inverters
4. Provide four more for the outputs of the inverters.
5. Connect input CE to ground and RW to a pulser
6. Store a few words into the memory and then read them to verify
that the write and read operations are functioning properly
7. To store the word in memory , flip the RW switch to write position
And then return it to the read position.
VHDL CODE:
library ieee;
entity ram is
port(CLK,RST,CE,WR,RD : in std_logic;
ADD : in integer range 0 to 15;
DATA_IN : in std_logic_vector(3 downto 0);
DATA_OUT : out std_logic_vector(3 downto 0)
);
end ram;
architecture ram of ram is

type vector_array is array(0 to 15) of std_logic_vector(3 downto 0);
signal mem : vector_array;
begin
process
begin
wait until clk'event and CLK ='1';
if(CE='1') then
if(RST='1') then DATA_OUT <="0000";
else
if(RD='1') then DATA_OUT <= mem(ADD);
elsif(WR='1') then mem(ADD) <= DATA_IN;
DATA_OUT <= "UUUU";
end if;
end if;
end if;
end process;
end ram;
TEST BENCH:
library ieee;
entity test_ram is
end entity test_ram;
architecture test of test_ram is

component ram
port(CLK,RST,CE,WR,RD : in std_logic;
ADD : in integer range 0 to 15;
DATA_IN : in std_logic_vector(3 downto 0);
DATA_OUT : out std_logic_vector(3 downto 0)
);
end component;
signal CLK,RST,CE,WR,RD : std_logic;
signal ADD : integer range 0 to 15;
signal DATA_IN,DATA_OUT : std_logic_vector(3 downto 0);
begin
U0: ram port map(CLK,RST,CE,WR,RD,ADD,DATA_IN,DATA_OUT);
process
begin
CLK <= '1';
wait for 10 ns;
CLK <= '0';
wait for 10 ns;
end process;
CE <= '1';
RST <= '1',
'0' after 20 ns;
DATA_IN <= "0000",
"1000" after 40 ns,
"1001" after 60 ns,
"1010" after 80 ns,
"1111" after 180 ns,
"0111" after 200 ns,
"0110" after 220 ns,
"0101" after 240 ns;
ADD <= 0,
1 after 40 ns,
2 after 60 ns,
3 after 80 ns,
0 after 100 ns,
1 after 120 ns,
2 after 140 ns,
3 after 160 ns,
0 after 180 ns,
1 after 200 ns,
2 after 220 ns,
3 after 240 ns;
WR <= '1',
'0' after 100 ns,
'1' after 180 ns;
RD <= '0',
'1' after 100 ns,
'0' after 180 ns;
end architecture test;
SIMULATION OUTPUT:

RESULT: RAM 16X4 has been verified.
11. ALU

AIM:
Develop VHDL model for 8-bit ALU and simulate and synthesize the same.
EQUIPMENT REQUIRED:

VHDL CODE:
entity Alu is
port( Clk : in Std_Logic;
MODE,EN: in Std_Logic;
A,B : in Std_Logic_Vector(7 downto 0);
OPCODE : in Std_Logic_Vector(3 downto 0);
Y : out Std_Logic_Vector(7 downto 0));
end Alu;
architecture Alu_a of Alu is
signal C_s : Unsigned(7 downto 0);

begin
process (A, B,OPCODE,mode)
variable A_v : Unsigned(7 downto 0);
variable B_v : Unsigned(7 downto 0);
begin
A_v := Unsigned(A);
B_v := Unsigned(B);
if(EN='0')then
C_s<=(others=>'Z');
if(mode='0')then
case OPCODE is
when "0000" => C_s <= A_v + B_v;
when "0001" => C_s <= A_v - B_v;
when "0010" => C_s <= A_v(3 downto 0) * B_v(3 downto 0);
when others => C_s <= (others => '0');
end case;
else
case opcode is
when "0011" => C_s <= not A_v;
when "0100" => C_s <= not B_v;
when "0101" => C_s <= A_v and B_v;
when "0110" => C_s <= A_v nand B_v;
when "0111" => C_s <= A_v or B_v;
when "1000" => C_s <= A_v nor B_v;
when "1001" => C_s <= A_v xor B_v;
when "1010" => C_s <= A_v xnor B_v;
when others => C_s <= (others => '0');
end case;
end if;
end if;
end process;
process
begin
wait until Clk'event and Clk = '1';
y <= Std_Logic_Vector(C_s);
end process ;
end Alu_a;
Additional Experiments

1. J-K flip-flop
AIM:
Develop the model for 74LS76 J-K flipflop and simulate and synthesize the same.
EQUIPMENT REQUIRED:

BLOCK DIGRAM:

PROCEDURE:
1. Connections are made as per circuit.

4 .Now apply +ve edge tiggered CLK & change values of ‘J’ and ‘K’ to 0
&1 combinations. And verify the change values of Q & Q.
5. All values are noted in truth table.
VHDL CODE:
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity JKFF is
PORT( J,K,CLK,PRST,CLR: in std_logic;
Q, QB: out std_logic);
end JKFF;
Architecture behavioral of JKFF is

begin
PROCESS(CLK,CLR,PRST)
variable x: std_logic;

begin
if(CLR='0') then
x:='0';
elsif(PRST='0')then
x:='1';
elsif(CLK='1' and CLK'EVENT) then

if(J='0' and K='0')then
x:=x;
elsif(J='1' and K='1')then
x:= not x;
elsif(J='0' and K='1')then

x:='0';
else
x:='1';
end if;
end if;
Q<=x;
QB<=not x;
end PROCESS;
end behavioral;
TEST BENCH:
LIBRARY ieee;
ENTITY jfkejfijeijk_vhd IS
END jfkejfijeijk_vhd;
ARCHITECTURE behavior OF jfkejfijeijk_vhd IS

COMPONENT JKFF
PORT(
J : IN std_logic;
K : IN std_logic;
CLK : IN std_logic;
PRST : IN std_logic;
CLR : IN std_logic;
Q : OUT std_logic;
QB : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL J : std_logic := '0';
SIGNAL K : std_logic := '0';
SIGNAL PRST : std_logic := '0';
SIGNAL CLR : std_logic := '0';
--Outputs
SIGNAL Q : std_logic;
SIGNAL QB : std_logic;
BEGIN

uut: JKFF PORT MAP(
J => J,
K => K,
CLK => CLK,
PRST => PRST,
CLR => CLR,
Q => Q,
QB => QB
);
process
begin
clk<='0';
wait for 5 ns;
clk<='1';
wait for 5 ns;
end process;
j<='0','1' after 60 ns;

k<='0','1' after 40 ns,'0' after 60 ns,'1' after 80 ns;
prst<='0','1' after 15 ns;
clr<='1','0' after 15 ns,'1' after 30 ns;
END;
SIMULATION OUTPUT:

2. ENCODER
AIM:
I. Develop the model for 4x2 encoder and simulate and synthesize the same.
EQUIPMENT REQUIRED:

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity encoder is
port(
d0,d1, d2 , d3 : in STD_LOGIC;
a, b : out STD_LOGIC
);
end encoder;
architecture encoder of encoder is

begin
a<= d2 or d3;
b<= d1 or d3;
end encoder;
TESTBENCH
library ieee;
entity encoder_tb is
end encoder_tb;
architecture TB_ARCHITECTURE of encoder_tb is
component encoder
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
a : out std_logic;
b : out std_logic );

end component;
signal d0 : std_logic;
signal a : std_logic;
signal b : std_logic;
begin
UUT : encoder
port map (
d0 => d0,
d1 => d1,
d2 => d2,
d3 => d3,
a => a,
b => b
);
d0<='1'; d1<='0';d2<='0';d3<='0'; wait for 5 ns;

d0<='0'; d1<='1';d2<='0';d3<='0'; wait for 5 ns;
d0<='0'; d1<='0';d2<='1';d3<='0'; wait for 5 ns;
d0<='0'; d1<='0';d2<='0';d3<='1'; wait for 5 ns;
end TB_ARCHITECTURE;
SIMULATION OUTPUT:

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1.

1. Xilinx ISE software

AND GATE (Quad 2-Input 74LS08)

OR GATE(Quad 2-Input 74LS32)

DIET – DSD&DICA Lab Manual ………………………………………………………….. 0

NOT GATE(Quad 2-Input 74LS04)

DIET – DSD&DICA Lab Manual ………………………………………………………….. 1

NOR GATE(Quad 2-Input 74LS02)

DIET – DSD&DICA Lab Manual ………………………………………………………….. 2

EXOR GATE(Quad 2-Input 74LS86)

DIET – DSD&DICA Lab Manual ………………………………………………………….. 3

1. Mount the required IC on to the borad.

entity logic gates is

end logic gates;

architecture Behavioral of logic gates is

DIET – DSD&DICA Lab Manual ………………………………………………………….. 4

ARCHITECTURE behavior OF tb_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

SIGNAL a : std_logic := '0';

SIGNAL y_nota : std_logic;

-- Instantiate the Unit Under Test (UUT)

uut: logicgates PORT MAP(

DIET – DSD&DICA Lab Manual ………………………………………………………….. 5

a<='0','1' after 20 ns;

RESULT: The truth table of OR,AND,NOR,NAND & EX-OR are verified.

DIET – DSD&DICA Lab Manual ………………………………………………………….. 6

1. Xilinx ISE software

DIET – DSD&DICA Lab Manual ………………………………………………………….. 7

1. Connect circuit as shown in figure.

architecture decoder3x8 of decoder3x8 is

signal S:std_logic_vector(2 downto 0);

end architecture decoder3x8;

ARCHITECTURE behavior OF tb_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

SIGNAL G1 : std_logic := '0';

SIGNAL Y : std_logic_vector(0 to 7);

-- Instantiate the Unit Under Test (UUT)

DIET – DSD&DICA Lab Manual ………………………………………………………….. 9

RESULT: operation of 3-8 decoder using IC 74 LS 138 is verified.

DIET – DSD&DICA Lab Manual ………………………………………………………….. 10

1. Xilinx ISE software

1. Connections are made as per the circuit diagram.

DIET – DSD&DICA Lab Manual ………………………………………………………….. 11

architecture mux8x1 of mux8x1 is

signal s:std_logic_vector(2 downto 0);

DIET – DSD&DICA Lab Manual ………………………………………………………….. 12

end architecture mux8x1;

ARCHITECTURE behavior OF tb_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

SIGNAL C : std_logic := '0';

DIET – DSD&DICA Lab Manual ………………………………………………………….. 13

-- Instantiate the Unit Under Test (UUT)

uut: mux8x1 PORT MAP(

C<='0','1' after 50ns;

VHDL CODE for 1 to 4 Demultiplexer

DIET – DSD&DICA Lab Manual ………………………………………………………….. 14

architecture Behavioral of demux1t4 is

ARCHITECTURE behavior OF tbdemux1t8_vhd IS

DIET – DSD&DICA Lab Manual ………………………………………………………….. 15

-- Instantiate the Unit Under Test (UUT)

en_l <= '1','0' after 10 ns,'1' after 50 ns;

RESULT: The operation of 8 X 1 multiplexer using IC 74 LS 150 and 1X4

DIET – DSD&DICA Lab Manual ………………………………………………………….. 16