4CS1A-Microprocessor & Interfaces (Deployment Updated)

JIET GROUP OF INSTITUTIONS
(A Constitute of Arun Shanti Education Trust, Jaipur) Mogra

National Highway No.65 New Pali Road, Jodhpur-342 002 (Raj.)
Tel: 0291-2868152/53, *E-mail: info@jietjodhpur.com
Web: www.jietjodhpur.com
ACADEMIC ADMINISTRATION OF JGI
Name of the Faculty: Subject with Code: Microprocessor and Interfaces (4CS1A)
Department: Department of CSE (SETG) Semester & Section: IV Date of Preparation:
Total No. of Lectures Planned: 31 Lecture Days:
Actual Delivery
Audit Cell Only

Tutorial Sheet
For Academic
Covered form
Planned Date
Lecture No.
References
Questions
Remarks
Date
Blown Up Syllabus
Zero lecture 0
EXPERT LECTURE -1 – SUBJECT OVERVIEW
EXPERT LECTURE -2
GUEST LECTURE
Unit:-1
Introduction to Micro Computers
 Microprocessors
 Historical Perspective
 Binary Digits
 Microprocessor as a
Programmable Device
1
 Moore Law
 Memory
 Microprocessor as CPU(MPU)
 Organization Of Microprocessor
Based Systems
 Microprocessor ALU, Register
Array, Control Unit
 Microcontrollers
 Advancement in Semiconductor
Technology SSI, MSI, LSI, VLSI,
SLSI
2
 Microcomputers
 Traditional Block Diagram of Micro
Controller
 Block diagram of Microcomputer
 Microcontroller: - Computer on a
Chip.
 Machine & Assembly Language

 Machine language Introduction (First
Generation
 Advantages & Disadvantages
 Assembly Language
1.) Mnemonics 2.) Word 3.) Byte
4.) Assembler 3 T2
 High Level Languages
 Advantages and Disadvantages
 8085 Machine Language
 8085 Assembly language
 Application of Microprocessor
(MCTS)
 Bus Concept
 M Read , M Write , I/O Read, I/O
Write.
 Address Bus
 Data Bus
 Control Bus /Control Signals
 Architecture & Pin Out of 8085
Microprocessor
4 T2
 8085 Pin out diagram
 All Signals Classification.
 Microprocessor
Communication & Bus Timing
 Demultiplexing the Bus AD7 ,AD0
 Generating Control Signals
 Functional Block Diagram
 Various Machine Cycles
 Multiplexing & Demultiplexing of
Buses
 Concept of Multiplexing &
Demultiplexing Of Buses
 Static & Dynamic Memory
 Static RAM
 Dynamic RAM
 Type Of ROM
 Masked ROM
5 T2
 Programmable Read Only
Memory(PROM)
 Erasable Programmable Read Only
Memory (EPROM)
 Electrically Erasable
PROM(EEPROM)
 Flash Memory
 Memory Map
 Memory Map(256 Bytes of Memory)
Unit:-2
Assembly Language & Programming in
8085
 Assembly Language
 Difference between Machine,

Assembly Low Level & High Level
Language
 Assembly language of 8085 6
T1,
 Advantages & Disadvantages
T2
 Classification of Instruction 8085
 Data Transfer Group
 Arithmetic Group
 Logical Group
 Branch Group
Stack, I/O And Machine Control Group
 Instruction set of 8085
 Data Copy Operations with Examples
 Input\Output Operations with
Examples
 Arithmetic Operations with Examples
 Logical Operations with Examples
 Branching Operations with Examples
 Machine Control Operations with
Examples
7
 Stack Operations with Examples T2
 Addressing Modes of 8085
 Register Addressing Mode
 Immediate Addressing Mode
 Direct Addressing Mode
 Indirect Addressing Mode
 Implied Addressing Mode
 Combined Addressing Mode
 Program Structures
 Sequential
 Conditional
 Iterative T1,
8
 Program for various T2
structure
 Programming Technique
 Looping
(a) Continuous Loop T1,
9
(b) Conditional Loop T2
 Counting
 Indexing
 Debugging a Program
 Static Debugging 10 T2
 Dynamic Debugging
Unit 3:-
 Peripherals & Their Interfacing with
8085-Ist
Counter & Timing Delay
 Definitions of Important Terms 11 T2
 T-State
 Machine Cycles
 Instruction Cycle
 Various Machine Cycles

a.Op-Code Fetch Machine
Cycle
b.Memory Read Machine
Cycle
12 T2
c.Memory Write Machine
Cycle
d.I\O Read Machine Cycle
e.I\O Write Machine Cycle
 Counters
 Time Delay
a. Time Delay by using 8
bit Register
b. Time Delay by using 16
T1,
bit Register Pair 13
T2
c. Time Delay using
Nested Loops
 Programming Examples &
 Time Delay Calculation
 Macros & Subroutine
 Macros
 Subroutines
T1,
 Instructions Required 14
T2
For Using Subroutine
 Difference b/w CALL
& JUMP Instruction
 Reusing Register in Subroutine
 Subroutine Documentation
 Nesting
T1,
 Multiple Ending 15
T2
 Subroutine Programs
Related to Subroutine
 Stack
 Introduction to Stack
T1,
 Difference b/w Stack & 16
T2
Stack Pointer
 Defining Stack in R/W
Memory
 Instructions related to Stack
 Application of PUSH & POP
Instruction
 Interrupt Structure & Its Programming
 Introduction to Interrupts
 Software and Hardware
Interrupts
 Accessing Interrupt Service Routine
T1,
 Enabling/Disabling 17
T2
Interrupts by EI &DI
 Priorities of Interrupts
 RIM Instruction
 SIM Instruction
 Vectored Interrupts
 Triggering Levels
 Maskable & Non Maskable
T1,
Interrupts 18
T2
 RST Instruction (Timing
 Diagram)
 Memory Interfacing
 Memory Interfacing Memory
 Flip Flop or Latch as storage Element
 Memory Mapping & Address Mapping
 Tri State Devices Buffer 19 T2
 Examples Of Buffer
 Decoder & Encoder
 D Flip Flop : Latched &
Clocked
 Architecture of (PIC) 8259 Controller
 Introduction to 8259 Controller
 Pin Diagram of 8259
 Registers of 8259
20 T2
 Working of 8259
 Initialization Command Word
 Operational Command Word (OCWs)

 Priority Modes of 8259
 End of Interrupts
21
T1
Unit:-4
 Peripherals and Their Interfacing with
8085-II
22 T1
Interfacing I/O Ports
 Interfacing I/O Devices using
Peripheral Mapped Technique
 Absolute & Multiple Address Decoding

 Interfacing I/O Devices using Memory
Mapped Technique
 Difference b\w Peripheral Mapped &
Memory I/O Interface Technique
 Important Points about Interfacing
 Architecture & interfacing of PPI
(8255)
 Architecture of 8255
 Control Register & Control Word
 Various Modes of 8255
 BSR Mode
o 2.I\O Mode 23 T1
o Mode 0
o Mode 1
 Interfacing of 8255
 Programming 8255 in
 Mode 1
a.Status Check I\O
b.Interrupt Check I\O
 Timer 8254 (PIT)
 Introduction to 8254/8253
 Block Diagram of 8254
24 T1
 Control Register & Control
Word of 8254/8253
 Mode 0 to Mode 5
 Programming of 8254
 8279 Programmable
Keyboard/Display Interface
 Key Debounce
 Functions of Various Pins 25 T1
 Schema of the 8279
 Operating Modes of 8279
 Programming of 8279
 Status Word 8279
Unit:5-
Microprocessor Application:
 Interfacing of Scanned Multiplexed
Display
 Introduction to Scanned
Multiplexed Display
26 T
 Block Diagram of
Multiplexed output Display
 Schematic of a scanned display
a. Interfacing Circuit
b.SN 75491- Segment Driver
c.SN 75492- Digit Driver
 Interfacing of Liquid Crystal

Display(LCD)
 Introduction to LCD T1
 Interfacing LCD using 8255 27 T1
 Data Transfer Timing Diagram of T1
LCD
 Interfacing of Matrix Keyboard

 Introduction to Matrix Keyboard
 Interfacing of Matrix Keyboard using
8255
28 T1
 Flow Chart of Matrix Keyboard
Subroutine
 Combining the Matrix Keyboard &
Scanned Multiplexed Display
 Architecture & Interfacing of USART
8251
1.Pin & Block Diagram of 29 T1
8251
 2.Function of Various Pins
Transmitter & Receiver
4.Control , Status & Data
30 T1
Buffer Register
 5.Initialization of 8251
Revision in Last 8 Lectures
(Discussion regarding solution of Previous
Year University Question Papers)
31 T1
Model Question Papers
Important Questions, Length of Solutions/
Answer in Exams, Time Management in
Exams etc.)
Text/References:
1. Microprocessor architecture, programming, and applications with the 8085 By Ramesh S. Gaonkar
2. Introduction to Microprocessor By Aditya P. Mathur, TMH
3. Microprocessor & Interfaceing By Douglas V. Hall,TMH
4. Microprocessor & Peripheral By A.K.Ray, K.M. Bhurchandi,TMH
Branch: CSE (II Year / IV SEM)

4CS1A: MICROPROCESSOR AND INTERFACES
UNIT 1
SECTION: A.1
1. Explain Bus Organization of 8085 Microprocessor. (RTU-2011)
2. Draw the functional block diagram of 8085 microprocessor architecture and explain it.
(RU 2008, RTU 2009, 10, 11, 12)
3. Draw the pin diagram of 8085 microprocessor and explain its various pins.
(RU 2001, RTU 2012)
4. With references to 8085 microprocessor explain the following registers
(a) Flag register
(b) Stack Pointer
(c) Program Counter (RU 2007)
5. Why are AD7 - AD0 lines multiplexed? With the help of latching circuit, explain how these
lines are multiplexed. (RTU 2009)
6. What are different flags available in 8085 microprocessor? Explain each in brief.
(RTU 2012, RU 2002)
7. Describe the externally initiated signals & control signals and status signals used in 8085.
(RU 2006)
8. What are the advantages of an assembly language in comparison with high level Language?
9. Explain how address & data bus can be demultiplexed in 8085- microprocessor with the help
of Block Diagram? (RTU 2012)
10. Compare static RAM with dynamic RAM. (RTU 2010)
11. Give the classification of the memory.

UNIT 1
SECTION: A.2
1. What are the functions of Instruction register and Decoder? (RTU 2010)
2. Explain the following pins of 8085 microprocessor.
(a) ALE
(b) Ready
(c) HLDA
(d) TRAP
(e) HOLD
(f) SID
(g) INTA’
(h) IO/M’ (RTU 2010)
3. Explain through block diagram the similarities and differences in between Microprocessor
and Microcomputers devices.
4. Explain the following:
(a) Decoder
(b) Tristate Buffer
(c) Latch
(d) Encoder
(e) Demultiplexer [RTU-2010]

UNIT 1
SECTION: B
1. Interface 1-Kbyte of R/W memory to an 8085 system, with the memory map from 3000 H to
33FF H.

4CS1A: BIOMEDICAL INSTRUMENTATION
UNIT 1
SECTION: C
1. The devices that provide the means for a computer to communicate with the user or other
computers are referred to as__________.
2. The software used to drive microprocessor-based systems is called________.
3. The circuits in the 8085A that provide the arithmetic and logic functions are called the__________.
4. How many buses are connected as part of the 8085A microprocessor?
5. How many bits are used in the data bus?
6. The items that you can physically touch in a computer system are called________.
7. Single-bit indicators that may be set or cleared to show the results of logical or arithmetic
operations are the___________.
8. When was the first 8-bit microprocessor introduced?
9. The register in the 8085A that is used to keep track of the memory address of the next op-code to be
run in the program is the___________.
10. The control bus and memories share a bidirectional bus in a typical microprocessor system.
(True/False)
11. Because microprocessor CPUs do not understand mnemonics as they are, they have to be converted
to ________.
12. A register in the microprocessor that keeps track of the answer or results of any arithmetic or logic
operation is the_________.
13. Which bus is a bidirectional bus?
14. Which of the bus is primarily used to carry signals that direct other ICs to find out what type of
operation is being performed?
15. How many bytes make a word of 32 bits?
16. Calculate the number of registers in a 64K memory board.
17. Specify the function of the address bus and the direction of the information flow on the address bus.
18. List the name of 16 bit registers in 8085 microprocessor.
19. What is the function of the WR’ signal on the memory chip?
20. How many address lines are necessary to address 2048K of memory?
21. List the name of Control and Status Signals.
22. Microprocessor 8085 is the enhanced version of _________ with essentially the same instruction
set.
23. The number of status flags in 8085 are__________.
24. Can ROM be used as stack? (True/False)
25. 8085 was introduced in __________.
26. The First Microprocessor was__________.
27. How many nibbles are 16 bits?
28. An instruction register is storage for______________.
29. In microprocessor architecture, flag indicates the______________.
30. The external system bus architecture is created using from ______ architecture.
31. The RAM which is created using bipolar transistors is called___________.
32. Which RAM is created using MOS transistors.
33. ________ is usually the first level of memory access by the microprocessor.
34. DIP stands for__________________.
35. ALE stands for________________.
36. Zero Flag is to _____ if the result of an arithmetic operation is zero.
37. There are two power connection for +5 volts in 8085 they are_______&________.
38. ________and ________lines provide the 8085 with a DMA capability by allowing another
processor on the same system bus to request control of the buses.
39. ______ memory locations can be addressed directly by Intel 8085 microprocessor.
40. What is the use of Bidirectional buffers?
41. Can an RC circuit be used as clock source for 8085?
42. What does Quality factor mean?

UNIT 2
SECTION: A.1
1. Draw the Programming Model of 8085 MPU? Explain the same with suitable example.
(RTU-2013)
2. Explain various addressing modes of 8085 microprocessor by giving examples of each. Also
explain the instruction format. (RTU 2009, 11, 12)
3. Draw and explain the timing diagram of memory write and opcode fetch machine Cycle.
4. Explain following terms with example-
(a) T-state
(b) Machine cycle
(c) Instruction cycle
5. Classify and discuss in detail the different types of instructions available in 8085 microprocessor,
giving an example for each type.
\

UNIT 2
SECTION: A.2
1. What are internal data operations in 8085 and how these are operated using 8085 programmable
registers? (RU 2008)
2. Explain the following instructions: (RTU 2011, 12)
(a) LDAX D
(b) STA 5500H
(c) STAX B
(d) IN 01H
(e) LXI SP, 4000H
(f) SUI 01H
(g) XTHL
(h) CALL 8000H
(i) DAA and DAD
(j) PUSH PSW
(k) XCHG
(l) CMP B
(m)CMA
(n) LDA 5000H
(Write about their function, addressing mode, Number of bytes, Flags affected, Number of
machine cycles)
3. Explain the operational difference between the following pairs of instructions.
(a) SPHL and XTHL
(b) CALL and JMP
(c) INR A and ADI 01H
(d) DAD Rp and DAA. (RTU-2011)
4. Compare the action of microprocessor 8085 for the following pairs of instructions.
(a) MVI A, 00H and XRA A
(b) SUB B and CMP B
(c) JMP 2700 H and PCHL
(d) LDA 2000 H and LHLD 2000H. (RU- 2005)

UNIT 2
SECTION: B
1. Six bytes of data are stored in memory location starting at XX50 H. Add all the data bytes .Use
register B to save any carries generated while adding the data bytes. Display the entire sum at two
output ports or store the sum at two consecutive memory locations, XX70 H, and XX71 H.
2. WAP to arrange the 10 Bytes of data in ascending order and data is stored as an array from
C100H onwards in memory. (RTU-2012)
3. Write an assembly language program to perform exchange of 10 data bytes started at
memory location 2500H onwards (1st Block ) with memory location 3000 H onwards (2nd
Block ).
4. Draw the timing diagram of the following instruction and also explain the same.
(a) LXI B, 2500H
(b) LHLD 2500H
(c) STA 16-bit address
(d) SHLD BABAH
(e) MVI A, 32H
(f) MOV A, B (RTU-2013)
5. Write a program for block move of data from location 2001H onwards to 5327H onwards.
The number of bytes to be moved is available in location 2000H.
6. Write an assembly language program to multiply two 8-bit data stored at location 2050H and
2051H and store the 16-bit result at 2052H and 2053H.
7. Find the square- root of the number stored at memory location 2550H. Store the result at memory
location 2551H.

UNIT 2
SECTION: C
1. The microprocessor 8085 has _____ basic instructions and _____ opcodes.
2. Which instruction that sets the carry flag.
3. Each m/c cycles have ________ T states.
4. ____________and ___________instructions provide a means of moving two bytes between HL
register and a RAM address.
5. PSW stands for contents of _____&_____.
6. Write any two example of one-byte instruction.
7. Write any two example of two-byte instruction.
8. Write any two example of three-byte instruction.
9. The second part of the instruction is the data to be operated on, and it is called ____.
10. The first part of an instruction which specifies the task to be performed by the computer is called
_______.
11. The status of S0 and S1 pins for memory read is________.
12. The status of S0 and S1 pins for memory write is_______.
13. The status of S0 and S1 pins for opcode fetch is________.
14. Status register is also called as ___________.
15. After the execution of CMA instruction, the status of Z and CY flags are respectively______
&_______.
16. To reset carry without affecting accumulator contents, we have to use ________ instruction.
17. In order to complement the lower order nibble of the accumulator, we can use ________
instruction.
18. Let the contents of C register be 00000000. The contents of C register after execution of DCR C is
_________.
19. Which instruction will never affect the zero flag?
20. A single instruction to clear the lower 4 bits of accumulator in 8085 is________.
21. To save accumulator value on to the stack, which of the instruction may be used?
22. If the contents of register B are greater than the contents of accumulator, CMP B will affect carry
flag, zero flag respectively as______&_____.
23. The status of S, Z, CY flags after execution of following instructions are________.
MVI A, A9H
MVI B, 57H
ADD B
ORA A
24. After the execution of XRA A instruction, which _________ flag is set?
25. The first machine cycle of an instruction is always___________.
26. What is the addressing mode used in instruction MOV M, C?
27. How many and what are the machine cycles needed for execution of MOV D, C?
28. The total number of memory accesses involved (inclusive of the op-code fetch) when an 8085
processor executes the instruction LDA 2003 is_______.
29. What do you mean by wait state? What is its need?

UNIT 3
SECTION: A.1
1. Explain the concept of ‘Subroutine’ in 8085 assembly language.
2. What is stack? Explain the use of stack pointer and how it is affected by instructions such as
PUSH, POP, CALL and RET. (RTU-2014)
3. Difference between Macro and Subroutine. Give suitable example.
4. What is peripheral mapped I/O and Memory mapped I/O? Differentiate between them.
(RTU-2012)
5. Distinguish between:
(a) Maskable and non maskable interrupts.
(b) Macro & Subroutine. [RTU-2010]
6. Explain the interrupts structure of 8085 microprocessor with suitable diagram. Draw the RIM
and SIM format. Also classify the different types of interrupts available with 8085
microprocessor. (RTU-2009)
7. Draw the block diagram of 8259 programmable interrupt controller (PIC) & explain the
functions of various blocks. (RU- 2007,RTU 2011)
8. Explain the following modes of 8259 A.
a) Full Nested Mode
b) Rotating Priority

UNIT 3
SECTION: A.2
1. Write instruction to set up time delays using register-pair and a loop within a loop technique (nested
technique).
2. Illustrate the memory addresses range from 0000H to 00FFH of the chip with 256 byte of memory.
Also show, how changing the hardware of chip select (CS’) logic can modify the range of memory
addresses from 5000H to 50FFH.

UNIT 3
SECTION: B
1. Write an ALP to provide a time delay of 0.5ms for an 8085 µp operating at 2MHz frequency.
2. Write program to count continuously in hexadecimal from FF H to 00 H is a system with 0.5 micro
sec clock period , use register C to set up a one millisecond delay b/w each count and display the
numbers at an O/P port . Show delay calculation also.
3. Interface a 2K bytes R\W memory using 3 to 8 decoder. Use O1 O/P line of decoder for
generating chip enable signal. Draw necessary schematic diagram. Compute the address for
this memory. [RTU-2011]
4. Write a program to perform following:
(a) Initialize the Stack Pointer register with XX99H. Clear the memory location starting
from XX90H to XX9FH.
(b) Show the contents of stack after program execution.
(c) Push the contents of register pairs BC, DE, HL on the stack.
5. Write a program to display count 0 to 9 at output port 0AH for a microprocessor system
having clock frequency of 1MHz. A one second delay must be provided between each count.
Use register pair DE to set up delay. At the count of 9, the counter should reset itself to zero.
At the count of 9, the counter should reset itself to zero and repeat the sequence continuously.
6. Write an assembly language program to generate a delay of 0.4 sec if the crystal frequency is
5MHz. [RTU-2010]
7. Show how you will connect a 2K*8 RAM and 4K*8 ROM to 8085 microprocessor. Give all
necessary details of connection. Also show the system memory map.
8. Interface two chips of 4K byte RAM and two chips of 2K byte ROM to MP 8085, by absolute
decoding using 74LS 138 decoder. Give the memory map starting at address 8000H for EPROM.
[RTU-2011]
9. Design a microprocessor system for 8085 microprocessor such that it should contain 8 KB of
EPROM and 8KB of RAM. Properly address the two memories and give detail address map.
(RTU 2010)
10. Explain in detail the interfacing of 8259 with 8085 microprocessor giving the pin details of 8259.

UNIT 3
SECTION: C
1. The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs
writing different data to the same bus.
2. The technique of assigning a memory address to each I/O device in the computer system is
called_____________.
3. Which is used to store critical pieces of data during subroutines and interrupts?
4. Which signal causes the microprocessor to immediately terminate its present activity?
5. Which interrupt has the highest priority?

6. What are level Triggering interrupts?
7. Which stack is used in 8085?
8. RIM is used to check whether, ______.
9. An interrupt initiated by a signal on the NMI pin is called a __________.
10. Two general class of interrupt are__________________ and _______________.
11. A ________is a segment of code that needs to be written only once but whose basic structure can be
caused to be repeated several times within a source module but placing a single statement at the
point of each appearance.
12. How many address lines in a 4096 x 8 EPROM CHIP?
13. Which interrupts are generally used for critical events?
14. The interrupt vector address for RST 5.5 is____________.
15. The interrupt vector address for RST 6.5 is____________.
16. Address line for RST 3 is__________.
17. What is software interrupt?
18. What is RST for the TRAP?
19. The interrupt vector address for TRAP is______.
20. In response to RST 7.5 interrupt, the execution of control transfers to memory location.______.
21. Which interrupt is both level and edge sensitive?
22. The number of software interrupts in 8085 is ____.
23. If instruction RST 5 is written in a program will jump to location________.
24. The execution of instructions MVI A, 10H and SIM will enable all three interrupts (7.5, 6.5 and
5.5). (True/False)
25. Instruction RIM is used to disable the interrupts 7.5, 6.5 and 5.5. (True/False)
26. Whenever the POP H instruction is executed, ___________.
27. The instruction RST 7 is a_____________.
28. How many T-states required for JNZ LOOP if condition is false?
29. Which line will be activated when an output device require attention from CPU?
30. When the 8085 processor checks for an interrupt?
31. What is the use of Full Nested Mode in 8259?

32. ___ bit in ICW1 indicates whether the 8259A is cascade mode or not? SNGL=0
UNIT 4
SECTION: A.1
1. Explain the control word in 8255 PPI .Explain its purpose and format. What are the different
modes of operations possible in 8255? (RTU-2014)
2. Explain with a block diagram the 8255(PPI).What are different modes. Give the format of control
word and what is set/reset mode? How will you use it?
3. Explain the Bidirectional data transfer mode (mode 2) of 8255.
4. Explain 8254 Programmable interval timer with the help of block diagram & it’s modes of
operations. (RTU-2010)
5. Draw the block diagram of 8279 programmable keyboard/Display interface & explain
functions of various blocks. (RTU-2013)
6. Explain various programming modes of 8279 keyboard and display controller. Also draw a
block diagram showing its interfacing with microprocessor.

UNIT 4
SECTION: A.2
1. Draw the circuit, illustrating the interfacing of microprocessor with an Input port using peripheral
mapped technique, showing various control signals. Use a NAND gate for decoding the address of
the Input port, such that the port address should be 52H. Also explain the interfacing circuit in
detail.
2. Design an interfacing circuit to interface one Input port and one Output port, such that the port
address of the Input port should be 80H and the port address of the Output port should be 82H. Use
3-to-8 decoder to decode the address.
3. Write BSR Control Word to set and then reset bit PC4 of Port C of 8255 PPI. Also write the
set of instruction to be used.

UNIT 4
SECTION: B
1. Design a square wave generator with a pulse width of 100 micro seconds by using 8254 timer. Set
the timer in mode 3. The clock frequency is 3 MHz.
2. An 8255 interfaced in memory-mapped I/O so that its address range is 8000H – 8003H. Frame
control word for the following configuration (Mode 0).
(a) Port A: Input
(b) Port Cl : Output
(c) Port Cu : Input
d) Port B: Not Used
3. Interface 8255 PPI with 8085 microprocessor in mode 0.
4. Initialize an 8254 programmable interval use counter 2 with a count 50,000 10. Frame
control word, Write initialization sequence to load the counter. Given that the address of
control register and counter 2 are 83H & 82H respectively.
(RU 2002)

UNIT 4
SECTION: C
1. What type of circuit is used at the interface point of an output port?
2. I/O mapped systems identify their input/output devices by giving them a(n) ________.
3. What type of circuit is used at the interface point of an input port?
4. How many modes in PPI 8255?
5. How many modes in PIT 8254?

6. Which mode in 8254 generate square wave?
7. What is the use of MODE-2 in 8255?
8. List the operating modes of 8255 programmable Peripheral Interface (PPI).
9. The interface peripheral used with keyboard is___________.
10. Interfacing devices for DMA controller, Programmable Interval Timer (PIT) are
respectively________&________.
11. What is a control word?
12. What is the size of ports in 8255?
What is the purpose of control word written to control register in 8255?
13. What are the features used mode 2 in 8255?
14. What happens during DMA transfer?
15. Give some examples of port devices used in 8085 microprocessor based system?
16. Write the advantages of differential data transfer?
17. What are the various programmed data transfer methods?
18. What are the Control signals used for DMA operation?
19. What are the signals used in input control signal & output control signal?
20. What is Read-Back Command?
21. Write BSR control word to set and then reset bit PC4.
22. Write the control word format for 8254?
23. In 8279 Strobed input mode, the control line goes low. The data on return lines is
strobed in the ____.
24. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to
interrupt the CPU.
25. In 8279 Status Word, data is read when ________ pins are low, and write to the display RAM with
____________ are low.
26. The 8279 normally provides a maximum of _____ seven segment display interface with CPU.
27. In 8279, the keyboard entries are debounced and stored in an _________, that is further accessed by
the CPU to read the key codes.

UNIT 5
SECTION: A.1
1. Write short note on IEEE 488. [RTU-2010]
2. Explain the detailed structure and working of segment driver.
3. Explain the detailed structure and working of digit driver.
4. Differentiate between synchronous and Asynchronous transmission. [RTU-2011]
5. Explain Control, Status & Data Buffer Register of USART 8251. [RTU-2010]
6. Differentiate between Serial Port and Parallel Port.
7. Briefly explain serial communication methods and standards. [RTU-2009,2010]
8. Draw the block diagram and pin description of USART 8251 and briefly explain formats of its
modes, command and status words. [RTU-2010,2011]
9. Compare RS-422A and RS423A serial data standards.
10. Write brief note in bus standard RS232C and IEEE 488.
11. Explain RS-232C.
12. What is difference between UART and USART? Describe the function of DSR, DTR, RTS, CTS,
TXD and RXD signals exchanged between a terminal and modem.
UNIT 5
SECTION: A.2
1. What is the role of segment driver and digit driver for multiplexed scanned display?
[RTU-2009]
2. Draw a schematic to interface 16-Key matrix keyboard using Port C of the 8255. Write instruction
of initialize the port. [RTU-2008]
3. Describe Interfacing DTE & DCE using RS232C.

UNIT 5
SECTION: B
1. Interface 8 switches and a seven segment display to 8085 through 8255 PPI. Write a program to the
switch when a switch is open. Assume that the 8255 is interfaced in memory mapped IO technique.
2. Interface a 20keys matrix keyboard using port B and C of the 8255.Write a keyboard with a
software key debounce to read the keyboard and return the equivalent binary code of the key
pressed in the accumulator. [RTU-2010]

UNIT 5
SECTION: C
1. RS-232 is used in _________.
2. There are ______ segments LEDs in scanned multiplexed displays. 7
3. Compared with RS-232, USB is faster and uses___________.
4. What is segment driver?
5. In scanned multiplexed displays _______ should sink seven or eight times that current.
6. Define command word register of 8251.
7. USART stands for___________________
8. Write the Difference between LCD and LED?
9. The number of hardware chips needed for multiple digit display can be minimized by using the
technique called ______.
10. What do you understand about multiplexed display?
11. Expansion for DTE is ______.
12. These are _______ common cathode in scanned multiplexed displays.
13. Write the difference between Synchronous and Asynchronous Transmission?
14. An RS-232 interface is ____________.
15. What is RS-422A?
16. What is RS-423A?

17. The _________ reduces the number of connections, thus the number of interfacing device required.
18. Write difference between RS-232C, RS-422A and RS-423A.
19. What is current loop?
20. What is the use of 8251(USART)?
21. Expansion of DCE ________.
22. What is use of Data buffer register in USART?
23. Write the function of SYNDET/BD pin in 8251?
24. I/O ports of programmable devices are limited in current capacity, therefore, additional transistors
or ICs called ________.
25. The 8251 is based in a _____ pin DIP
26. What are simple Half Duplex and Full Duplex modes of communication?
27. Write serial communication standards?
28. The output line of interfacing circuit is used in _____.
29. Speed of data transmission is measured in term of____________.
30. Data are transmitted in both directions, this technique is called______________.
31. Write the function of modem control in 8251?
32. The ______ is called segment or digit driver.
33. Define mode word register of 8251 for asynchronous mode.
34. Define mode word register of 8251 for synchronous mode.
35. Write status word of 8251?
36. What is parallel Interface?
37. GPIB stands for________________.
38. Write Bus configuration of IEEE-488.
39. Write the factors that depend on Serial data transmission.
40. The SN75491 and SN75492 have ________ and _________ Darlington pair transistors in a
package.
41. In serial I/O, data can be transmitted as either current or voltage.(True/False)
42. The advantage of current loop method is that signals are relatively noise-free and suitable for
transmission over a distance. (True/False)
43. ____________ is a commonly used input device when more than 8 key are necessary.
44. Difference between Serial port and parallel port.
45. What is the use of C/D’ pin in USART 8251
46. In multiplexing, the data lines and output ports are time shared by ______.
47. Rs-232 was introduced in _________.

4CS1A-Microprocessor &amp; Interfaces (Deployment Updated)

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JIET GROUP OF INSTITUTIONS

(A Constitute of Arun Shanti Education Trust, Jaipur) Mogra

Audit Cell Only

EXPERT LECTURE -1 – SUBJECT OVERVIEW

 Machine & Assembly Language

 Difference between Machine,

 Various Machine Cycles

 Operational Command Word (OCWs)

 Absolute & Multiple Address Decoding

 Interfacing of Liquid Crystal

 Interfacing of Matrix Keyboard

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

5. Which interrupt has the highest priority?

31. What is the use of Full Nested Mode in 8259?

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

5. How many modes in PIT 8254?

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

Branch: CSE (II Year / IV SEM)

16. What is RS-423A?

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4CS1A-Microprocessor & Interfaces (Deployment Updated)

4CS1A-Microprocessor & Interfaces (Deployment Updated)