VHDL IMPLIMENTATION OF A MAC

BASED FIR FILTER

A
Thesis Submitted
in partial fulfillment of the requirements for the award of the degree
Of
MASTER OF TECHNOLOGY
In
VLSI AND EMBEDDED SYSTEMS
Submitted By,
PRAVASMITA BEHERA
REGD. NO.:1107999013

CENTRE FOR MICROELECTRONICS

BIJU PATNAIK UNIVERSITY OF TECHNOLOGY
ROURKELA, ODISHA
2013-14
VHDL IMPLIMENTATION OF A MAC
BASED FIR FILTER
A
Thesis Submitted
in partial fulfillment of the requirements for the award of the degree
Of
MASTER OF TECHNOLOGY
In
VLSI AND EMBEDDED SYSTEMS
Submitted By,

PRAVASMITA BEHERA
REGD. NO.:1107999013

Guided By,
PROF.J.K DAS
READER, DEPT OF I&EE
KIIT, BHUBANESWAR
And
PROF. ANANYA DASTIDAR
LECTURER, DEPT. OF IEE
CET, BHUBANESWAR

CENTRE FOR MICROELECTRONICS

BIJU PATNAIK UNIVERSITY OF TECHNOLOGY
ROURKELA, ODISHA
2013-14
 CENTRE FOR MICROELECTRONICS
BIJU PATNAIK UNIVERSITY OF TECHNOLOGY
ROURKELA, ODISHA

CERTIFICATE
This is to certify that the thesis entitled “VHDL IMPLIMENTATION OF A MAC FIR

FILTER” submitted by Pravasmita Behera, Registration number 1107999013, in partial

fulfillment of the requirements for the degree of Master of Technology, during session 2012-13

in the department of VLSI and Embedded Systems of Centre For Microelectronics, BPUT,

Odisha, is a bona-fide work carried out by her under my supervision and guidance.

I believe that the thesis fulfills part of the requirements for the award of degree of Master

of Technology. Neither this dissertation nor any part of it has been submitted for any degree or

academic award elsewhere.

SUPERVISOR SUPERVISOR EXTERNAL EXAMINER

 ACKNOWLEDGEMENTS

I take this opportunity to thank all those concerned, who have helped me to successfully
complete the thesis work.

I would like to express my sincere gratitude to Prof. J.K DAS Associate Professor, Dept. of ECE,
KIIT, DEEMED university and Prof. Ananya Dastidar, Lecturer, Dept. of IEE, CET , for their
constant guidance, encouragement and help, without which, the thesis in its present form would
not have completed in time.

I would like to thank Prof. (Dr.) Aruna Tripathy, Reader, Dept.of IEE, CET and for encouraging
and helping me, whenever I needed help.

I would like to thank Prof. (Dr.) Chandrabhanu Mishra, Director, Centre for Microelectronics,
BPUT, for supporting and inspiring us all the way.

I also thank my friends Shaktijeet, Rosalin, and Jasmin for all the constructive criticism and
ideas.

Last but not the least,I would like to thank my parents,Mr.Baikuntha Nath Behera and Mrs.
Santilata Behera for their constant encouragement, patience and love.

PRAVASMITA BEHERA

Regd No. 1107999013

 LIST OF FIGURES
FIG FIGURE NAME PAGE
NO NO
2.1 Direct Form FIR Filter 6
2.2 Cascade Form FIR Filter 7
2.3 Lattice Form FIR Filter

3.1 Basic Mac Unit

3.2 Block Diagram of MAC unit
3.3 Gate Schematic for 4-bit carry-look ahead logic in a NAND-NAND network
3.4 4 Bit Carry look ahead adder
3.5 16bit carry look ahead adder
3.6 Gate Schematic for group propagate and group generate
3.7 Block Diagram of CLA
3.8 RTL schematic of CLA
3.9 Block Diagram of Booth Multiplier
3.10 RTL Schematic Of Booth Multiplier
3.11 RTL Schematic of D-Flip-flop
3.12 Block Diagram of MAC unit
3.13 RTL Schematic of MAC unit

4.1 7 Tap Fir Filter Structure

4.2 Mac Fir Filter Structure
4.3 Magnitude Response of filter
4.4 Generation of filter coefficients
4.5 Block Diagram of MAC FIR FILTER
4.6 RTL SCHEMATIC OF MAC FIR FILTER
4.7 Internal Structure of Instant=coe_mux0000 (2) _imp,
Type=coe_mux0000<2>_imp
4.8 Internal Structure of Instant=din_mux0000 (7) _imp
4.9 Simulation waveform of MAC FIR FILTER
 LIST OF TABLES

TABLE TABLE NAME PAGE

NO NO
2.1 18
 LIST OF ABBREVATIONS
1-D, 1D One Dimensional
2-D, 2D Two Dimensional
ASIC Application Specific Integrated Circuits

CLA Carry Look Ahead Adder

CMOS
CSA Carry Save Adder

DFT Discrete Fourier Transform

DSP Digital Signal Processors; Also Digital Signal Processing
FDC
FFT
FIR Finite Impulse Response
FM Frequency Modulation
FPGA Field Programmable Gate Array
GCLK

HA Half Adder
IC Integrated Circuits
IDFT Inverse Discrete Fourier Transform
IEEE Institute of Electrical and Electronic Engineers
IIR Infinite Impulse Response
IOB
IP Intellectual Property (IP)
ISE

LUT
MAC Multiply and Accumulate
RCA Ripple Carry Adder
RTL Register Transfer Level
SOC System on Chip

VLSI Very Large Scale Integrated Circuits

VHDL Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
 CONTENTS
SL CHAPTER NAME PAGE
NO NO
1 Introduction 1
2 Literature Survey

2.1 Introduction 3
2.2 Advantages of fir filters
2.3 Terms Are Used In Describing Fir Filters
2.4 Linear Phase
2.4.1 Linear Phase Filter
2.4.2 Condition for Linear Phase
2.4.3 Delay of a Linear-Phase Fir
2.5 Realization of Fir Filters
2.6 Structure for Fir Systems
2.6.2 Cascaded Form
2.6.1 Direct Form
2.6.3 Lattice Form:
2.7 Methods Of Designing Fir Filters
2.7.1 Design by Fourier series Method
2.7.2 Design of Fir Filter by Window Technique
2.7.3 Design of Fir Filter by Frequency Sampling Method
2.8 Typical Design Requirements
2.9 Special Types Of Fir Filters
2.10 Related Work
2.11Conclusion

3 Design Of Mac

3.1 Introduction
3.2 Overview of Multiplier- Accumulator Unit
3.3 Operation of MAC
3.3.1 A Carry-Look Ahead Adder
3.3.2 Booth Multiplier
3.3.3 D-Flip-Flop
3.4 Simulation and Synthesis Tools
3.5Implementation of MAC
3.6Conclusion
4 VHDL Implementation Of Mac Fir Filter
4.1 Introduction
4.2VHDL Implementation of Fir Filter
4.3 Generation of Filter Coefficients
4.4 VHDL Design Report
4.5 Simulation Result
4.6Conclusion

5 Conclusion and Future scope 87

6 References 88