IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO.

5, MAY 2019 2081

A Compact Model for Digital Circuits Operating

Near Threshold in Deep-Submicrometer
MOSFET
Wenjie Wang , Pingping Yu, and Yanfeng Jiang , Member, IEEE
Abstract — Integrated circuits operated in the near- simple calculations of the delay and energy. In 2013, a
threshold region exhibit specific merit with high energy near-threshold model was proposed by using the parameter
efficiency. A near-threshold model is highly required for fitting method [9]. In 2010, Markovic et al. [10] introduced a
the circuit design. In this paper, a near-threshold drain
current model is proposed based on the surface inversion method for modeling of delay and energy in the near-threshold
layer charge model for analyzing digital circuits. The short- region as a function of the essential design parameters.
channel effect in deep submicrometer is also included in In this paper, a near-threshold drain current model is set up
the model. Moreover, the delay and energy parts based based on the inverse-charge model. The model includes the
on the near-threshold drain current model are derived and drain-induced barrier lowering (DIBL) effect for better accu-
integrated in the model. Two process design kits (PDKs) are
used for parameter extraction to demonstrate the feasibility racy when analyzing deep submicrometer circuits. Moreover,
of the proposed model. The results show that the proposed the delay and energy parts are included in the model. The key
model can be used for the near-threshold circuit calculation, parameters in the model are extracted based on the process
with the benefit of high accuracy. design kits (PDKs) supported by foundries. In this way,
Index Terms — Energy efficient, inversion layer charge the accuracy of the model can be fulfilled and demonstrated.
model, near threshold, parameter extraction.
II. N EAR -T HRESHOLD D RAIN C URRENT M ODEL
I. I NTRODUCTION In this paper, the drain current model is based on the inverse-
charge modeling [7]. Inversion-charge model is directly related
H OW to reduce the power of an integrated circuit is a
critical problem all the time, especially in submicrometer
region. One of recent effective methods is the reduction on
to the derivation process and the geometrical structure of the
device
 ∞  ∞
the supply voltage with the sacrifice on the operation speed.
i d,s = i f − i r = qi dv c − qi dv c (1)
Intel demonstrated a 32-nm pentium processor relied on the vs vd
solar energy supply at ISSCC 2012, succeeded in operating where forward current i f is independent of the drain voltage
at 3-MHz frequency under 280-mV voltage [1]. To reduce while reverse current i r is independent of the source voltage.qi
the power dissipation and guarantee the performance, one of is the normalized inversion charge.v c is the channel voltage.
the effective approaches is to design a circuit operated in v s and v d are corresponding to the voltages of the source and
near-threshold region. the drain terminals. The model is symmetric with respect to
The near-threshold circuit design becomes one of the the source and drain. The forward and reverse components are
hotspots in recent years. Various structures of near-threshold of the same form. Using a combined notation to indicate both
circuits have been proposed, such as SRAM, phase-locked i f and i r [9], one can get
loop, and charge pump [2]–[4]. Several device models for the  ∞
near-threshold MOS transistor were also proposed [5], [6], i f,r = qi dv c . (2)
[8]–[12]. A typical near-threshold drain current model was v s,d
proposed in [7] and used in the digital circuit design. However, The normalization factors are as follows:
the delay and power parameters are not included in the
−Q i
model. In 2010, Harris et al. [8] proposed a transregional qi =
near-threshold model with semiempirical data fitting, including 2nϕ t Cox
Ids 2nμCox ϕt2 W
Manuscript received January 8, 2019; revised February 20, 2019; I0 = =
accepted March 13, 2019. Date of publication April 1, 2019; date of i ds L
current version April 22, 2019. This work was supported by the National Vs Vd Vg Vp Vc Vb
Nature Science Foundation of China (NSFC) under Grant 61774078. The ϕt = = = = = = (3)
review of this paper was arranged by Editor B. Iñiguez. (Corresponding
vs vd vg vp vc vb
author: Yanfeng Jiang.) where Q i is the inversion charge, Cox is the grid capacitance,
The authors are with the Department of Microelectronics, College
of Internet of Things Engineering, Jiangnan University, Wuxi 214122, and n is the slope factor. μ is the mobility. W and L are the
China (e-mail: 981169842@qq.com; pingpingyu@jiangnan.edu.cn; gate length and the gate width. ϕt is the thermal voltage. v g
jiangyf@jiangnan.edu.cn). denotes the normalized grid voltage. v p is the pinchoff voltage.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. Vb is the body voltage on the device. The body region
Digital Object Identifier 10.1109/TED.2019.2905895 tends to be depleted of majority carriers during the normal

0018-9383 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2082
Fig. 1. Relationship between the channel voltage and the charge of
the MOS device. Inset shows that the near-threshold model and the
standard model are approximated in the near-threshold region. The near-
threshold model fits more accurate compared with the weak-inversion
model and the strong-inversion model in the near-threshold region.
Equation (5): standard model. Equation (12): near-threshold model.
Equation (9): strong-inversion model. Equation (7): weak-inversion
model.
device operation, which is dependent on the body voltage.
Here, we define Vb = 0 V to make the model be suitable
for the partially depleted (PD) device instead of the fully
depleted (FD) device. The device in the near-threshold region
is PD under such condition of Vb = 0 V. Under Vsb > 0 V,
the device is FD, and the top and back gates are in control of
the channel charge.
The normalized relationship between the inverse-charge
density and the channel voltage is expressed as [13]
2q i + ln qi = v p −v c . (4)
Applying the Lambert W function [14] to solve (4), the
following equations are derived:
W0 (2ev p −v c )
qi = (5)
2
 2
W0 (2ev p −v c ) W0 (2ev p −v c )
i f,r = + . (6)
2 2
For the Lambert W function image [14], the upper branch
with W (x) ≥ −1 is the function W0 (x), the lower branch
with W (x) ≤ −1 is the function W−1 (x). Equation (6) is
the accurate relationship of the MOS transistor drain current
without considering the second-order effects. It is defined as
a standard model in this paper.
Fig. 1 shows the normalized relationship between the inver-
sion charge and the channel voltage. Fig. 2 shows the nonlinear
relationship between the drain current and the channel voltage
based on (6). This equation also helps to correlate i f,r with
the standard operating regime, weak, moderate, and strong
inversion.
In the weak inversion, there is no pinchoff voltage in the
channel and v p −v c  0. The logarithmic term dominates
in (4), and there is 2q i + ln qi  0. Ignoring the linear term
in (4), (7) can be obtained
qi ≈ e v p −v c
. (7)
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 5, MAY 2019
Fig. 2. Relationship between the channel voltage and the current of
the MOS device. Inset shows that the standard model and the EKV
model are approximated in all the regions. The near-threshold model fits
more accurate compared with the weak-inversion model and the strong-
inversion model in the near-threshold region. Equation (6): standard
model. Equation (13): near-threshold model. Equation (10): strong-
inversion model. Equation (8): weak-inversion model. Equation (11): EKV
model.
In the strong inversion, v p −v c  0. The linear term dom-
inates in (4). On the condition, 2q i + ln qi  0. Ignoring the
logarithmic term, (4) is simplified as
(v p −v c )
qi ≈ . (9)
2
Substituting (9) into (1), one can get
  2
v p −v c
i f,r ≈ . (10)
2
The EKV model in the whole region is [13]
v p −v s,d
2
i f,r ≈ ln 1 + e 2 . (11)
Based on the above-mentioned mathematical analysis,
the linear term dominates in the strong inversion while the
logarithmic term dominates in the weak inversion. However,
the linear term and the logarithmic term are not the main part
in the moderate inversion. So, how to determine the expression
in the moderate inversion is different from the above analysis.
From [9], the near-threshold model is
qi ≈ k0 [k1 + 2k2 (v p −v c )]ek1 (v p −v c )+k2 (v p −v c ) . (12)
2
i f,r ≈ k0 ek1 (v p −v s,d )+k 2 (v p −v s,d )
2
(13)
where k0 = 0.54, k1 = 0.69, and k2 = −0.033. The max-
imum absolute error between the near-threshold model (13)
and the standard model (6) is 21%.
Substituting (13) into (1) resulting in
i ds = k0 ek1 (v p −v s )+k2 (v p −v s ) − k0 ek1 (v p −v d )+k2 (v p −v d ) . (14)
2 2
Removing the normalization and substituting
v p ≈(Vg − Vt /nϕt ) [13] into (14), one can get
   2
Vg −Vt V −V
Substituting (7) into (1), (8) is expressed as k1 − Vϕst +k2 gnϕt t − Vϕst
Ids = I0 k 0 e nϕt
   2
i f,r ≈ ev p −v s,d . (8) k1
Vg −Vt V V −V V
− ϕdt +k2 gnϕt t − ϕdt
−I0 k 0 e nϕt
. (15)
WANG et al.: COMPACT MODEL FOR DIGITAL CIRCUITS OPERATING NEAR THRESHOLD 2083

In the following derivation, let Vb = Vs to eliminate the

body effect. Letting Vg = Vgs , Vd = Vds , Vs = 0V, so
   2
Vgs −Vt Vgs −Vt
k1 +k2
Ids = I0 k 0 e nϕt nϕt
⎛ ⎞
−V ds n 2 Vds
2 −2nV V +2nV V
ds gs ds t
k1 +k2
× ⎝1 − e ⎠.
ϕt n 2 ϕt2
(16)

Letting VDD = Vds = Vgs , (16) is simplified to

 2
VDD −Vt VDD −Vt
k1 +k2
ION = I0 k 0 e nϕt nϕt
⎛ ⎞
−V DD n2 V D
2 −2nV 2 +2nV
DD Vt
ϕt +k2
k1 D DD
× ⎝1 − e n 2 ϕt2 ⎠. (17)

VDD is several times larger than ϕt while it is less than twice

Vt . So, the terms within parentheses can be approximated Fig. 3. Near-threshold drain current model (19) against a SPICE
as unity simulation of the 90-nm mixed-signal process. (a) 90-nm regular devices.
VDD −Vt
k1
ION = I0 k 0 e nϕt
Equation (18) is the drain current of a logically “ON”
transistor as a function of the supply voltage proposed in [9].
The near-threshold model is derived based on the long/wide
channel device. However, DIBL is a major effect governing
short-channel devices of deep-submicrometer CMOS tech-
nologies [15]. Ignoring the effects of DIBL can result in an
order of magnitude of error [8]. In this paper, to make the
model be suitable for deep submicrometer, the DIBL effect is
included in the near-threshold model. Vt is influenced by VDD
at the short-channel length. The effective threshold voltage
can be expressed as Vt − ηVDD, where η is the DIBL factor.
Considering this effect, (18) can be expressed as
 2 (b) 90-nm low-threshold devices. (c) 90-nm near-threshold devices.
VDD −Vt (d) 90-nm high-threshold devices.
+k2
nϕt
. (18)
to determine the lower bound and upper bound of the near-
threshold model. The mean absolute error is the average value
of the errors between the upper and lower voltages, which
is used to evaluate the accuracy of the model within its
applicable range. The parameters are extracted by adopting
the least-squares method in the near-threshold model. Based
on the results shown in Table I, the extracted near-threshold
model parameter values are close to those provided in the
PDKs due to including the DIBL effect. The temperature
is set to 70 °C, and it is desirable to include the thermal
coefficient in the extracted parameters. We also explored the
near-threshold drain current model at different temperatures.
For the nMOS device, the parameters of I0 , Vt , n, and η are all
 2 physically related to the temperature. The results are shown in
(1+η)VDD −Vt (1+η)VDD −Vt
k1 +k2 .
ION = I0 k 0 e nϕt nϕt
(19) Table II. With the temperature increasing, I0 becomes smaller,
Vt decreases, and n and η become larger [16], [17].
Equation (19) is the proposed near-threshold model.
The key parameters (I0 ,Vt , n, and η) influence the accuracy III. N EAR -T HRESHOLD D ELAY AND E NERGY M ODELS
of the model. Careful extraction should be conducted to
The delay and energy models are included in the near-
improve the accuracy.
threshold model. The delay of a gate can be approximated as
In this paper, a 65-nm low-power process and a 90-nm
mixed-signal process are used to extract the parameters. kn Cload VDD
t pd = . (20)
The 65-nm low-power process includes regular devices, low- ION
threshold devices, and high-threshold devices. The 90-nm kn is a fitting parameter. Combining (19) and (20) gives a
mixed-signal process includes regular devices, low-threshold near-threshold delay model
devices, near-threshold devices, and high-threshold devices.  2
(1+η)VDD −Vt (1+η)VDD −Vt
Fig. 3 shows the simulation results of the near-threshold drain kn Cload −k −k2 .
t pd = VDD e 1 nϕt nϕt
(21)
current model based on the 90-nm mixed-signal process. The I0 k 0
simulation results are plotted within the whole VDD operating kn , I0 , and k 0 are the fitting constants. Equation (19) can
range to observe when the model deviations occur. It can be be simplified as
seen that the two curves are fit well in the near-threshold  2
(1+η)VDD −Vt (1+η)VDD −Vt
Cload −k −k2 .
region. t pd = VDD e 1 nϕt nϕt
(22)
Table I shows the key parameters of the near-threshold drain kf
current model, in which the key parameters are extracted based Cload is the load capacitance. k f is a new fitting parameter.
on the commercial technology process. Different technologies When (22) is applied to a circuit, the delays of the nMOS
are used for comparison and for the parameter extraction. The and pMOS transistors can be calculated, separately. In this
size of the device, the supply voltage, the value of parameters, paper, the delay model is used to calculate the mean propa-
and the errors are shown in Table I. The 21% error is used gation delays of nMOS and pMOS transistors in the circuits.
2084 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 5, MAY 2019

TABLE I
F ITTING THE N EAR -T HRESHOLD D RAIN C URRENT M ODEL F ROM 180 TO 700 mV
U SING 65-nm L OW-P OWER AND 90-nm M IXED -S IGNAL P ROCESSES

TABLE II
F ITTING THE N EAR -T HRESHOLD D RAIN C URRENT M ODEL U SING
90-nm M IXED -S IGNAL P ROCESS W ITH R EGULAR N MOS D EVICES
F ROM 180 TO 700 mV AT D IFFERENT T EMPERATURES

TABLE III
F ITTING THE N EAR -T HRESHOLD D ELAY M ODEL U SING 90-nm
M IXED -S IGNAL P ROCESS W ITH R EGULAR D EVICES
F ROM 180 TO 700 mV
Fig. 4. Near-threshold delay model (22) against a SPICE simulation
of the 90-nm mixed-signal process for different circuits. (a) FO1 delay.
(b) FO4 delay. (c) FO8 delay. (d) NAND2 delay.

The parameters values are the average results of nMOS and

pMOS devices. Therefore, the parameters are needed to be
refitted for the delay model. Compare the fitting parameters
shown in Tables I and III, the maximum error of Vt is 12%,
the maximum error of n is 11%, and the maximum error of
η is 12.5%. Fig. 4 shows the delay of gate circuits with the Fig. 5. OFF-current model (24) against a SPICE simulation of the 90-nm
minimum size transistors in the 90-nm mixed-signal process. mixed-signal process.
The near-threshold model is fit from 180 to 700 mV. (The
inverter does not work below 180 mV.) Equation (22) can be on the path, and t pd is the delay of each gate. Nl is the number
applied to various circuits by fitting (Cload /k f ). Table III shows of representative leaking gates in a cycle. Cdyn represents the
the delay of FO1, FO4, FO8, and NAND2 when VDD ≈ Vt . total switching capacitor.
E tot is the total energy dissipated in the CMOS circuit, Consider the DIBL effect, the OFF-current model is
which is the sum of the dynamic component and the leakage ηVDD −V t

component. The total energy is defined by the energy per cycle, IOFF = I0 e nϕt . (24)
that is, Fig. 5 shows the OFF-current of the nMOS transistor in
2 the 90-nm mixed-signal process. The values of the voltage
E tot = α E dyn + E leak = αCdyn VDD + Nl IOFF VDD t pd L d p . (23)
boundaries, n and Vt , are obtained based on Table III. η is
E dyn is the dynamic energy and E leak is the leakage energy. 0.072, and I0 = 0.51μA. The mean absolute error is 1.31%,
α is the switching activity factor. L d p is the number of gates and the maximum absolute error is 5.3%.
WANG et al.: COMPACT MODEL FOR DIGITAL CIRCUITS OPERATING NEAR THRESHOLD 2085

its feasibility in the simulation of the near-threshold circuits

in the deep-submicrometer region.

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