Address Latch Enable/Program Pulse: This pin is used to latch the low byte of the address of

external program/data memory. This pin is also the program pulse input (PROG) during EPROM
programming.

Program Store Enable: This pin is used to enable output buffer of external program memory.
This is the read strobe to external program memory.

External Access Enable/Programming Supply Voltage: EA must be externally held low to

enable the device to fetch code from external program memory locations 0000H to 0FFFH. If EA
is held high, the device executes from internal program memory unless the program counter
contains an address greater than the on-chip ROM/OTP. This pin also receives the 12.75 V
programming supply voltage (VPP) during EPROM programming.
Crystal 1: Input to the internal clock generator circuits

Crystal 2: Output from the inverting oscillator amplifier.

Oscillator and clock

The XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured
for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To
drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown
in Figure 2. There are no require-ments on the duty cycle of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.

The crystal oscillates at its series resonance frequency. The CMOS inverter is initially biased
into the middle of its operating region by the feedback resistor, R1. This ensures that the Q-point
of the inverter is in a region of high gain. Here a 1MΩ value resistor is used, but its value is not
critical as long as it is more than 1MΩ. An additional inverter is used to buffer the output from
the oscillator to the connected load.
The inverter provides 180o of phase shift and the crystal capacitor network the additional
180o required for oscillation. The advantage of the CMOS crystal oscillator is that it will always
automatically readjust itself to maintain this 360ophase shift for oscillation.

Reset Circuit: Reset means to execute from the beginning. The capacitor acts as a short-
circuit when DC is applied across it – that’s basic stuff. During charging, the RST pin is
connected to the 5V supply and hence in HIGH state – the microcontroller automatically resets
at start-up this way. Once the capacitor is fully charged, it acts as an open-circuitand the RST
pin is driven LOW through the attached resistor. The button, on the other hand, works exactly
the same way but manually. When pressed, it will SET the RST pin and microcontroller will
reset.

A reset is accomplished by holding the RST pin high for at least two machine cycles (24
oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin
must be high long enough to allow the oscillator time to start up (normally a few milliseconds)
plus two machine cycles.
RESET is an active High input When RESET is set to High, 8051 goes back to the
power on state.The 8051 is reset by holding the RST high for at least two machine cycles and
then returning it low.
There are two method of reset circuit:
1. Power On Reset.
 Initially charging of capacitor makes RST High
 When capacitor charges fully it blocks DC.
2. Manual Reset
 Closing the switch momentarily will make RST High.
Internal Data and Program memory organization:

Data Memory:

Internal data memory is 128 bytes. These locations are address from 0 to 7Fh and can be directly
and indirectly addressable. These 128 bytes of registers or RAM is divided in several blocks like
Register Bank0 to Register Bank3, Bit addressable register and General or user RAM and a stack
memory as shown in figure.

2) Special function registers:

The register in between memory location 80H to FFH are use as a SFR.
The unused locations are shown by blank and must not be used by 8051 programmer.

Program memory:

In 8051 Microcontroller, the code or instructions to be executed are stored in the Program
Memory, which is also called as the ROM of the Microcontroller. The 8051 has 4KB of internal
ROM and the address space is 0000H to 0FFFH. If the address space i.e. the program addresses
exceed this value, then the CPU will automatically fetch the code from the external Program
Memory.
Ports and Circuits:

All four ports in the 80C51 are bidirectional. Each consists of a latch (Special Function Register
P0 through P3), an output driver, and an input buffer.

Port 0:

The structure of Port 0 is shown in figure below.

Port-0 can be used as a normal bidirectional I/O port or it can be used for address/data
interfacing for accessing external memory. When control is '1', the port is used for address/data
interfacing. When the control is '0', the port can be used as a bidirectional I/O port.

When the port is used as an input port, ‘1’ is written to the latch. In this situation both the output
MOSFETs are ‘off’. Hence the output pin have floats and whatever data written on pin is directly
read by read pin.
Suppose we want to write 1 on pin of Port0, a 1 written to the latch which turns off the lower
MOSFET while due to 0 control signal upper MOS also turns off as shown in figure. In this case
we wants logic 1 on the pin but we getting floating value so to convert that floating value into
logic 1, we need to connect the pull up resistor parallel to upper MOS. This is the reason why we
needed to connect pullup resistor to port0.

If we want to write '0' on pin of port 0 , when '0' is written to the latch, the pin is pulled down by
the lower FET. Hence the output becomes zero.

When the control is '1', address/data bus controls the output driver FETs. If the address/data bus
(internal) is '0', the upper FET is 'off' and the lower FET is 'on'. The output becomes '0'. If the
address/data bus is '1', the upper FET is 'on' and the lower FET is 'off'. Hence the output is '1'.
Hence for normal address/data interfacing (for external memory access) no pull-up resistors are
required.

PORT 1:
The structure of a port-1 pin is shown in fig below. It has 8 pins (P1.1-P1.7) . Port-1 dedicated
only for I/O interfacing. When used as output port, not needed to connect additional pull-up
resistor like port 0. It have provided internally pull-up resistor as shown in fig. below. The pin is
pulled up or down through internal pull-up when we want to initialize as an output port. To use
port-1 as input port, '1' has to be written to the latch. In this input mode when '1' is written to the
pin by the external device then it read fine. But when '0' is written to the pin by the external
device then the external source must sink current due to internal pull-up. If the external device is
not able to sink the current the pin voltage may rise, leading to a possible wrong reading.
PORT 2:
The structure of a port-2 pin is shown in fig. below. It has 8-pins (P2.0-P2.7) .

Port-2 we use for higher external address byte or a normal input/output port. The I/O operation is
similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory
access. Here again due to internal pull-up there is limited current driving capability.

PORT 3:
Port-3 (P3.0-P3.7) having alternate functions to each pin,The internal structure of a port-3 pin is
shown in fig below.
Following are the alternate functions of port 3:

It work as an IO port same like Port 2. only alternate function of port 3 makes its architecture
different than other ports.

External Memory:
External Program Memory Interface:
External Program Memory is accessed under two conditions:
1. Whenever signal EA is active
2. Whenever the program counter (PC) contains a number that is larger than the memory size.

Three pins namely the EAbar, ALE and PSENbar are the additional pins apart from address and
data pins to interface external program memory.
o EAbar (External Access) should connect to ground to access external program memory
from address 0000H to FFFFH.
o ALE (Address Latch Enable) is used to distinguish the content as address or data at the
input of latches.
 o PSENbar is used to enable output buffer of ROM during instruction fetch operation. So
this pin can used as read pin for program memory.
o Port 0 (Lower Address and Data lines) and Port 2 (Higher Address lines) are works as
the Address bus and Data bus to interface external program memory.

Write Enable
Output Enable
Output Enalbe

External Data Memory Interface:

External Program Memory can accessed using MOVX instruction. In this instruction the pointer
register must be DPTR.

Two pins namely the Wrbar and Rdbar are the additional two pins apart from address and data
pins to interface external data memory.

o Rdbar is used to enable output buffer of external data memory during data read
operation.
o Wrbar is used to enable input buffer of external data memory, So this pin can used as
read pin for program memory.
Timers and Counters:
The two 16-bit Timer/Counter registers can be configured to operate either as timers or event
counters.
In the ‘Timer’ function, the register is incremented at every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1.

The ‘Timer’ or ‘Counter’ function can select using control bits C/T of TMOD Register.

These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0)
in TMOD.

Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different.
 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter
with a fixed divide-by-32 prescaler. Figure 7 shows Mode 0 operation. In this mode, the Timer
register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the
Timer interrupt flag TFn. The count input is enabled to the Timer when TRn = 1 and either
GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to be controlled by external input
INTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function
Register TCON (Figure 6). The GATE bit is in the TMOD register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of
TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the
registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 7). There are two different
GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

7.3.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are
used. See Figure 8.
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown
in Figure 9. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of
THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is
the same for Timer 0 and Timer 1.

Mode 3
When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting TR1 =
0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for
Mode 3 and Timer 0 is shown in Figure 10. TL0 uses the Timer 0 control bits: T0C/T, T0GATE,
TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes
over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the ‘Timer 1’ interrupt.
Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3,
the P89V51RD2 can look like it has an additional Timer.
Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out
of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any
application not requiring an interrupt.