Metal oxide semiconductor field effect transistors (MOSFETs)

A newer form of transistor which has pretty much replaced BJT

technology for all digital applications and much of analog.

Basically, an FET is a resistor whose resistance can be controlled

through a third terminal. So the transistor mechanism is much different
than that of the BJT. A BJT used both electrons and holes injected
across the junctions (hence bipolar). An FET uses either electrons or
holes (hence unipolar) flowing by drift current between two contacts
(source and drain). The amount of flow is controlled by a voltage
applied at the gate.

electron-current device: n-channel MOSFET (NMOS)

hole-current device: p-channel MOSFET (PMOS)

Using NMOS and PMOS together (known as CMOS) offers some

significant advantages in circuit design.

EE 230 MOSFETs – 1
 Basic NMOS structure
(n-channel device)

e
gat e
d
Start with a p-type substrate. oxi

in
dra

Form two n-type regions rce

s ou
(source & drain)

Form a thin layer of silicon Put metal contacts on the

dioxide on the p-type silicon source, drain, and oxide (gate)
between source and drain for electrical connection

PMOS has n- and p-type regions reversed. (Duh!)

EE 230 MOSFETs – 2
 Basic NMOS structure
(n-channel device)
n-type source
p-type substrate. & drain

in
dra

rc e
sou

gate oxide
e
de gat e
i d
o x oxi

ra in ain
d dr

rce e
s o u ou rc
s
metal contacts
EE 230 MOSFETs – 3
Critical dimensions

oxide thickness: typical 1 - 10 nm.

oxide thickness (tox)

e
gat e
d
oxi

in
dra
(L )
g t h
len
wid
th (
W)
o u rce gate length (distance from source
s
to drain) – as small as 20 nm.
width: typical L to 10 L
(W/L ratio is important)

EE 230 MOSFETs – 4
 Will current flow?
Apply a voltage between drain and source (VDS).
VDS

+
–
gate

n n
source drain
p

If VDS > 0, the diode at the drain end will be reverse-biased, preventing
current flow.

Reversing the polarity doesn’t help, because then the other junction
will be reverse biased.

EE 230 MOSFETs – 5
 The MOS capacitor
The secret to MOSFET operation lies in the MOS capacitor (the central
part of the FET).

gate
body

substrate (body)

The structure is essentially a little parallel-plate capacitor formed by the

gate metal and the semiconductor with the oxide as the dielectric.

= εox = 3.9εo = 3.9(8.85x10–12 F/m)

for tox = 10 nm (10–8 m)
Define oxide
=
capacitance Cox = 0.00345 F/m2

units: F/m2 (or F/µm2) = 3.45x10–15 F/µm2

EE 230 MOSFETs – 6
 gate
body

P-type semiconductor – + +
+ + + –+ + +
the carriers are mostly – +
+ + + + –
holes, but there are few – +
electron lurking around. + –
+ + + + +

vGB < 0

+
–
gate
body
Try applying a negative voltage
between the gate and the body: –– – + + + ++ + + ++ +
Holes are attracted to the gate – – + +
+ + + + + + +
region and electrons are +
pushed away from the negative
voltage. substrate (body)

Hole concentration under the gate is enhanced. So negative voltage

causes holes to “accumulate”. Probably not helpful for our NMOS.
EE 230 MOSFETs – 7
 vGB > 0

+
–
gate
body
So try applying a positive
voltage to the gate. Now the + + – – – – –
+
holes are pushed away and the + + + +
+ + + +
electrons are attracted. + + + + + + + + +
substrate (body)

The region under the gate becomes “depleted” of holes. So this is

probably not helpful either, but the movement of the electrons towards
the gate looks promising.

EE 230 MOSFETs – 8
 vGB > VT

+
–
gate
body
So try increasing the gate
voltage further. Holes are + – – – – – – – – – – – –
+ – – – – – – – – – – – –
pushed away further and more +
and more electrons are pulled + + + +
+ + + + ++ +
in. + + + + ++
substrate (body)

At a sufficiently high voltage, enough electrons will gather together to

make the region under the gate “invert” and behave like it was n-
type!

The gate voltage required create the electron “inversion layer” is called
the threshold voltage, VT. If the voltage is increase beyond VT, even
more electrons are gathered together under the gate.

EE 230 MOSFETs – 9
 The inversion layer vOV = vGB – VT
gate
How many electrons are in the
inversion layer? The definition of
– – – – – – – – – – – –
the threshold voltage says that when – – – – – – – – – – – – –
vGB = VT, the electron concentration
in the inversion layer is equal to the
hole concentration in the substrate:
substrate (body)
n(inversion) = p(substrate).
This gives just enough electrons so that the region under the gate begins
to act like it is n-type. A detailed physical description is beyond our
capabilities now. (See EE 332 and beyond.) But we can get a good
approximation by using the fact that the MOS structure is basically a
capacitor. Once the gate voltage is bigger than the threshold, electrons
pile up under gate just like charge on a plate of a capacitor.

Qinv = Cgate (vGB

<latexit sha1_base64="tljb/ognnYJjHerF0SeDwCOlRtA=">AAAClnicbVFdaxNBFJ2sXzV+NNUXwZfFIKZQw64I9qFKsUp88CGFJikkYbk7ubsZMjuzzNwNDcv+BH+Nr/pD/DfOphGa1AsDh3Pux5x741wKS0Hwp+HduXvv/oO9h81Hj5883W8dPBtaXRiOA66lNpcxWJRC4YAESbzMDUIWSxzFi7NaHy3RWKHVBa1ynGaQKpEIDuSoqPXmPCqFWlYfz6IyBcJqIjGhzjIqe5+rt8PoYmJEOqfDqNUOusE6/Nsg3IA220Q/OmiMJjPNiwwVcQnWjsMgp2kJhgSXWDUnhcUc+AJSHDuoIEM7LdeOKv+1Y2Z+oo17ivw1e7OihMzaVRa7zAxobne1mvyfNi4oOZ46x3lBqPj1oKSQPmm/Xo8/EwY5yZUDwI1wf/X5HAxwckvcmrLunSPfclJeFUpwPcMdVtIVGXCkRcpAqNpV2QfprqD0P9r1q/nOF5EKskffa/GoZxAXhzdym+4U4e7ib4Phu24YdMPz9+3Tk81R9thL9op1WMg+sFP2jfXZgHH2g/1kv9hv74X3yfvq9a5Tvcam5jnbCq//F3x9zkE=</latexit>
VT )

= ( )= where ns is the sheet concentration

of electrons in the inversion layer.
EE 230 (electrons per unit area). MOSFETs – 10
 vOV = vGB – VT
The threshold voltage gate
The threshold voltage for a MOSFET
depends primarily on two things. The – – – – – – – – – – – –
– – – – – – – – – – – – –
doping level of the substrate and the
thickness of the insulating gate oxide
layer.
substrate (body)
The definition of threshold is that the electron concentration under the
gate is equal to the hole concentration in the rest of the substrate. If
the hole concentration in the substrate is higher (due to higher doping)
more voltage is required to induce the higher number of electrons
needed for inversion. Increased doping means higher threshold.
The electric field in MOS capacitor in the gate that controls what is
happening in the inversion layer. Since E ∝ vGB/tox , making the oxide
thicker requires more voltage in order to create the same electric field.
So a thicker oxide also leads to higher a threshold voltage.
Integrated circuit fabrication engineers work very hard to control the
threshold voltages of the MOSFETs. Not easy when there are millions
EE 230 (or billions) of transistors in a chip! MOSFETs – 11
 Summary of MOS capacitor operation
So through the application of the gate voltage, we control carriers under
the gate.

vGB < 0 hole accumulation

0 < vGB < VT carrier depletion

inversion –
vGB > VT electron layer forms,
qns = Cox(vGB – VT)

EE 230 MOSFETs – 12
 Now we see a mechanism by which we might get current to flow
between drain and source.
Apply a gate voltage to create an electron inversion layer. Then
electrons from the source can flow to the drain using the inversion
layer as a channel.

+
–
vGS > VT
gate

body n n
electron inversion layer
source drain

For now, we connect the source to the body (call this ground) and
apply the controlling voltage between the gate and the source. This is
OK for the time being, but we will have to revisit the issue of the body
connection later. With the drain also at ground, the inversion layer
(channel) is uniform between source and drain.
EE 230 MOSFETs – 13
 Drain resistance
With the inversion layer in place, we can apply a positive voltage
between the drain and source. This creates an electric field along the
channel that will push electrons from the source through the inversion
layer to the drain. The moving electrons represent a current in the
opposite direction — from drain to source.
vDS > 0

+
–
+
–
vGS > VT
gate

body n n
electron inversion layer
source electrons drain
iD
p

EE 230 MOSFETs – 14
 At first inspection, the current is
essentially that of a resistor — vDS > 0
increasing the drain voltage will

+
–
increase the current. So we
need to find the resistance
between the drain and source,

+
–
RDS. vGS > VT
gate

body n n
electron inversion layer
source electrons drain
iD
p

The total resistance is the sum the resistances of the three regions: RDS =
Rsource + Rinversion + Rdrain. Usually, the source and drain are very heavily
doped (lots of electrons) and so the resistances in those regions are very
small. Most of the resistance is associated with the inversion layer so
that RDS ≈ Rinversion.
EE 230 MOSFETs – 15
 Using the basic definition for a resistor:
L ρ L 1
RDS =ρ = ρinv =
A tinv W <latexit sha1_base64="he2Rydzc+dLSjFEwdrs9TCz77Uk=">AAACknicbZFbaxNBFMcnWy813trqmy+DQahQwq4UKqJQqaAPfYhgmkI2hLOTs8mQuawzZ0vDsh/AT+OrfhS/jbNJhCb1wMCf37nNOScrlPQUx39a0c6du/fu7z5oP3z0+MnTvf2DC29LJ7AvrLLuMgOPShrskySFl4VD0JnCQTY/a/yDK3ReWvONFgWONEyNzKUACmi810ndzI4raa7qD2nuQFRJXX1PdTk23Kx4HaLibrw0flska9Fha+uN91uDdGJFqdGQUOD9MIkLGlXgSAqFdTstPRYg5jDFYZAGNPpRtZym5q8CmfDcuvAM8SW9mVGB9n6hsxCpgWZ+29fA//mGJeVvR2GkoiQ0YtUoLxUny5vV8Il0KEgtggDhZPgrFzMIO6GwwI0uy9oFio1JquvSSGEnuEUVXZODAD2SBmmaqaoeqHABY//hUK/hh5/kVJI/Om+cR58d4vz1jdh2OEWyvfjb4uJNN4m7ydfjzun79VF22Qv2kh2yhJ2wU/aF9VifCfaD/WS/2O/oefQu+hidrUKj1jrnGduw6PwvtQbNmw==</latexit>
qμn ninv
<latexit sha1_base64="Qr9gJULamNXjBygvzLFFwN+l2Gk=">AAACv3icbZFRa9swEMcVt127bN3S7nEvpmGQQgn2GKwPG7SssD30IVuXphAHIytnR0SWjHQuDcJfa99l0Nfuc0xOUkjSHhj++v3vJN9dUghuMAj+Nryt7Z0Xu3svm69e77952zo4vDaq1Az6TAmlbxJqQHAJfeQo4KbQQPNEwCCZfqv9wS1ow5X8jbMCRjnNJE85o+hQ3Or9iu3FVfU10hMVpZoye1nZc3cWkGJnQWqvshhbLm+rKtI8m+DxaoIrGTzyuNUOusE8/KciXIo2WUYvPmgMorFiZQ4SmaDGDMOgwJGlGjkTUDWj0kBB2ZRmMHRS0hzMyM5br/wPjoz9VGn3SfTndLXC0tyYWZ64zJzixGx6NXzOG5aYno5cx0WJINniobQUPiq/nqM/5hoYipkTlGnu/tVnE+qmgW7aa6/M7y6ArXVi70rJmRrDBhV4h5o6aABzymXdle1R4dYl1SN299W8c8EzjubksjZPvmuA6fFKbtOtItwc/FNx/bEbBt3w56f22ZflUvbIe3JEOiQkn8kZ+UF6pE8Y+UPuyQP55517mSe9YpHqNZY178haeLP/sgrguA==</latexit>

where ninv is the electron concentration (m–3) in the inversion layer, tinv
is the “thickness” of the inversion layer, µn is the electron mobility, q is
the charge on one electron and L and W are the gate length and width.

= =

The electron concentration and inversion layer thickness are difficult to

quantify because of the sheet-like nature of the inversion layer.
However, the product ninv· tinv can be re-expressed more easily – it
represents the “sheet concentration” (m–2) of electrons in the inversion
layer, which we denote as ns.

We saw earlier that: = ( )

EE 230 MOSFETs – 16
 Using the basic definition for a resistor:
L ρinv L 1
RDS = ρinv = ρinv =
A tinv W <latexit sha1_base64="he2Rydzc+dLSjFEwdrs9TCz77Uk=">AAACknicbZFbaxNBFMcnWy813trqmy+DQahQwq4UKqJQqaAPfYhgmkI2hLOTs8mQuawzZ0vDsh/AT+OrfhS/jbNJhCb1wMCf37nNOScrlPQUx39a0c6du/fu7z5oP3z0+MnTvf2DC29LJ7AvrLLuMgOPShrskySFl4VD0JnCQTY/a/yDK3ReWvONFgWONEyNzKUACmi810ndzI4raa7qD2nuQFRJXX1PdTk23Kx4HaLibrw0flska9Fha+uN91uDdGJFqdGQUOD9MIkLGlXgSAqFdTstPRYg5jDFYZAGNPpRtZym5q8CmfDcuvAM8SW9mVGB9n6hsxCpgWZ+29fA//mGJeVvR2GkoiQ0YtUoLxUny5vV8Il0KEgtggDhZPgrFzMIO6GwwI0uy9oFio1JquvSSGEnuEUVXZODAD2SBmmaqaoeqHABY//hUK/hh5/kVJI/Om+cR58d4vz1jdh2OEWyvfjb4uJNN4m7ydfjzun79VF22Qv2kh2yhJ2wU/aF9VifCfaD/WS/2O/oefQu+hidrUKj1jrnGduw6PwvtQbNmw==</latexit>
qμn ninv
<latexit sha1_base64="cVy5nXE7x7CFBndu37s72msvbKM=">AAACy3icbZHfahNBFMYna9Ua/6V66c3SIKRQwq4IeqFQsaAXLaRqmkI2LLOTs8mQ2Zll5mxpHPfSF/MtfIPetk/Q2WSLSeqBgY/f+c7MnHOSXHCDQfC34d3buv/g4faj5uMnT589b+28ODWq0Az6TAmlzxJqQHAJfeQo4CzXQLNEwCCZfa7yg3PQhiv5A+c5jDI6kTzljKJDcSv6FtvD7+XHSE9VbLk8L6NUU2aPSvvJUQEpdpbkn6O0WItI88kU91ZtrnBwy+NWO+gGi/DvirAWbVJHL95pDKKxYkUGEpmgxgzDIMeRpRo5E1A2o8JATtmMTmDopKQZmJFdjKH0Xzsy9lOl3ZHoL+hqhaWZMfMscc6M4tRs5ir4v9ywwPT9yHWcFwiSLR9KC+Gj8quZ+mOugaGYO0GZ5u6vPptSNw10k197ZXF3DmytE3tRSM7UGDaowAvU1EEDmFEuq65sjwq3Oqlusbuv4p1DPuFo9o+q5P4XDTDbW/E23SrCzcHfFadvumHQDU/etg8+1EvZJq/ILumQkLwjB+Qr6ZE+YeQPuSRX5No79oz30/u1tHqNuuYlWQvv9w30auZ4</latexit>

where ninv is the electron concentration (m–3) in the inversion layer, tinv is
the “thickness” of the inversion layer, µn is the electron mobility, q is the
charge on one electron and L and W are the gate length and width. (See
slide 4 for a reminder of the 3D geometry.) Putting the equations
together:
1 L
RDS =
<latexit sha1_base64="SEVcpFaCqb+3+rKYrFphwc/eeDU=">AAACu3icbZFLaxsxEMflTR+p+3KaYy+ipuBAMLuh0B4aCDSQHnxwH44DXrNo5VlbtaTdSrMhRuyXyqdpj+0nqdZ2wHY6IPTnNw9pZtJCCoth+LsR7D14+Ojx/pPm02fPX7xsHby6tHlpOAx4LnNzlTILUmgYoEAJV4UBplIJw3T+qfYPr8FYkevvuChgrNhUi0xwhh4lrd7XxJ1/q05jCRl24sww7qLK/YxVSRNNdeKEvq5wdVWxEdMZHm0G9yo3vONJqx12w6XR+yJaizZZWz85aAzjSc5LBRq5ZNaOorDAsWMGBZdQNePSQsH4nE1h5KVmCuzYLduu6FtPJjTLjT8a6ZJuZjimrF2o1EcqhjO766vh/3yjErMPY99xUSJovnooKyXFnNYzpBNhgKNceMG4Ef6vlM+Ynwb6SW+9sqxdAN/qxN2UWvB8AjtU4g0a5qEFVEzouivXZ9KvSud32NereedcTAXa417tPL4wAPOjjdimX0W0O/j74vKkG4Xd6Mu79tnH9VL2yWvyhnRIRN6TM/KZ9MmAcHJLfpE/5G9wGvDgRyBXoUFjnXNItiwo/wF7rt6T</latexit>
qμn ninv tinv W

= =

The electron concentration and inversion layer thickness are difficult to

quantify because of the sheet-like nature of the inversion layer.
However, the product ninv· tinv can be re-expressed more easily – it
represents the “sheet concentration” (m–2) of electrons in the inversion
layer, which we denoted earlier as ns.
EE 230 MOSFETs – 17
 W
iD = qμn ns vDS
<latexit sha1_base64="AHGVFaeSs5MBeAk8VVfl7F8bLTc=">AAACqHicbVFba9swFFa8W5fd0u1xL2JhkI4S7FHoBhsUFtge+pCxpe6IjZGV40REkj3puDQY/5b9mr22z/s3k50MmnQHhD5956bznbSQwqLv/+l4d+7eu/9g72H30eMnT5/19p+f2bw0HCY8l7k5T5kFKTRMUKCE88IAU6mEMF1+avzhBRgrcv0dVwXEis21yARn6Kik914ko4+RhAynPyNVJprqxLbvQZQZxquwrk7ryIj5Ag/WV3yRVKNvddLr+0O/NXobBBvQJxsbJ/udMJrlvFSgkUtm7TTwC4wrZlBwCXU3Ki0UjC/ZHKYOaqbAxlU7Y01fO2ZGs9y4o5G27M2MiilrVyp1kYrhwu76GvJ/vmmJ2bu4ErooETRfN8pKSTGnjWB0JgxwlCsHGDfC/ZXyBXPSoJN1q0tbuwC+NUl1WWrB8xnssBIv0TBHWkDFhG6mqsZMur3o/B/t6jX8YCTmAu3haeM8/GwAlgc3YrtuFcGu8LfB2dth4A+Dr0f9kw+bpeyRl+QVGZCAHJMT8oWMyYRw8ov8Jlfk2nvjjb3Q+7EO9TqbnBdky7z0L1qP1kk=</latexit>
L

We saw earlier that: = ( )

1
= ( ) RDS =
<latexit sha1_base64="ZwLqi1xD6Zhu7ewanbYZ1k+9WP0=">AAACvHicbZFda9swFIYV76vLvtLtcjdmYZBCF+wx2C62UWihu+ggW5ukEAcjy8eJiCQb6TgkCP+q/Zrebn9kcuJBk+6A4OV5j450zkkKwQ0GwU3Lu3f/wcNHB4/bT54+e/6ic/hyZPJSMxiyXOT6OqEGBFcwRI4CrgsNVCYCxsnitPbHS9CG5+oK1wVMJZ0pnnFG0aG48/1nbM8uqy9RpimzYWUjARn2Iln6sfJPY5uvqq03ruxFFWk+m+PRNmkZ2/PL6t0ovmpwFXe6QT/YhH9XhI3okiYG8WFrHKU5KyUoZIIaMwmDAqeWauRMQNWOSgMFZQs6g4mTikowU7vpu/LfOpL6Wa7dUehv6O0blkpj1jJxmZLi3Ox7NfyfNykx+zS1XBUlgmLbh7JS+Jj79RD9lGtgKNZOUKa5+6vP5tRNCd2od17Z1C6A7XRiV6XiLE9hjwpcoaYOGkBJuaq7sgMq3K5U/g+7ejXvnfEZR3N8UZvH5xpgcXQrt+1WEe4P/q4Yve+HQT/88aF78rlZygF5Td6QHgnJR3JCvpEBGRJGfpEb8pv88b56qbfw5DbVazV3XpGd8JZ/Aas73iA=</latexit>
μn Cox W
L (vGS VT )

µnCoxW/L = 0.5 mA/V2 and vGS–VT = 4 V.

1.0

0.8
drain current — iDS (mA)

0.6

0.4

0.2

0.0
0.0 0.1 0.2 0.3 0.4 0.5
drain voltage — vDS (V)
EE 230 MOSFETs – 18
 But the most important observation is that the channel resistance
depends on the gate voltage! As the gate voltage is increased (which
increases the electron sheet concentration in inversion layer), the
channel resistance decreases. This a variable resistor. (But not anything
like a potentiometer.)
µnCoxW/L = 0.5 mA/V2 and VT = 1 V.
1.0
vGS = 5 V

For vGS < VT, there is

drain current — iDS (mA)

0.8
no inversion layer: vGS = 4 V
RDS → ∞ and iD = 0 0.6
(blue curve).
vGS = 3 V
For vGS ≥ VT, the 0.4
resistance decreases
(slope increases) as 0.2
vGS = 2 V

vGS increases.
vGS < VT
0.0
0.0 0.1 0.2 0.3 0.4 0.5

drain voltage — vDS (V)

EE 230 MOSFETs – 19
 Drain resistance
However, the picture gets more complicated as vDS increases.
vG
gate vD
vS (=0) + +
vGS vGD
n – – n

source – vDS + drain

The electron sheet concentration depends on the local voltage of the

semiconductor underneath the gate. In the MOS capacitor, the voltage
of the semiconductor was the same everywhere, so the electron
concentration was uniform. In the case of the MOSFET, the local voltage
under the gate can vary from one end to the other. At the source end, the
channel voltage is 0, (because we have tied the source to ground). At
the drain end, the channel voltage is vD, because we have applied a
voltage there in order to make current flow. In between, the channel
voltage ranges between 0 and vD.
EE 230 MOSFETs – 20
 vG
gate vD
vS (=0) + +
vGS vGD
n – – n

source drain

The electron sheet concentration is determined by the difference

between the gate voltage and the local channel voltage. At the source
end, qns = Cox(vGS – VT). At the drain end, qns = Cox(vGD – VT).
Since vGD = vGS – vDS, then qns = Cox(vGS – vDS – VT) at the drain end.
Increasing vDS decreases vGD and so decreases the electron
concentration at the drain end, increasing the incremental resistance at
the drain end.

The result of all this is that the inversion layer (channel) resistance is
actually non-linear – the resistance changes as the drain voltage changes.
EE 230 MOSFETs – 21
 VGS > VT
VDS > 0

VGS VGD
gate

n n

source drain
electron concentration decreases
at drain end

The non-uniform electron concentration along the channel implies that

the channel resistance is not uniform — it is greater at the drain end,
where there are fewer electrons.

So, the drain voltage increases, the channel resistance increases. The
effect is that the I-V curve bends over.

EE 230 MOSFETs – 22
 So a more correct analysis of the current flow shows that the iD-vDS
relationship is not linear, but parabolic. (See EE 332.)

= ( )

Exercise: Show that this reduces to the linear equation for small values of
vDS.
µnCoxW/L = 0.5 mA/V2 and vGS–VT = 4 V.
4.0

3.0
drain current — iDS (mA)

2.0

1.0

0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
EE 230 drain voltage — vDS (V) MOSFETs – 23
 This mode of operation is known as "linear" or "ohmic". (Some old
codgers also call is "triode" — but don't use that.)

= ( )

Notation: To save on ink and time, define the constant in front as:

The units of this “MOS current parameter” are A/V2. Or more

typically mA/V2. (Check it.)

Note: This use of K is not standard. Different textbooks will handle the
current parameter differently.

EE 230 MOSFETs – 24
 current saturation
VGS > VT
VDS > 0

Now take the final step: If VGS VGD < VT

gate
vDS is increased sufficiently,
we reach a point where vGD
n n
< VT. The electron
source drain
concentration should electron layer is "pinched down"
disappear at the drain end!

The usual terminology is to say that the channel is “pinched off” at the
drain end, but this is slightly misleading. If the channel were truly
pinched off, then the electron concentration would go to zero there
and the current would necessarily have to go to zero, also.
Instead, it might be better to say that the channel is “pinched down”.
The electron concentration goes to some minimum value, but never
really shuts off. In effect, the flowing current works to hold the
channel open, even though the drain voltage seems high enough to
truly pinch off the channel.
EE 230 MOSFETs – 25
 The mathematical analysis of what happens in a FET at pinch-off is a
fairly complicated problem in electromagnetics – definitely beyond
our current capabilities. (Again, see EE 332.)
However, the end result on the device behavior is easy to grasp – the
current saturates at the pinch down value. For higher values of vDS, the
current stays constant at a constant value.

The condition for the NMOS going reaching the “pinch-down”

condition is vGD ≤ VT. This can be re-expressed in terms of vDS and vGS.

To determine the saturation current, we can insert the pinch-down

condition given above into the iD-vDS equation from the ohmic region
of operation. Then the saturated current is

( )= [ ] = [ ]

(Work out these details for yourself.)

EE 230 MOSFETs – 26
 NMOS iD-vDS curves
1.3

drain current — iDS (mA)

1.0

Fix vGS and vary vDS. 0.8

Plot the drain current.
0.5

0.3

0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
drain voltage — vDS (V)

For small vDS (vDS < vGS - VT), the NMOS will be in the ohmic region.
At higher vDS (vDS ≥ vGS - VT), the channel pinches down and the
current saturates.
If vGS < VT, there is no inversion layer and the NMOS is off (iD = 0).
EE 230 MOSFETs – 27
 NMOS iD-vDS curves
A set of characteristic curves for an NMOS with VT = 1 V and

1 W 1 mA 10 μm mA
Kn = μn Cox = 0.05 2 = 0.25 2
2 L 2
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V 1 μm V

5.0

vGS = 5 V
4.0
drain current — iDS (mA)

3.0
vGS = 4 V
2.0

vGS = 3 V
1.0
vGS = 2 V
0.0 vGS < VT
0.0 2.0 4.0 6.0 8.0 10.0
drain voltage — vDS (V)

EE 230 MOSFETs – 28
 Another useful plot is iD vs. vGS, with vDS fixed. If vDS is kept large so
that the NMOS does not go into the ohmic region, the curve is
essentially a plot of the saturation equation.

5 2.5

4 2

(mA)
3 1.5
I (mA)

NMOS in
saturation

1/2
D

(I )
2 NMOS in 1

D
saturation 1/2
K
V
T
1 0.5

NMOS off NMOS off

0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6

V (V) V (V)
GS GS

In a slight modification, we can plot iD1/2= K1/2(vGS - VT). From this

graph, we can immediately pick out the two important NMOS
parameters: VT and K.

EE 230 MOSFETs – 29
Summary of NMOS equations
VT, =

vGS < VT off iD = 0

vGS ≥ VT on vDS < vGS – VT ohmic or linear

= ( )

vDS ≥ vGS – VT saturation

= [ ]

iG = 0 !! (at least at DC)

The equations are exact (within the limits of the simplest MOSFET
model). The quadratic dependence of current on voltage means that
the circuit analysis will be non-linear and we will have frequent need
for the quadratic equation.
EE 230 MOSFETs – 30
 The NMOS substrate (body)
In applying the drain voltage to make the drain current flow, is it necessary to use
positive value for vDS? It would seem that vDS < 0 might be OK. However, it's not.
vGS > VT vDS
gate

n n
electron inversion layer
source drain
p-type body

To see why, consider the p-n junctions formed by the drain and source with the
substrate.

If the substrate is at ground potential and we apply a negative voltage to the drain,
the p-n junction there would be forward-biased – probably with a very large voltage
possibly without a limiting resistor – and a huge forward-bias diode current would
flow from the substrate into the drain. The junction would likely be burned out.

The NMOS substrate rule: The NMOS substrate (body) should be connected to the
lowest voltage in the circuit – usually the ground. (Although it could be a negative
power supply.) Then the source and drain will both always be at the same or higher
voltages, and it will be impossible to forward-bias the diodes.
EE 230 MOSFETs – 31