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Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY • Ultra Low Gate Charge
VDS (V) 500 • Reduced Gate Drive Requirement Available
ORDERING INFORMATION
Package TO-220AB
IRF840LCPbF
Lead (Pb)-free
SiHF840LC-E3
IRF840LC
SnPb
SiHF840LC
THERMAL RESISTANCE
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 62
Case-to-Sink, Flat, Greased Surface RthCS 0.50 - °C/W
Maximum Junction-to-Case (Drain) RthJC - 1.0
VGS
Top 15 V
101 10 V
8.0 V 101
7.0 V
6.0 V 150 °C
5.5 V
5.0 V
Bottom 4.5 V 25 °C
100
100
4.5 V
91067_01 VDS, Drain-to-Source Voltage (V) 91067_03 VGS, Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics, TC = 25 °C RDS(on), Drain-to-Source On Resistance Fig. 3 - Typical Transfer Characteristics
3.0
VGS ID = 8.0 A
101 Top 15 V VGS = 10 V
10 V 2.5
8.0 V
ID, Drain Current (A)
7.0 V
2.0
(Normalized)
6.0 V
5.5 V 4.5 V
1.0
0.5
10-1 20 µs Pulse Width
TC = 150 °C
0.0
10-1 100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
91067_02 VDS, Drain-to-Source Voltage (V) 91067_04 TJ, Junction Temperature (°C)
Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature
2400
VGS = 0 V, f = 1 MHz
1600 101
Ciss
1200
800 Coss 25 °C
400 Crss
100 VGS = 0 V
0
100 101 0.6 0.8 1.0 1.2 1.4 1.6
91067_05 VDS, Drain-to-Source Voltage (V) 91067_07 VSD, Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage
20 103
ID = 8.0 A Operation in this area limited
5
VGS, Gate-to-Source Voltage (V)
by RDS(on)
VDS = 400 V 2
16
ID, Drain Current (A)
102
VDS = 250 V
5
12 VDS = 100 V
2 10 µs
10
100 µs
5
8
2 1 ms
1
4 10 ms
5 TC = 25 °C
For test circuit 2
TJ = 150 °C
see figure 13 Single Pulse
0 0.1
2 5 2 5 2 5
0 8 16 24 32 40 48 1 10 102 103
91067_06 QG, Total Gate Charge (nC) 91067_08 VDS, Drain-to-Source Voltage (V)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area
RD
VDS
VGS
8.0 D.U.T.
RG
+
- VDD
ID, Drain Current (A)
6.0 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
4.0
Fig. 10a - Switching Time Test Circuit
2.0
VDS
90 %
0.0
25 50 75 100 125 150
Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms
10
Thermal Response (ZthJC)
1
D = 0.5
PDM
0.2
0.1 0.1 t1
0.05 t2
0.02 Notes:
0.01 Single Pulse 1. Duty Factor, D = t1/t2
(Thermal Response) 2. Peak Tj = PDM x ZthJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1 10
L
VDS VDS
Vary tp to obtain
tp
required IAS
VDD
RG D.U.T. +
V DD
- VDS
IAS
10 V
tp 0.01 Ω
IAS
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
1200
ID
EAS, Single Pulse Energy (mJ)
Top 3.6 A
1000 5.1 A
Bottom 8.0 A
800
600
400
200
VDD = 50 V
0
25 50 75 100 125 150
Current regulator
Same type as D.U.T.
QG 50 kΩ
10 V 12 V 0.2 µF
0.3 µF
QGS QGD +
VDS
D.U.T. -
VG
VGS
3 mA
Charge
IG ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
- +
-
Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test
VGS = 10 Va
Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
Ripple ≤ 5 % ISD
Note
a. VGS = 5 V for logic level devices
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91067.
DWG: 5471
Notes
* M = 1.32 mm to 1.62 mm (dimension including protrusion)
Heatsink hole for HVM
• Xi’an and Mingxin actual photo
C
b
e
J(1)
e(1)
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