Fin Field Effect Transistor

The term “FinFET”, also known as Fin Field Effect Transistor, describes a non-planar,
double gate transistor built on an SOI substrate, based on the single gate transistor design.
These devices have been given the generic name "FinFET" because the source/drain region
forms fins on the silicon surface.
The important characteristics of FinFET are that the conducting channel is wrapped by a thin
Si “fin”, which forms the body of the device. The thickness of the fin determines the effective
channel length of the device. It is the basis for modern nanoelectronic semiconductor device
fabrication.

Figure 01: FinFET Device Schematic

History of FinFET
FinFET is a transistor design first developed by Chenming Hu and his colleagues at the
University of California at Berkeley, which tries to overcome the worst types of SCE (short
channel effect). Originally, FinFET was developed for use on Silicon-On-Insulator (SOI).
SOI FIinFET with thick oxide on top of fin are called “Double-Gate” and those with thin
oxide on top as well as on sides are called “Triple Gate” FinFETs.

Reason for evolution of FinFET

Researchers are making progress in developing new types of transistors, called finFETs,
which use a fin like structure instead of the conventional flat design, possibly enabling
engineers to create faster and more compact circuits and computer chips.

The fins are made not of silicon, but from a material called indium-gallium arsenide. In
addition to making smaller transistors possible, finFETs also might conduct electrons at least
five times faster than conventional silicon transistors, called MOSFETs, or metaloxide-
semiconductor field-effect transistors.
For the double gate SOI MOSFETs, the gates control the energy barrier b/w source and drain
effectively. Therefore, the Short Channel Effect (SCE) can be suppressed without increasing
the channel impurity concentration.

Layout and Mode of Operation

The basic electrical layout and mode of operation of a FINFET does not differ from a
traditional FET. There is one source and one drain contact as well as a gate to control the
current flow.

In contrast to planar MOSFETs the channel between source and drain is build as a three
dimensional bar on top of the silicon substrate, called fin. The gate electrode is then wrapped
around the channel, so that there can be formed several gate electrodes on each side which leads
to reduced leakage effects and an enhanced drive current.

Construction of a Bulk Silicon based FinFET

The heart of the FINFET is a thin Si fin, which serves as a body of the MOSFET. A heavily
doped poly Si film wraps around the fin and makes the electrical contact to the vertical faces
of the fin. A gap is etched through the poly Si film to separate the source and drain.
1. Substrate
Basis for a FinFET is a lightly p-doped substrate with a hard mask on top (e.g. silicon nitride) as
well as a patterned resist layer.

2. Fin etch
The fins are formed in a highly anisotropic etch process. Since there is no stop layer on a bulk
wafer as it is in SOI, the etch process has to be time based. In a 22 nm process the width of the
fins might be 10 to 15 nm, the height would ideally be twice that or more.

3. Oxide deposition
To isolate the fins from each other, a oxide deposition with a high aspect ratio filling behavior is
needed.
4. Planarization
The oxide is planarized by chemical mechanical polishing. The hard mask acts as a stop layer.

5. Recess etch
Another etch process is needed to recess the oxide film to form a lateral isolation of the fins.

6. Gate oxide
On top of the fins the gate oxide is deposited via thermal oxidation to isolate the channel from the
gate electrode. Since the fins are still connected underneath the oxide, a high-dose angled implant
at the base of the fin creates a dopant junction and completes the isolation.

7. Deposition of the gate

Finally a highly n+-doped poly silicon layer is deposited on top of the fins, thus up to three gates
are wrapped around the channel: one on each side of the fin, and - depending on the thickness of
the gate oxide on top - a third gate above.

The influence of the top gate can also be inhibited by the deposition of a nitride layer on top of
the channel.

Since there is an oxide layer on an SOI wafer, the channels are isolated from each other anyway.
In addition the etch process of the fins is simplified as the process can be stopped on the oxide
easily.
Working of FinFET
The working principle of a FinFET is similar to that of a conventional MOSFET. The
MOSFET can function in two modes for both p-channel and n-channel MOSFETs:
enhancement mode and depletion mode.

The channel shows maximum conductance when there is no voltage on the gate terminal. As
the voltage changes to positive or negative, the conductivity of the channel reduces.

In enhancement mode of MOSFET, when there is no voltage on the gate terminal, it does not
conduct. Unlike the depletion mode, in enhancement mode, the device conducts better when
there is more voltage on the gate terminal.

Figure 02: Diagram Depicting Working Principle of FinFET Based on MOORE’S law

Performance-IV characteristics

Figure 03: IV model

Benefits of FinFET
 They have much better performance and reduced power consumption compared
to planar transistors.
 Suppressed short channel effect.
 Higher technological maturity than planar DG.
 Better in driving current.
 More compact.
 Low cost.

Limitations
 On a bulk-silicon process, control over fin depth is more difficult.
 Higher source and drain resistances.

Applications of FinFET

 Possibility to save power arises when both gates can be controlled separately.
 The second gate can be used to control the threshold voltage of the device, thereby
allowing fast switching on one side and reduced leakage currents when circuits are
idle.
 Finally, separate access to both gates could also be used to design simplified logic
gates. This would also reduce power, and save chip area, leading to smaller, more
cost-efficient designs.
 World leader in smartphones, Samsung Electronics has incorporated FinFET in its
14nm processors. This processor is used in the latest Samsung smartphone, the
Samsung Galaxy S6. Along with Samsung, Apple, Intel and TSMC are set to ship the
14nm technology by 2016. This technology will benefit all smartphones as it will
speed up the phone.