CXP740056/740096/740010

CMOS 8-bit Single Chip Microcomputer

Description
The CXP740056/740096/740010 is a CMOS 8-bit 100 pin QFP (Plastic) 100 pin LQFP (Plastic)
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, capture timer/counter, remote control receive
circuit, PWM output, and the like besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O
port.
The CXP740056/740096/740010 also provides the
sleep/stop functions that enables lower power
Structure
consumption.
Silicon gate CMOS IC

Features
• A wide instruction set (211 instructions) which covers various types of data.
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle 167ns at 24MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (2.7 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM capacity 56K bytes (CXP740056)
96K bytes (CXP740096)
120K bytes (CXP740010)
• Incorporated RAM capacity 4096 bytes
• Peripheral functions
— A/D converter 8 bits, 8 channels, successive approximation method
(Conversion time 10.3µs at 24MHz)
— Serial interface Srart-stop synchronization (UART), 1 channel
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels
8-bit clock syncronization (MSB/LSB first selectable), 1 channel
— Timer 8-bit timer 2 channels, 8-bit timer/counter 2 channels,
19-bit time-base timer, 16-bit capture timer/counter
32kHz timer/counter
— Remote control receive circuit Noise elimination circuit
8-bit pulse measuring counter, 6-stage FIFO
— PWM output 12 bits, 2 channels
• Interruption 22 factors, 15 vectors, multi-interruption possible
• Standby mode Sleep/stop
• Package 100-pin plastic QFP/LQFP
• Piggy/evaluation chip CXP740000

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E98406-PS
 Block Diagram

INT4

INT0

AVREF
AVSS
NMI
INT1
EXTAL

INT3

AVDD
TX

INT2
VSS

RST
XTAL

TEX
VDD
AN0 to AN11 12 A/D CONVERTER 8 PA0 to PA7
CLOCK
SPC 700αII GENERATOR/
RxD UART RECEIVER CPU CORE SYSTEM CONTROL
TxD UART TRANSMITTER 8 PB0 to PB7
UART BAUD RATE
GENERATOR

12-BIT PWM GENERATOR 0 8 PC0 to PC7

PWM0
PWM1 12-BIT PWM GENERATOR 1 ROM RAM
56K/96K/120K 4096
RMC REMOCON IN FIFO BYTES BYTES 8 PD0 to PD7

INTERRUPT CONTROLLER
CS0 SERIAL
SI0 BUFFER 2 PE0 to PE1
INTERFACE
SO0 RAM
UNIT (CH0) 6 PE2 to PE7
SCK0
CS1 SERIAL
SI1

–2–
INTERFACE BUFFER 8 PF0 to PF7
SO1 RAM
SCK1 UNIT (CH1)

SI2
SO2 SERIAL INTERFACE UNIT PRESCALER/ 32kHz 8 PG0 to PG7
SCK2 (CH2) TIME-BASE TIMER TIMER-COUNTER

EC0 8-BIT TIMER/COUNTER 0

2 8 PH0 to PH7
TO0 8-BIT TIMER 1

EC1 8-BIT TIMER/COUNTER 2

2
TO1 8-BIT TIMER 3 7 PI1 to PI7
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A

TO2
16-BIT CAPTURE 2
CINT TIMER/COUNTER 4
EC2 8 PJ0 to PJ7
PORT J

PORT K
2

ADJ
PK3 to PK7
PK1 to PK2
CXP740056/740096/740010
 CXP740056/740096/740010

Pin Assignment (Top View) 100-pin QFP package

PI4/INT1/CS1
PI3/TO0/ADJ

PI5/SCK1
PK2/TEX
PI1/RMC
PI2/NMI
PK1/TX
PC7
PA0
PC6

PA4
PA1
PA2

PA5
PA6
PA3

PA7

VSS
VDD
NC
PC5
PC4 2
1 AA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
79
PI6/SO1
PI7/SI1
PC3 3 78 PE0/INT0
PC2 4 77 PE1/INT2
PC1 5 76 PE2/PWM0
PC0 6 75 PE3/PWM1
PB7/SI2 7 74 PE4
PB6/SO2 8 73 PE5
PB5/SCK2 9 72 PE6
PB4/TO2 10 71 PE7
PB3 11 70 PG0/TxD
PB2 12 69 PG1/RxD
PB1 13 68 PG2/EC0
PB0 14 67 PG3/EC1
PJ7 15 66 PG4/EC2
PJ6 16 65 PG5/INT3
PJ5 17 64 PG6/INT4
PJ4 18 63 PG7/CINT
PJ3 19 62 AN0
PJ2 20 61 AN1
PJ1 21 60 AN2
PJ0 22 59 AN3
PD7 23 58 PF0/AN4
PD6 24 57 PF1/AN5
PD5 25 56 PF2/AN6
PD4 26 55 PF3/AN7
PD3 27 54 AVDD
PD2 28 53 AVREF
PD1 29 52 AVSS
PD0 30 51 PF4/AN8
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
EXTAL
RST
PH2
PH6

PF7/AN11
PF6/AN10
PH0

PK5/SI0
PH3
PH7

PK6/CS0
PH4
PH5

PK7/TO1

VSS
PH1

PF5/AN9
PK4/SO0
PK3/SCK0
XTAL

Note) 1. NC (Pin 90) is left open.

2. VSS (Pins 41 and 88) are both connected to GND.

–3–
 CXP740056/740096/740010

Pin Assignment (Top View) 100-pin LQFP package

PI4/INT1/CS1
PI3/TO0/ADJ

PI5/SCK1

PE0/INT0
PK2/TEX
PI1/RMC

PI6/SO1
PI2/NMI
PK1/TX

PI7/SI1
PC4

PC7

PA2
PC5
PC6

PA5

PA7
PA6
PA0

PA4
PA3
PA1

VDD
VSS
NC
AA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

PC3 1 75 PE1/INT2
PC2 2 74 PE2/PWM0
PC1 3 73 PE3/PWM1
PC0 4 72 PE4
PB7/SI2 5 71 PE5
PB6/SO2 6 70 PE6
PB5/SCK2 7 69 PE7
PB4/TO2 8 68 PG0/TxD
PB3 9 67 PG1/RxD
PB2 10 66 PG2/EC0
PB1 11 65 PG3/EC1
PB0 12 64 PG4/EC2
PJ7 13 63 PG5/INT3
PJ6 14 62 PG6/INT4
PJ5 15 61 PG7/CINT
PJ4 16 60 AN0
PJ3 17 59 AN1
PJ2 18 58 AN2
PJ1 19 57 AN3
PJ0 20 56 PF0/AN4
PD7 21 55 PF1/AN5
PD6 22 54 PF2/AN6
PD5 23 53 PF3/AN7
PD4 24 52 AVDD
PD3 25 51 AVREF

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PH0
PD1

PH4

PK3/SCK0
PK4/SO0

PF6/AN10
PH3

PK6/CS0

AVSS
VSS
PH5

PH2
PD0

PK7/TO1
RST

XTAL
PH7

PH1
PH6

PF5/AN9
EXTAL

PK5/SI0

PF7/AN11

PF4/AN8
PD2

Note) 1. NC (Pin 88) is left open.

2. VSS (Pins 39 and 86) are both connected to GND.

–4–
 CXP740056/740096/740010

Pin Description

Symbol I/O Description

(Port A)
8-bit I/O port. I/O can be set in a unit of single bits.
PA0 to PA7 I/O Incorporation of pull-up resistor can be set through the program in a unit of
single bits.
(8 pins)

PB0 to PB3 I/O (Port B)

8-bit I/O port. I/O can be set
PB4/TO2 I/O/Output in a unit of single bits. 16-bit timer/counter rectangular wave output.
Incorporation of pull-up
PB5/SCK2 I/O/I/O Serial clock I/O (CH2).
resistor can be set through
PB6/SO2 I/O/Output the program in a unit of Serial data output (CH2).
single bits.
PB7/SI2 I/O/Input (8 pins) Serial data input (CH2).
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up
PC0 to PC7 I/O resistor can be set through the program in a unit of single bits.
(8 pins)
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink
PD0 to PD7 I/O current. Incorporation of pull-up resistor can be set through the program in a
unit of single bits.
(8 pins)
PE0/INT0 Input/Input External interrupt inputs.
(Port E) (2 pins)
PE1/INT1 Input/Input 8-bit port. Lower 2 bits are
PE2/PWM0 Output/Output for input; upper 6 bits are for 12-bit PWM outputs.
output. (2 pins)
PE3/PWM1 Output/Output (8 pins)
PE4 to PE7 Output
(Port F)
8-bit I/O port. PF4 to PF7
can be set in a unit of single
bits as standby release
PF0/AN4 inputs. I/O can be set in a
Analog inputs to A/D converter.
to I/O unit of single bits.
(8 pins)
PF7/AN11 Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(8 pins)

–5–
 CXP740056/740096/740010

Symbol I/O Description

PG0/TxD I/O/Output UART transmission data output.
PG1/RxD I/O/Input (Port G) UART reception data input.
PG2/EC0 I/O/Input 8-bit I/O port. I/O can be set External event input for 8-bit timer/counter 0.
in a unit of single bits.
PG3/EC1 I/O/Input Incorporation of pull-up External event input for 8-bit timer/counter 2.
PG4/EC2 I/O/Input resistor can be set through External event input for 16-bit timer/counter.
the program in a unit of
PG5/INT3 I/O/Input single bits. External interrupt inputs.
PG6/INT4 I/O/Input (8 pins) (2 pins)

PG7/CINT I/O/Input External capture input to 16-bit timer/counter.

(Port H)
8-bit I/O port. Operated as N-ch open drain output for medium voltage drive
PH0 to PH7 Output (12V) and large current (12mA).
(8 pins)
PI1/RMC I/O/Input Remote control receiver circuit input.
PI2/NMI I/O/Input Non-maskable interrupt input.
(Port I)
7-bit I/O port. I/O can be set Output for the 8-bit timer/counter 1
PI3/TO0/ I/O/Output/
in a unit of single bits. rectanguler waves and 32-kHz oscillation
ADJ Output
Incorporation of pull-up frequency demultiplication.
PI4/INT1/ I/O/Input/ resistor can be set through External Chip select input for serial
CS1 Input the program in a unit of interrupt input. interface (CH1).
single bits.
PI5/SCK1 I/O/I/O (7 pins) Serial clock I/O (CH1).
PI6/SO1 I/O/Output Serial data output (CH1).
PI7/SI1 I/O/Input Serial data input (CH1).
(Port J)
8-bit I/O port. I/O can be set in a unit of single bits.
Standby release input can be set in a unit of single bits.
PJ0 to PJ7 I/O Incorporation of pull-up resistor can be set through the program in a unit of
single bits.
(8 pins)
Crystal connectors for 32-kHz timer/counter
PK1/TX Input
(Port K) clock oscillation circuit.
7-bit port. lower 2 bits are for For usage as event count, connect clock
PK2/TEX Input/Input input; upper 5 bits are for I/O. oscillation source to TEX, and leave TX
I/O can be set in a unit of open.
PK3/SCK0 I/O/I/O single bits. Serial clock I/O (CH0).
For PK3 to PK7, incorporation
PK4/SO0 I/O/Output of pull-up resistor can be set Serial data output (CH0).
PK5/SI0 I/O/Input through the program in a unit Serial data input (CH0).
of single bits.
PK6/CS0 I/O/Input (7 pins) Chip select input for serial inteface (CH0).
PK7/TO1 I/O/Output 8-bit timer/counter 3 rectangular wave output.

–6–
 CXP740056/740096/740010

Symbol I/O Description

Analog inputs to A/D converter.
AN0 to AN3 Input
(4 pins)
EXTAL Input Connects a crystal for system clock oscillation. When a clock is supplied
externally, input it to EXTAL pin and input a reversed phase clock to XTAL
XTAL pin.
RST Input System reset; active at Low level.
Not connected.
NC
Leave this pin open for normal operation.
AVDD Positive power supply of A/D converter.
AVREF Input Reference voltage input of A/D converter.
AVSS GND of A/D converter.
VDD Positive power supply.
VSS GND. Connect both VSS pins to GND.

–7–
 CXP740056/740096/740010

I/O Circuit Format for Pins

Pin Circuit format After a reset

Port A
Port B AAAA
AAAAA
AAAA
Pull-up resistor ∗

AAAAA A
“0” after a reset
Port C
Ports A, B, C data

AAAAA A
PA0 to PA7
PB0

AAAAA AA
PB2
Ports A, B, C direction Hi-Z
PC0 to PC7

AA
“0” after a reset
IP
Internal data bus

RD (Ports A, B, C)
∗ Pull-up transistors
18 pins approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Port B
AAAA
AAAA
Pull-up resistor ∗

AAAA A
“0” after a reset

Port B data

PB1
AAAA A
AAAA AA
PB3 Port B direction
Hi-Z

AA
“0” after a reset
IP

Internal data bus Schmitt input

RD (Port B)
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
2 pins approx. 150kΩ (VDD = 2.7 to 3.3V)

AAA
Port I
Port K Pull-up resistor ∗

“0” after a reset

AAAA AA
TO0/ADJ, TO1

AAAA AA
Ports I, K function
select
PB4/TO2

AAAA
“0” after a reset
PI3/TO0/ADJ
Ports I, K data

AAAA AA
PK7/TO1 Hi-Z
Ports I, K direction
IP
“0” after a reset

Internal
data bus
RD (Ports B, I, K)
∗ Pull-up transistors
3 pins approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

–8–
 CXP740056/740096/740010

Pin Circuit format After a reset

Port B
Port I

AAAA
Port K

AAAA
Pull-up resistor ∗

AAAA
“0” after a reset

AAAA
Output buffer
capability

AAAA
“0” after a reset
Output enable

AAAA
PB5/SCK2 SCK2, SCK1, SCK0
PI5/SCK1

AAAA AA
Ports B, I, K function
PK3/SCK0 select Hi-Z

AAAA AA
“0” after a reset

AAAA AA
Ports B, I, K data

AA
Ports B, I, K direction
IP
“0” after a reset

Internal Schmitt input

data bus
RD (Ports B, I, K)

SCK2, SCK1, SCK0 ∗ Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
3 pins approx. 150kΩ (VDD = 2.7 to 3.3V)

Port B
Port G
Port I

AAAA
Port K

AAAA
Pull-up resistor ∗

AAAA
“0” after a reset

AAAA
Output buffer
capability

“0” after a reset

PB6/SO2
Output enable
PG0/TxD

AAAA
TO2, SO2, TxD, SO1, SO0
PI6/SO1 Hi-Z

AAAA AA
PK4/SO0 Ports B, G, I, K
function select

AAAA AA
“0” after a reset

AAAA AA
Ports B, G, I, K data

AAAA
Ports B, G, I, K IP
direction
“0” after a reset

Internal
data bus
RD (Ports B, G, I, K)
∗ Pull-up transistors
4 pins approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

–9–
 CXP740056/740096/740010

Pin Circuit format After a reset

Port B
Port G
AAAAA
AAAAA
PB7/SI2 Pull-up resistor ∗
Port I
PG1/RxD

AAAAA AA
“0” after a reset
PG2/EC0 Port K
PG3/EC1 Ports B, G, I, K data

AAAAA A AA
PG4/EC2
PG5/INT3

AAAAA A
PG6/INT4 Ports B, G, I, K direction IP
PG7/CINT
“0” after a reset Hi-Z
PI1/RMC Schmitt input
PI2/NMI Internal data bus
PI4/INT1/CS1 RD (Ports B, G, I, K)
PI7/SI1
PK5/SI0 SI2, RxD, EC0, EC1, EC2, INT3, INT4, CINT,
PK6/CS0 RMC, MNI, INT1/CS1, SI1, SI0, CS0
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
14 pins

Port D
AAAA
AAAA
Pull-up resistor ∗2

AAAA AA
“0” after a reset

Port D data

AAAA AA
AAAA A
∗1
PD0 to PD7 Port D direction
IP Hi-Z
Internal data bus

RD (Port D)
∗1 Large current
12mA (VDD = 4.5 to 5.5V)
4.5mA (VDD = 2.7 to 3.3V)
∗2 Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
8 pins approx. 150kΩ (VDD = 2.7 to 3.3V)

AAAA
Port E
Schmitt input

AAAA
PE0/INT0
PE1/INT2 IP INT0, INT2
Hi-Z
Internal data bus

RD (Port E)
2 pins

– 10 –
 CXP740056/740096/740010

Pin Circuit format After a reset

Port E

AAAA AA
PWM0, PWM1

AAAA AA
Port E function select
PE2/PWM0

AAAA
PE3/PWM1 “0” after a reset
Hi-Z
Port E data
Hi-Z by writing to Port E data register or Port E
function select register → Output active
Internal data bus
2 pins

AAAA
RD (Port E)

AAAA AA
Port E

AA
Port E data
PE4
PE5 Internal data bus Hi-Z
RD (Port E)

Hi-Z by writing to Port E data

2 pins register → Output active

AAAA AA
Port E

PE6
AAAA Port E data

“1” after a reset

Internal data bus

AA High level

1 pin RD (Port E)

Port E
Internal reset signal ∗

AAAA AA
"H" level

) )
"H"level at

AAAA AA
ON
PE7
Port E data resistance
of pull-up
“1” after a reset
transistor
Internal data bus during a
∗ Pull-up transistors reset.
RD (Port E) approx. 150kΩ (VDD = 4.5 to 5.5V)
approx. 200kΩ (VDD = 2.7 to 3.3V)
1 pin

AAAA
Input multiplexer
AN0 to AN3

AA
IP A/D converter Hi-Z

4 pins

– 11 –
 CXP740056/740096/740010

Pin Circuit format After a reset

Port F

AAAA
AAAA
Pull-up resistor ∗

AAAA AA
“0” after a reset

Port F data

PF0/AN4
to
PF3/AN7
AAAA
AAAA
Port F direction
“0” after a reset
A
A
AA IP
Hi-Z
Internal data bus

AAAA
AAAA
RD (Port F)

Port F
function select
“0” after a reset
Input multiplexer
A/D converter
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
4 pins approx. 150kΩ (VDD = 2.7 to 3.3V)

AAAA
Port F

AAAA Pull-up resistor ∗

AAAA
“0” after a reset

AAAA AA
Port F data

AAAA AA
AA
Port F direction
IP
“0” after a reset

AAAA
Internal data bus
PF4/AN8

AAAA
RD (Port F)
to
PF7/AN11 Port F Hi-Z
function select

A
“0” after a reset

Standby release

AAAAA
Edge detection

AAAA Polarity select

“0” after a reset

A/D converter
Input multiplexer

∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
4 pins approx. 150kΩ (VDD = 2.7 to 3.3V)

– 12 –
 CXP740056/740096/740010

AA
Pin Circuit format After a reset
Port H

PH0 to PH7
AAAA Port H data

“1” after a reset

∗
AA Hi-Z
Internal data bus ∗ High tension proof 12V
Large current
RD (Port H)
12mA (VDD = 4.5 to 5.5V)
8 pins 4.5mA (VDD = 2.7 to 3.3V)

Port J
AAAA
AAAA Pull-up resistor ∗

AAAA
“0” after a reset

AAAA AA
Port J data

AAAA AA
AA
Port J direction
IP
PJ0 to PJ7 “0” after a reset
Internal data bus Hi-Z
RD (PortJ)

Standby release

AAAA A
Edge detection

8 pins
AAAA Polarity select
“0” after a reset
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Port K
TEX oscillation circuit control
“1” after a reset

Internal
data bus
RD (Port K)

PK1/TX
Internal Oscillation
PK2/TEX data bus
stop port
RD (Port K)
Schmitt input
input
PK2/TEX IP IP
Clock input

2 pins PK1/TX

– 13 –
 CXP740056/740096/740010

Pin Circuit format After a reset

EXTAL
XTAL
AA
EXTAL
AA A
AA AA A IP IP
• Diagram shows circuit configuration
during oscillation.
• When program stops the oscillation, Oscillation

AA
the feedback registor disconnects,
and XTAL is driven at "H" level.

AA
2 pins XTAL

Pull-up resistor
RST "L" level

AA AA
Mask option OP
(during a
Schmitt input
reset)
IP

1 pin

– 14 –
 CXP740056/740096/740010

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Rating Unit Remarks

VDD –0.3 to +7.0 V
AVDD AVSS to +7.0∗1 V
Supply voltage
AVSS –0.3 to +0.3 V
AVREF AVSS to +7.0 V
Input voltagte VIN –0.3 to +7.0∗2 V
Output voltage VOUT –0.3 to +7.0∗2 V
High level output current IOH –5 mA Output (value per pin)
High level total output current ∑IOH –50 mA Total for all output pins
All pins excluding large current
IOL 15 mA
Low level output current outputs (value per pin)
IOLC 20 mA Large current outputs (value per pin) ∗3
Low level total output current ∑IOL 100 mA Total for all output pins
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +150 °C
600 QFP package
Allowable power dissipation PD mW
380 LQFP package
∗1 AVDD and VDD must be set to the same voltage.
∗2 VIN and VOUT must not exceed VDD + 0.3V.
∗3 The large current output pins are Port D and H (PD, PH).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.

– 15 –
 CXP740056/740096/740010

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

4.5 5.5 V fc = 24MHz or less Guaranteed operation
range for 1/2 and 1/4
2.7 5.5 V fc = 12MHz or less frequency dividing clock.
Guaranteed operation range for 1/16
Supply voltage VDD 2.7 5.5 V
frequency dividing clock or sleep mode
2.7 5.5 V Guaranteed operation range for TEX
Guaranteed data hold operation range
2.5 5.5 V
during stop mode
Analog voltage AVDD 2.7 5.5 V ∗1

0.7VDD VDD V ∗2, ∗6

VIH
0.8VDD VDD V ∗2, ∗7

Hysteresis input∗3
High level input
VIHS 0.8VDD VDD V
voltage
VDD – 0.4 VDD + 0.3 V EXTAL pin∗4, ∗6, TEX pin∗5, ∗6
VIHEX
VDD – 0.2 VDD + 0.2 V EXTAL pin∗4, ∗7, TEX pin∗5, ∗7
0 0.3VDD V ∗2, ∗6
VIL
0 0.2VDD V ∗2, ∗7

Hysteresis input∗3
Low level input
VILS 0 0.2VDD V
voltage
–0.3 0.4 V EXTAL pin∗4, ∗6, TEX pin∗5, ∗6
VILEX
–0.3 0.2 V EXTAL pin∗4, ∗7, TEX pin∗5, ∗7
Operating temperature Topr –20 +75 °C

∗1 AVDD and VDD must be set to the same voltage.

∗2 Normal input port (PA, PB0, PB2, PB4, PB6, PC, PD, PF, PG0, PI3, PI6, PJ, PK1, PK2, PK4, PK7)
∗3 RST, PB1, PB3, PB5/SCK2, PB7/SI2, PE0/INT0, PE1/INT2, PG1/RxD, PG2/EC0, PG3/EC1, PG4/EC2,
PG5/INT3, PG6/INT4, PG7/CINT, PI1/RMC, PI2/NMI, PI4/INT1/CS1, PI5/SCK1, PI7/SI1, PK3/SCK0,
PK5/SI0, PK6/CS0
∗4 Specifies only when the external clock is input.
∗5 Specifies only when the external event count is input.
∗6 This case applies to the range of 4.5 to 5.5V supply voltage (VDD).
∗7 This case applies to the range of 2.7 to 5.5V supply voltage (VDD).

– 16 –
 CXP740056/740096/740010

Electrical Characteristics

DC Characteristics (VDD = 4.5 to 5.5V) (Ta = –20 to +75°C, VSS = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit

PA to PD,
VDD = 4.5V, IOH = –0.5mA 4.0 V
PE2 to PE7,
PF to PG,
PI to PJ, VDD = 4.5V, IOH = –1.2mA 3.5
High level V
VOH PK3 to PK7
output voltage
PB5, PB6∗1, VDD = 4.5V, IOH = –1.0mA 4.0 V
PG0∗1,
PI5, PI6∗1,
PK3, PK4∗1
VDD = 4.5V, IOH = –2.4mA 3.5 V

PA to PD,
VDD = 4.5V, IOL = 1.8mA 0.4 V
PE2 to PE7,
Low level PF to PG,
output voltage VOL PI to PJ, VDD = 4.5V, IOL = 3.6mA 0.6 V
PK3 to PK7
PD, PH VDD = 4.5V, IOL = 12.0mA 1.5 V
IIHE VDD = 5.5V, VIH = 5.5V 0.5 40 µA
EXTAL
IILE VDD = 5.5V, VIL = 0.4V –0.5 –40 µA
IIHT VDD = 5.5V, VIL = 5.5V 0.1 10 µA
TEX
Input current IILT VDD = 5.5V, VIL = 0.4V –0.1 –10 µA
IILR RST∗2 –1.5 –400 µA
VDD = 5.5V, VIL = 0.4V
PA to PD∗3, –45 µA
IIL PF to PG∗3,
PI to PK∗3 VDD = 4.5V, VIL = 4.0V –2.78 µA
PA to PD∗3,
PF to PG∗3,
I/O leakage PI to PK∗3, VDD = 5.5V
IIZ ±10 µA
current PE, VI = 0, 5.5V
AN0 to AN3
RST∗2
Open drain
output leakage
VDD = 5.5V
current LLOH PH 50 µA
VOH = 12V
(N-ch Tr off
state)

– 17 –
 CXP740056/740096/740010

Item Symbol Pins Conditions Min. Typ. Max. Unit

24MHz crystal oscillation
IDD1 (C1 = C2 = 15pF) 27 47 mA
VDD = 5V ± 0.5V
Sleep mode
IDDS1 1.0 5.0 mA
VDD = 5V ± 0.5V
32kHz crystal oscillation
Supply IDD2 (C1 = C2 = 47pF) 30 75 µA
VDD
current∗4 VDD = 3V ± 0.3V
Sleep mode
IDDS2 12 40 µA
VDD = 3V ± 0.3V
Stop mode
(Termination of EXTAL and TEX pins
IDDS3 crystal oscillation) 10 µA

VDD = 5V ± 0.5V
PA to PD,
PE0 to PE1,
PF to PG, Clock 1MHz
Input
CIN PI to PK, 0V for all pins excluding measured 10 20 pF
capacity
AN0 to AN3, pins
EXTAL,
RST
∗1 This case applies that Port B buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = "1, 1") and
Ports G/I/K buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4, 3 and 0= "1, 1, 1, 1, 1") are ON.
∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current
when no resistor is selected.
∗3 PA to PD, PF to PG and PI to PK pins specify the input current when the pull-up resistor is selected, and
specify the leakage current when no resistor is selected.
∗4 When all pins are open.

– 18 –
 CXP740056/740096/740010

Electrical Characteristics

DC Characteristics (VDD = 2.7 to 3.3V) (Ta = –20 to +75°C, VSS = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit
PA to PD,
VDD = 2.7V, IOH = –0.12mA 2.5 V
PE2 to PE7,
PF to PG,
PI to PJ, VDD = 2.7V, IOH = –0.45mA 2.1
High level V
VOH PK3 to PK7
output voltage
PB5, PB6∗1, VDD = 2.7V, IOH = –0.24mA 2.5 V
PG0∗1,
PI5, PI6∗1,
PK3, PK4∗1 VDD = 2.7V, IOH = –0.9mA 2.1 V

PA to PD,
VDD = 2.7V, IOL = 1.0mA 0.25 V
PE2 to PE7,
Low level PF to PG,
output voltage VOL PI to PJ, VDD = 2.7V, IOL = 1.4mA 0.4 V
PK3 to PK7
PD, PH VDD = 2.7V, IOL = 4.5mA 0.9 V
IIHE VDD = 3.3V, VIH = 3.3V 0.3 20 µA
EXTAL
IILE VDD = 3.3V, VIL = 0.3V –0.3 –20 µA
IIHT VDD = 3.3V, VIL = 3.3V 0.1 10 µA
TEX
Input current IILT VDD = 3.3V, VIL = 0.4V –0.1 –10 µA
IILR RST∗2 –0.9 –200 µA
VDD = 3.3V, VIL = 0.3V
PA to PD∗3, –20 µA
IIL PF to PG∗3,
PI to PK∗3 VDD = 3.3V, VIL = 2.7V –1.0 µA
PA to PD∗3,
PF to PG∗3,
I/O leakage PI to PK∗3, VDD = 3.3V
IIZ ±10 µA
current PE, VI = 0, 3.3V
AN0 to AN3
RST∗2
Open drain
output leakage
VDD = 3.3V
current LLOH PH 50 µA
VOH = 12V
(N-ch Tr off
state)

– 19 –
 CXP740056/740096/740010

Item Symbol Pins Conditions Min. Typ. Max. Unit

12MHz crystal oscillation
IDD1 (C1 = C2 = 15pF) 8 20 mA
VDD = 3.0V ± 0.3V∗3
Sleep mode
Supply IDDS1 0.3 1.5 mA
VDD
current∗4 VDD = 3.0V ± 0.3V
Stop mode
(Termination of EXTAL and TEX pins
IDDS3 crystal oscillation) 10 µA

VDD = 3.0V ± 0.3V

PA to PD,
PE0 to PE1,
PF to PG, Clock 1MHz
Input
CIN PI to PK, 0V for all pins excluding measured 10 20 pF
capacity
AN0 to AN3, pins
EXTAL,
RST

∗1 This case applies that Port B buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = "1, 1") and
Ports G/I/K buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4, 3 and 0 = "1, 1, 1, 1, 1") are ON.
∗2 RST pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current
when no resistor is selected.
∗3 PA to PD, PF to PG and PI to PK pins specify the input current when the pull-up resistor is selected, and
specify the leakage current when no resistor is selected.
∗4 When all pins are open.

– 20 –
 CXP740056/740096/740010

AC Characteristics
(1) Clock timing (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)
Item Symbol Pin Conditions Min. Typ. Max. Unit

XTAL VDD = 4.5 to 5.5V 1 24

System clock frequency fC Fig. 1, Fig. 2 MHz
EXTAL 1 12

System clock input pulse tXL, Fig. 1, Fig. 2 VDD = 4.5 to 5.5V 28
EXTAL ns
width tXH External clock drive 37.5
System clock input tCR, Fig. 1, Fig. 2
200 ns
EXTAL
rise time, fall time tCF External clock drive
Event count input clock tEH, Fig. 3 tsys + 50∗1 ns
EC
pulse width tEL
Event count input clock tER, Fig. 3 20 ms
EC
rise time, fall time tEF
VDD = 2.7 to 5.5V
TEX
System clock frequency fC Fig. 2 (32kHz clock applied 32.768 kHz
TX
condition)
Event count input clock tTL, Fig. 3 10 µs
TEX
pulse width tTH
Event count input clock tTR, Fig. 3 20 ms
TEX
rise time, fall time tTF
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 000FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
1/fc

VDD – 0.4V (VDD = 4.5 to 5.5V)

EXTAL VDD – 0.3V
0.4V (VDD = 4.5 to 5.5V)
0.3V

tXH tCF tXL tCR

Fig. 1. Clock timing

AAAA AAAAAAAA
Crystal oscillation 32kHz clock applied condetions
Ceramic oscillation External clock crystal oscillation

AAAAAAAAAAAA
EXTAL

C1
XTAL

C2
EXTAL

74HC04
XTAL

C1
TEX TX

C2

Fig. 2. Clock applied conditions

0.8VDD
TEX
EC0
EC1 0.2VDD
EC2

tEH tEF tEL tER

tTH tTF tTL tTR
Fig. 3. Event count clock timing
– 21 –
 CXP740056/740096/740010

(2) Serial transfer (CH0, CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Conditions Min. Max. Unit
CS↓ → SCK SCK0 Chip select transfer mode
tDCSK 1.5tsys + 200 ns
delay time SCK1 (SCK = output mode)
CS↑ → SCK SCK0 Chip select transfer mode
tDCSKF 1.5tsys + 200 ns
floating delay time SCK1 (SCK = output mode)

CS↓ → SO delay time tDCSO SO0

Chip select transfer mode 1.5tsys + 200 ns
SO1
CS↑ → SO floating SO0
tDCSOF Chip select transfer mode 1.5tsys + 200 ns
delay time SO1

CS High level width tWHCS CS0 tsys + 200 ns

Chip select transfer mode
CS1

SCK0 Input mode 2tsys + 200 ns

SCK cycle time tKCY
SCK1 Output mode 8000/fc ns

SCK High and Low tKH SCK0 Input mode tsys + 100 ns
level width tKL SCK1 Output mode 4000/fc – 50 ns

SI input setup time SI0 SCK input mode –tsys + 100 ns

(for SCK↑)
tSIK
SI1 SCK output mode 200 ns

SI input hold time SI0 SCK input mode 2tsys + 200 ns

(for SCK↑)
tKSI
SI1 SCK output mode 100 ns

SCK↓ → SO SO0 SCK input mode 2tsys + 200 ns

delay time
tKSO
SO1 SCK output mode 100 ns

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1
and SO1 for CH1, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
Note 4) This case applies that Port I/K output buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4
and 3 = "0, 0, 0, 0") is OFF.

– 22 –
 CXP740056/740096/740010

Serial transfer (CH0, CH1) (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item Symbol Pin Conditions Min. Max. Unit
CS↓ → SCK SCK0 Chip select transfer mode
tDCSK 1.5tsys + 250 ns
delay time SCK1 (SCK = output mode)
CS↑ → SCK SCK0 Chip select transfer mode
tDCSKF 1.5tsys + 250 ns
floating delay time SCK1 (SCK = output mode)
SO0
CS↓ → SO delay time tDCSO Chip select transfer mode 1.5tsys + 250 ns
SO1
CS↑ → SO floating SO0
tDCSOF Chip select transfer mode 1.5tsys + 250 ns
delay time SO1
CS0
CS High level width tWHCS Chip select transfer mode tsys + 200 ns
CS1

SCK0 Input mode 2tsys + 200 ns

SCK cycle time tKCY
SCK1 Output mode 8000/fc ns

SCK High and Low tKH SCK0 Input mode tsys + 100 ns
level widths tKL SCK1 Output mode 4000/fc – 100 ns

SI input setup time SI0 SCK input mode –tsys + 100 ns

(for SCK↑)
tSIK
SI1 SCK output mode 200 ns

SI input hold time SI0 SCK input mode 2tsys + 200 ns

(for SCK↑)
tKSI
SI1 SCK output mode 100 ns

SCK↓ → SO SO0 SCK input mode 2tsys + 250 ns

delay time
tKSO
SO1 SCK output mode 125 ns

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1
and SO1 for CH1, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
Note 4) This case applies that Port G/I/K output buffer capability switching register (BUFG: 010F5h, bits 6, 5,
4 and 3 = "1, 1, 1, 1") is ON.

– 23 –
 CXP740056/740096/740010

tWHCS

CS0
CS1
0.8VDD

0.2VDD

tKCY

tDCSK tDCSKF
tKL tKH

0.8VDD 0.8VDD
SCK0
SCK1
0.2VDD

tSIK tKSI

0.8VDD
SI0
Input data
SI1
0.2VDD

tDCSO tKSO tDCSOF

0.8VDD
SO0
Output data
SO1
0.2VDD

Fig. 4. Serial transfer CH0, CH1 timing

– 24 –
 CXP740056/740096/740010

Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit

Input mode 1000 ns
SCK cycle time tKCY SCK2
Output mode 8000/fc ns

SCK High and Low tKH Input mode 400 ns

SCK2
level widths tKL Output mode 4000/fc – 50 ns

SI input setup time SCK input mode 100 ns

tSIK SI2
(for SCK↑) SCK output mode 200 ns

SI input hold time SCK input mode 200 ns

tKSI SI2
(for SCK↑) SCK output mode 100 ns
SCK input mode 200 ns
SCK↓ → SO delay time tKSO SO2
SCK output mode 100 ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL.
Note 4) This case applies that Port B output buffer capability switching register (BUFB: 010F4h, bits 6 and 5 =
“0, 0”) is OFF.

Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit

Input mode 1000 ns
SCK cycle time tKCY SCK2
Output mode 8000/fc ns

SCK High and Low tKH Input mode 400 ns

SCK2
level widths tKL Output mode 4000/fc – 100 ns

SI input setup time SCK input mode 100 ns

tSIK SI2
(for SCK↑) SCK output mode 200 ns

SI input hold time SCK input mode 200 ns

tKSI SI2
(for SCK↑) SCK output mode 100 ns
SCK input mode 250 ns
SCK↓ → SO delay time tKSO SO2
SCK output mode 125 ns

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF.
Note 4) This case applies that Port B output buffer capability switching register (BUFB: 010F4h, bits 6 and 5 =
“1, 1”) is ON.

– 25 –
 CXP740056/740096/740010

tKCY

tKL tKH

0.8VDD
SCK2
0.2VDD

tSIK tKSI

0.8VDD

SI2 Input data

0.2VDD

tKSO

0.8VDD

SO2 Output data

0.2VDD

Fig. 5. Serial transfer CH2 timing

– 26 –
 CXP740056/740096/740010

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)

Item Symbol Pin Conditions Min. Typ. Max. Unit

Resolution 8 Bits
Linearity errror Ta = 25°C ±2 LSB
VDD = AVDD = AVREF = 5.0V
Absolute error VSS = AVSS = 0V ±3 LSB
Conversion time tCONV 31/fADC∗3, ∗4 µs
Sampling time tSAMP 10/fADC∗3, ∗4 µs
Reference input voltage VREF AVREF VDD = AVDD = 4.5 to 5.5V AVDD – 0.5 V
Analog input voltage VIAN AN0 to AN11 0 V
IREF Operation mode 0.6 1.0 mA

AVREF current AVREF Sleep mode

IREFS Stop mode 10 µA
32kHz operation mode

(Ta = –20 to +75°C, VDD = AVDD = 2.7 to 3.3V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference)

Item Symbol Pin Conditions Min. Typ. Max. Unit

Resolution 8 Bits
Linearity errror Ta = 25°C ±2 LSB
VDD = AVDD = AVREF = 3.0V
Absolute error VSS = AVSS = 0V ±3 LSB
Conversion time tCONV 31/fADC∗3, ∗4 µs
Sampling time tSAMP 10/fADC∗3, ∗4 µs
Reference input voltage VREF AVREF VDD = AVDD = 2.7 to 3.3V AVDD – 0.3 V
Analog input voltage VIAN AN0 to AN11 0 V
IREF Operation mode 0.4 0.7 mA

AVREF Sleep mode

AVREF current
IREFS Stop mode 10 µA
32kHz operation mode

∗1 VZT: Value at which the digital conversion value changes

FFh
FEh from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes
Digital conversion value

from FEh to FFh and vice versa.

∗3 fADC indicates the below values due to the contents of bit
6 (CKS) of the A/D control register (ADC: 000F9h).
PS3 selected fADC = fc/4
Linearity error
PS4 selected fADC = fc/8
01h However, when PS3 is selected, fc is 12MHz or less.
00h ∗4 Sub clock operated tCONV = 34/fTEX
VZT VFT
Analog input tSAMP = 10/fTEX
Fig. 6. Definition of A/D converter terms
– 27 –
 CXP740056/740096/740010

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit

INT0
INT1
External interruption tIH INT2 1 µs
High and Low level widths tIL INT3
INT4
NMI
Reset input Low level width tRSL RST 32/fc µs

tIH tIL

INT0 0.8VDD
INT1
INT2 0.2VDD
INT3
INT4 tIL tIH
NMI
(NMI is specified only for
the falling edge)

Fig. 7. Interruption input timing

tRSL

RST
0.2VDD

Fig. 8. RST input timing

– 28 –
 CXP740056/740096/740010

Appendix

Fig. 9. Recommended oscillation circuit

AAAAA AAAA AAAAA

(i) Main clock (ii) Main clock (iii) Sub clock

AAAAA AAAA AAAAA

AA
EXTAL XTAL EXTAL XTAL TEX TX

AA
Rd Rd Rd

AA
C1 C2 C1 C2

C1 C2

fc (MHz) Circuit Remarks

Manufacturer Model C1 (pF) C2 (pF) Rd (Ω)
example
CSA10.0MTZ 10.0
30 30
CSA12.0MTZ 12.0 (i)
CSA16.00MXZ040 16.0 5 5
MURATA MFG 0 ∗1
CO., LTD. CST10.0MTW∗ 10.0
30 30
CST12.0MTW∗ 12.0 (ii)
CST16.00MXW0C1∗ 16.0 5 5
8.0 18 18
RIVER
ELETEC HC-49/U03 12.0 12 12 330 ∗1
CO., LTD.
16.0 10 10
(i)
8.0 10 10
HC-49/U (-S) 12.0 5 5 0 ∗1
KINSEKI LTD.
16.0 Open Open
P3 32.768kHz 30 33 120k (iii)
Seiko VTC-200
32.768kHz 18 18 330k (iii) CL = 12.5pF
Instruments Inc. SP-T

∗ Indicates types with on-chip grounding capacitor (C1, C2).

∗1 XTAL series resistor (Rd = 500Ω or less) is hard to affect noise by ESD.

– 29 –
 CXP740056/740096/740010

Characteristics Curve

IDD vs. VDD IDD vs. fc

(fc = 24MHz, Ta = 25°C, Typical) (VDD = 5.0V, Ta = 25°C, Typical)
1/2 dividing mode

20.0 1/4 dividing mode

10.0 30
1/16 dividing mode
5.0 1/2 dividing mode
IDD – Supply current [mA]

IDD – Supply current [mA]

Sleep mode

1.0
20
0.5

1/4 dividing mode

0.1 32kHz operation

(100µA) mode 10
0.05
(50µA) 32kHz sleep mode
1/16 dividing mode
0.01
(10µA) Sleep mode
0
0 10 20 24
2 3 4 5 6
fc – System clock [MHz]
VDD – Supply voltage [V]

IDD vs. VDD IDD vs. fc

(fc = 12MHz, Ta = 25°C, Typical) (VDD = 3.0V, Ta = 25°C, Typical)

20.0 1/2 dividing mode

1/4 dividing mode
10.0
30
5.0
IDD – Supply current [mA]

1/16 dividing mode

IDD – Supply current [mA]

Sleep mode

1.0
20
0.5

1/2 dividing mode

0.1
(100µA) 10
0.05
(50µA) 1/4 dividing mode

0.01 1/16 dividing mode

(10µA) Sleep mode
0
0 10 20 24
2 3 4 5 6
fc – System clock [MHz]
VDD – Supply voltage [V]

– 30 –
 CXP740056/740096/740010

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4 + 0.1
20.0 – 0.1 0.15 – 0.05

80 51

81 50

15.8 ± 0.4
14.0 – 0.1
17.9 ± 0.4
+ 0.4
A

100 31

1 + 0.15 30
0.65 0.3 – 0.1 + 0.35
0.13 M 2.75 – 0.15

+ 0.2
0.1 – 0.05
0.15
(16.3)

0° to 10°
0.8 ± 0.2

DETAIL A

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-100P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE QFP100-P-1420 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 1.7g

100PIN LQFP (PLASTIC)

16.0 ± 0.2
∗ 14.0 ± 0.1

75 51

76 50
(15.0)

A
0.5 ± 0.2

100 26 (0.22)

1 25
+ 0.08 + 0.05
0.5 0.18 – 0.03 0.127 – 0.02
0.13 M + 0.2
1.5 – 0.1
0.1

0.1 ± 0.1

NOTE: Dimension “∗” does not include mold protrusion.

0.5 ± 0.2

0° to 10°

DETAIL A PACKAGE STRUCTURE

PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-100P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE LQFP100-P-1414 LEAD MATERIAL 42 ALLOY

JEDEC CODE PACKAGE MASS 0.8g

– 31 –