UNIT V

2 mark:

1.What is programmable logic array.How it differs from ROM?(Nov/Dec 2018)

2.interpret READ and WRITE operation(Nov/Dec 2018)
3.State the advantages of CMOS logic
4.Differentiate between PAL and PLA(Apr/May 2017)
5.What is FPGA(Nov/Dec 2014)
6.Define noise margin(May/June 2016)
7.Draw the CMOS inverter circuit(Nov/Dec 2014)
8.What is the basic difference between the RAM and ROM circuit(Apr/May 2015)
9.What is the memory capacity of random access memeory if it has 10 bit address line(Nov/Dec
2017)
10.Briefly explain about EEPROM(Nov/Dec 2016)
11.How does ROM retain information(Apr/May 2017)
12.Compare and contrast EEPROM and Flash memory.(Nov/Dec 2014)
13.Compare static RAM and Dynamic RAM(Apr/May 2015)
14. Mention few applications of PLA and PAL. [April/May-2012]
15. Draw the structure of a static RAM cell. [April/May-2014]
16. What is volatile and non-volatile memory? [Nov/Dec-2013]
17. Define the term Fan out. [Nov/Dec-2011]
18. What is a totem pole output? [April/May-2011]
19. Give the advantages of RAM. [Nov/Dec-2013]
20. What is a totem pole output? [April/May-2011]
13 mark:

1.Implement BCD to Excess 3 code conversion using PLA(Apr/May 2018)

2.Explain in detail about the working of bipolar SRAM and DRAM cell with neat
sketches.(Apr/May 2018)

(or)

Differentiate static and dynamic RAM. Draw the circuit of one cell of each and explain its
working.(Nov/Dec 2018)
3.Illustrate the circuit operation and characteristics of TTL NAND logic gate in detail(Nov/Dec
2018)

(or)

Explain the tristate configuration with neat diagram(Apr/May 2018)

4.Implement the following function using PLA.(May/June 2016)

F1(x,y,z)=m(1,2,4,6)

F2(x,y,z)= m(0,1,6,7)

F3(x,y,z)= m(2,6)

5.Write a short note on FPGA.(May/June 2016)

(or)

Discuss the features and functional blocks of FPGA.(Nov/Dec 2017)

6.Give the comparison between PROM,PAL and PLA with respect to various performance
feature.(Nov/Dec 2016)

7.Using PLA with 3 inputs,4 AND terms and 2 outputs to implement the following two Boolean
functions(Nov/Dec 2014)

F1(a,b,c)=m(3,5,6,7)

F2(a,b,c)= m(1,2,3,4)

8.Explain memory decoding. Compare the RAM,ROM,PROM,EPROM.(Apr/May 2017)

9.Obtain the programming table for the SUM output of the Full Adder to implement with
PLA.(Nov/Dec2018)

10.List the CMOS characteristics. Draw the circuit diagram of basic CMOS inverter and explain
the operation

UNIT III

2 mark:

1.Distinguish between combinational circuit and sequential circuit(Apr/May 2015)

2.What are the classification of sequential circuit(Nov/Dec 2016)
3.Realize JK Flip flops(Nov/Dec 2014)
4.Define race around condition?(Nov/Dec 2016)
5.Derive the characteristic equation of D Flip flop(Apr/may 2017)
6.Draw D latch with truth table(Nov/Dec 2017)
7.What is the significance of state assignment(Apr/May 2017)
8.How does ripple counter differ from synchronous counter(Nov/Dec 2014)
9.Define shift register/(Nov/Dec 2018)
10. Mention any two differences between the edge triggering and level triggering.
[April/May-2010]
11. How many flip-flops are required to build a binary counter that counts from 0 to 1023?
[April/May-2013]
12. Compare the logics of synchronous counter and ripple counter. [April/May-2014, Nov/Dec-
2009]
13. Draw the state table and excitation table of T flip-flop. [Nov/Dec-2010]
14. What is synchronous sequential circuit? [Nov/Dec-2013]
15. Define latches. [Nov/Dec-2013]
16.What is the primary disadvantages of asynchronous counter?(Apr/May 2017)
17.A binary ripple counter is reuired to count upto 1638310.How many flipflops are required?If
the clock frequency is 8.192MHz,what is the frequency at the output of MSB?(Apr/May 2018)
18.Draw the circuit diagram of 4 bit ring counter using DFlipflop/(Nov/Dec 2018)
19.Define Universal Shift register
20.Define sequential circuit.

13 mark:

1.Explain in detail about the ring counter with its logic diagram,state diagram and its sequence
table(Apr/May 2018)

2.Explain the operation of synchronous MOD 6 counter.(Nov/Dec 2018)

3.a)Explain the operation of JK Flipflop with neat diagram(Nov/Dec 2018)

b)Explain the operation of master slave flipflop and show how race condition is
eliminated.(Nov/Dec 2018)

4.Design an 3-bit synchorounous counter using JK Flip flop.(Nov/Dec 2014)

5.Design a synchronous UP/DOWN counter(Nov/Dec 2016)

6.Using D Flip flop, design a synchronous counter which counts in the sequence
000,001,010,011,100,110,111,000. (Apr/May 2015)

7.Draw and explain 4 bit shift SISO,SIPO,PISO and PIPO with its waveform(May/June 2016)

8.Design a synchronous sequential circuit using JK Flipflop to generate the following sequence
and repeat 0,1,2,4,5,6(Apr/May 2010)

9.Discuss the working of 4 bit Johnson counter with a neat diagram.(Apr/May 2015)
10.Design a serial 2’s complement circuit with a shift register and a flipflop.The binary number
is shifted out from one side and its 2’s complement shifted into other side of the shift
register.(Nov/Dec 2017)