9/29/2018 Combinational circuits | Digital circuits | Electronics and Communication Engineering | ECE | GATE Syllabus, Paper Solution, Questi…

 Weightage of Combinational circuits

Total 18 Questions have been asked from Combinational circuits topic of Digital circuits subject in previous GATE papers. Average
marks 1.67.

GATE - 2016 (../../../../GATE2016) 01

Question No. 27 (../../../ECE-GATE-2016-Question-27)

The output of the combinational circuit given below is

 (A) A+B+C  (B) A(B+C)  (C) B(C+A)  (D) C(A+B)

Show Answer

GATE - 2016 (../../../../GATE2016) 02

Question No. 52 (../../../ECE-GATE-2016-Question-52)

Identify the circuit below.

 (A) Binary to Gray code converter  (B) Binary to XS3 converter  (C) Gray to Binary converter

 (D) XS3 to Binary converter

Show Answer

₹ 818 ₹ 3,279 ₹ 2,999 ₹ 7,499 ₹ 1,374 ₹ 4,400

GATE - 2016 (../../../../GATE2016) 02

Question No. 53 (../../../ECE-GATE-2016-Question-53)

The functionality implemented by the circuit below is

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 (A) 2-to-1 multiplexer  (B) 4-to-1 multiplexer  (C) 7-to-1 multiplexer  (D) 6-to-1 multiplexer

Show Answer

GATE - 2016 (../../../../GATE2016) 01

Question No. 128 (../../../ECE-GATE-2016-Question-128)

A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cin is the input
carry and Cout is the output carry. A and B are to be used as the select bits with A being the more signi cant select bit.

Which one of the following statements correctly describes the choice of signals to be connected to the inputs I0, I1, I2 and I3 so that
the output is Cout?

 (A) I0=0, I1=Cin, I2=Cin, and I3=1  (B) I0=1, I1=Cin, I2=Cin, and I3=1  (C) I0=Cin, I1=0, I2=1, and I3=Cin

 (D) I0=0, I1=Cin, I2=1, and I3=Cin

Show Answer

GATE - 2016 (../../../../GATE2016) 02

Question No. 254 (../../../ECE-GATE-2016-Question-254)

For the circuit shown in the gure, the delays of NOR gates, multiplexers and inverters are 2 ns,1.5 ns and 1 ns, respectively. If all
the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is __________

Enter Your Answer Here

Show Answer

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GATE - 2015 (../../../../GATE2015) 02

Question No. 148 (../../../ECE-GATE-2015-Question-148)

A 1-to-8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB) and Y
0
  to   Y
7
as the eight
demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable input E and address inputs A0 and A1) as shown
in the gure. Din, S0, S1 and S2 are to be connected to P,Q,R and S , but not necessarily in this order. The respective input
connections to P,Q,R and S terminals should be

 (A) S2, Din, S0, S1  (B) S1, Din, S0, S2  (C) Din, S0, S1, S2  (D) Din, S2, S0, S1

Show Answer

Question No. 126 (../../../ECE-GATE-2014-Question-126) GATE - 2014 (../../../../GATE2014) 01

In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Di erence (N = X - Y) are given by

 (A) M = X ⊕ Y , N = XY  (B) M = XY , N = X ⊕ Y  (C) M ¯¯

¯
= XY,N = X ⊕ Y

 (D) M ¯¯
¯,N = ¯
= XY ¯¯¯¯¯¯¯¯¯
X ⊕ Y

Show Answer

(C) M ¯¯
¯
= XY,N = X ⊕ Y

Subject : Digital circuits

Topic : Combinational circuits

Question No. 226 (../../../ECE-GATE-2014-Question-226) GATE - 2014 (../../../../GATE2014) 01

Consider the multiplexer based logic circuit shown in the gure.

Which one of the following Boolean functions is realized by the circuit?

 (A) F = W S1 S2  (B) F = W S1 + W S2 + S1 S2  (C) F = W S1 + W S2 + S1 S2

 (D) F ¯
¯¯¯
= W   ⊕ S1 ⊕ S2

Show Answer

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GATE - 2014 (../../../../GATE2014) 02

Question No. 251 (../../../ECE-GATE-2014-Question-251)

In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by

 (A) F ¯¯
¯ ¯
¯¯¯ ¯¯
¯ ¯¯
= WX + W X + Y Z
¯
 (B) F ¯¯
¯ ¯
¯¯¯ ¯¯
¯
= WX + W X + Y Z  (C) F ¯¯
¯ ¯¯
¯ ¯
¯¯¯
= W X Y + W XY
¯¯
¯

 (D) F ¯
¯¯¯ ¯¯
¯ ¯¯
¯ ¯¯
¯
= (W + X )Y  Z

Show Answer

GATE - 2014 (../../../../GATE2014) 02

Question No. 350 (../../../ECE-GATE-2014-Question-350)

An 8-to-1 multiplexer is used to implement a logical function Y as shown in the gure. The output Y is given by

 (A) Y ¯¯
¯ ¯¯
¯
= A B  C + A C  D  (B) Y ¯¯
¯ ¯¯
¯
= A  B C + A B  D  (C) Y ¯¯
¯ ¯¯
¯
= A B C + A  C  D

 (D) Y ¯¯
¯ ¯¯
¯ ¯¯
¯
= A  B  D + A B  C

Show Answer

GATE - 2012 (../../../../GATE2012) 01

Question No. 7 (../../../ECE-GATE-2012-Question-7)

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of
combinations for which the output is logic 1, is


 (A) 4  (B) 6  (C) 8  (D) 10

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Show Answer

GATE - 2011 (../../../../GATE2011) 01

Question No. 7 (../../../ECE-GATE-2011-Question-7)

The logic function implemented by the circuit below is (ground implies a logic "0")

 (A) F = AND(P,Q)  (B) F = OR (P,Q)  (C) F = XNOR (P,Q)  (D) F = XOR (P,Q)

Show Answer

GATE - 2010 (../../../../GATE2010) 02

Question No. 39 (../../../ECE-GATE-2010-Question-39)

The Boolean function realized by the logic circuit shown is

 (A) F= Σm(0,1,3,5,9,10,14)  (B) F= Σm(2,3,5,7,8,12,13)  (C) F= Σm(1,2,4,5,11,14,15)  (D) F= Σm(2,3,5,7,8,9,12)

Show Answer

GATE - 2009 (../../../../GATE2009) 02

Question No. 37 (../../../ECE-GATE-2009-Question-37)

What are the minimum number of 2-to-1 multiplexers required to generate a 2-input AND gate and a 2-input Ex-OR gate?

 (A) 1 and 2  (B) 1 and 3  (C) 1 and 1  (D) 2 and 2

Show Answer

GATE - 2009 (../../../../GATE2009) 02

Question No. 59 (../../../ECE-GATE-2009-Question-59)


Two products are sold from a vending machine, which has two push buttons P1 and P2. When a button is pressed, the price of the
corresponding product is displayed in a 7-segment display.
If no buttons are pressed, ‘0’ is displayed, signifying ‘Rs. 0’.
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If only P1 is pressed, ‘2’ is displayed, signifying ‘Rs. 2’.
If only P2 is pressed, ‘5’ is displayed, signifying ‘Rs. 5’.
If both P1 and P2 are pressed, ‘E’ is displayed, signifying ‘Error’.
The names of the segments in the 7-segment display, and the glow of the display for ‘0’, ‘2’, ‘5’ and ‘E’, are shown below

Consider
(i) push button pressed/not pressed is equivalent to logic 1/0 respectively
(ii) a segment glowing / not glowing in the display is equivalent to logic 1/0 respectively

If segments a to g are considered as functions of P1 and P2, then which of the following is correct?

P1 + P2, d = c + e
 (A) g = ¯  (B) g = P1 + P2, d = c + e P1 + P2, e = b + c
 (C) g = ¯  (D) g = P1 + P2, e = b + c
¯¯¯ ¯¯¯

Show Answer

Question No. 60 (../../../ECE-GATE-2009-Question-60) GATE - 2009 (../../../../GATE2009) 02

Two products are sold from a vending machine, which has two push buttons P1 and P2. When a button is pressed, the price of the
corresponding product is displayed in a 7-segment display.
If no buttons are pressed, ‘0’ is displayed, signifying ‘Rs. 0’.
If only P1 is pressed, ‘2’ is displayed, signifying ‘Rs. 2’.
If only P2 is pressed, ‘5’ is displayed, signifying ‘Rs. 5’.
If both P1 and P2 are pressed, ‘E’ is displayed, signifying ‘Error’.
The names of the segments in the 7-segment display, and the glow of the display for ‘0’, ‘2’, ‘5’ and ‘E’, are shown below

Consider
(i) push button pressed/not pressed is equivalent to logic 1/0 respectively
(ii) a segment glowing / not glowing in the display is equivalent to logic 1/0 respectively

What are the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the driver for this 7-segment
display?

 (A) 3 NOT and 4 OR  (B) 2 NOT and 4 OR  (C) 1 NOT and 3 OR  (D) 2 NOT and 3 OR

Show Answer

Question No. 58 (../../../ECE-GATE-2008-Question-58) GATE - 2008 (../../../../GATE2008) 02

For the circuit shown in the following gure I0-I3 are inputs to the 4:1 multiplexer R(MSB) and S are control bits

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The output Z can be represented by

 (A) P Q + P ¯¯
¯ ¯¯
¯ ¯¯
¯ ¯
QS+QR S  (B) P ¯¯
¯ ¯¯
¯ ¯
¯¯¯¯
Q+PQR +PQS
¯ ¯
 (C) P ¯¯
¯ ¯¯
¯ ¯
¯¯ ¯¯
¯ ¯¯
QR +PQR+PQRS+QR S
¯ ¯

 (D) P Q ¯¯
¯ ¯ ¯¯
¯ ¯¯
¯ ¯¯
¯ ¯¯
R +PQRS+PQR S+QR S
¯ ¯

Show Answer

GATE - 2007 (../../../../GATE2007) 02

Question No. 43 (../../../ECE-GATE-2007-Question-43)

In the following circuit, X is given by

 (A) X ¯¯
¯ ¯¯
¯ ¯¯
¯ ¯¯
¯ ¯¯
¯ ¯¯
¯
= AB C + A BC + A B C + ABC  (B) X ¯¯
¯ ¯¯
¯ ¯¯
¯ ¯¯
¯ ¯¯
¯ ¯¯
= A BC + AB C + ABC + A B C
¯

 (C) X = AB + BC + AC  (D) X ¯
¯B̄
= Ā ¯
¯ + B̄
¯¯C̄
¯
¯ + Ā
¯
¯C̄
¯
¯

Show Answer

Topics of Digital circuits

Boolean algebra (Boolean-algebra)

Minimization of Boolean functions

Logic gates (Llogic-gates)

Digital IC families (DTL, TTL, ECL, MOS, CMOS) (Digital-IC-families-DTL-TTL-ECL-MOS-CMOS)

Combinational circuits (Combinational-circuits)

Arithmetic circuits

Code converters

Multiplexers

Decoders

PROMs and PLAs

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Sequential circuits (Sequential-circuits)

Latches and ip- ops

Counters and shift-registers

Sample and hold circuits

ADCs, DACs (ADCs-DACs)

Semiconductor memories

Microprocessor(8085) (Microprocessor-8085)

8085 architecture

8085 programming (8085-programming)

8085 memory and IO interfacing (8085-memory-IO-interfacing)

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