dIy: project

PLL FM Transmitter
(PLL) method, making transmission
frequency rock-solid all the time, just
like commercial stations. Using DIP
switches, simply punch in the frequency
Joy Mukherji on which you wish to broadcast, and
you are on the air.

T
thuria
nidhi ka
his is a circuit that offers a chal-
lenge to electronics enthusiasts Circuit and working
and hobbyists—an FM trans- The circuit comprises two units. Unit
mitter that uses readily available com- band in 100kHz steps. The frequency 1 is the RF section of the transmitter,
ponents and covers the FM broadcast drift is controlled by phase-locked-loop shown in Fig. 1, which transmits the
FM signal. Unit 2 is the
A
TP1
PLL control section, shown
R1
B R3 C6 C7 C8 in Fig. 2, which helps in
RFC1* 33K 1n 1000u 1n
47K
25V L2# locking the transmission
frequency. The circuit uses
R8 ANT.
R2 47K L3# phase-lock loop that pro-
100K
S1 C1 C2 vides drift-free transmis-
22p TP2
POWER 470p T1 T2
VC1 sion frequency.
2N2222 2N2222
RFC2*
D1
L4# 50p The RF section is built
MV209 R7 around transistors T1-T4,
C3
CON1 15p
100E
R9 with T1 (2N2222) in Col-
12V L1#
C9 C4 C5 T3 T4
3.3K pitts oscillator configura-
100n R4
33K R5 15p 15p BF199 2N3866A tion. The frequency of the
330E WITH
JACK1 R6
TP0 HEATSINK oscillator is determined by
100E
AUDIO IN C coil L1 and capacitors C1,
D
GND
C2, C3 and C4. Modulating
S1 = ON/OFF SWITCH RFC1*, RFC2* AND L1# − L4# −− FOR DETAILS REFER TEXT
signal, which is in audio
Fig. 1: RF section of the transmitter (Unit 1) range, is fed through Jack1.
D1 is a varactor diode,
Parts List working in reverse-bias mode. Since
Semiconductors: C2 - 470pF ceramic disk
this is an FM transmitter, the devia-
IC1 - SAB6456A 64/256 prescaler C3-C5 - 15pF ceramic disk tion in the frequency of the oscillator
IC2 - 7805 voltage regulator C6, C8 - 1nF ceramic disk
is based on the amount of reverse-bias
IC3 - CD4059 programmable C7, C21 - 1000µF, 25V electrolytic
divide-by-N counter C9, C14, generated by the audio signal. Transis-
IC4 - CD4046 phase-locked-loop C18-C20, C22, tor T2 (2N2222) acts as a buffer that
(PLL) comparator C24 - 100nF ceramic disk
IC5 - CD4060 ripple carry binary C10, C15 - 10µF, 25V electrolytic isolates the oscillator from the rest of
counter/oscillator C11 - 200nF ceramic disk the amplifier chain.
IC6 - TL071 operational amplifier C12 - 400nF ceramic disk
T1, T2, T6 - 2N2222 npn transistor C13 - 220µF, 25V electrolytic Frequency-modulated signal is cou-
T3, T5 - BF199 npn transistor VC1 - 50pF trimmer capacitor pled to driver transistor T3 (BF199) via
T4 - 2N3866A npn transistor Miscellaneous:
D1 - MV209 varactor diode
capacitor C5. R7 is a current-limiting
RFC1 - 50T, 28SWG balun core
LED1 - 5mm LED RFC2 - 25T, 28SWG balun core resistor. Transistor T3 is wired as a
Resistors (all 1/4-watt, ±5% carbon): L1 - 4T, 4mm dia 26SWG Class A amplifier and drives transistor
R1, R8, R19-R31 - 47-kilo-ohm L2 - Broadband transformer
R2, R15 - 100-kilo-ohm 6T primary 26SWG, T4 (2N3866A) via broadband imped-
R3, R4 - 33-kilo-ohm 1T secondary, 20SWG ance matching transformer L2. Power
R5 - 330-ohm L3 - 13T, 8mm dia 26SWG
R6, R7 - 100-ohm air core amplifier operates in Class B mode. Coil
R9 - 3.3-kilo-ohm L4 - 6T, 8mm dia 26 SWG L4 and trimmer capacitor VC1 match
R10 - 18-kilo-ohm air core
R11, R12, R16 - 10-kilo-ohm CON-CON2 - 2-pin terminal connector
transistor T4’s collector to the antenna.
R13 - 220-ohm X TAL1 - 6.4MHz crystal The PLL control section is built
R14 - 2.2-kilo-ohm DIP1-DIP4 - DIP switch around 64/256 prescaler SAB6456A
R17 - 4.7-kilo-ohm S1, S2 - On/off switch
R18 - 1-mega-ohm - Audio input jack (IC1), programmable divide-by-N
VR1 - 100-kilo-ohm preset - Co-axial cable counter CD4059 (IC3), phase locked-
Capacitors: - Heat sink for transistor T4
C1, C16, C17 - 22pF, ceramic disk - Wire antenna loop comparator CD4046 (IC4), 14-stage
ripple carry binary counter/oscillator

72 December 2014 | Electronics For You www.efymag.com

 dIy: project

R12 10K
1
PCP_OUT VDD
16 R15 7
R14 R17
100K TP6
Q4
R11 2 ZENER 15 2.2K 4.7K 16
C12 PC1 V DD 5
10K Q5
400n 3 14 C24
COMP_IN SIG_IN 4
100n 12
Q6
RESET
4 13
1 OS N1 NC 8 VCO_OUT PC2 LED1 6
Q7
IN− 7 C13
2 Vcc+ 5 INH IC4 R2 12 11 IC5
IC6 220u 01 Q8 14
6 CD4046
3 A 6 C1A 11 25V CD4060
IN+ TL071 OUT 5
B R1 T6 R18 Q9 13
4 9
Vcc− OS N2 7 C1B 10 R13 2N2222 1M 00
SF_OUT 15
220E Q10
_
C11 8 Vss VCO_IN
9
C15 10
00 Q12 1
200n R16 X TAL1
10u
1 IC2 3 C14 10K 25V 6.4MHz 2
8 Q13
C10 7805 100n C17 C16 Vss
C23 Q14 3
10u 22p 22p
25V 100n
2

TP4
S2 C22
POWER 100n
R10 TP5
18K
C21 T5
1000u
CON2 BF199
23
24

13

25V
12V
VDD

OUT
L
Kb

VR1
100K
IC3
1

CL
11

CD4059
Ka Vss Kc
12

1
NC Vcc 8
C18
14

J16

J13

J12

J11

J10
J15

J14

J9

J8

J7

J6

J5

J4

J3

J2

J1
100n
2 IC1 QL 7
10

16

17

C
7

15

18

19

20

21

22

3
C1
D C20
SAB6456A
3 6 100n
C2 QH
C19
100n 5
4 VEE MC
TP3

GND R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31
4

1
OFF

R19 − R31 = 47K

OFF

1
OFF

OFF

DIP1 − DIP4 = DIP SWITCH

ON

ON

ON

ON
6

8
5

8
5

8
5

DIP1 1000’S DIP3 10’S DIP4 1’S

DIP2 100’S

Fig. 2: PLL control section (Unit 2)

CD4060 (IC5) and operational amplifier levels. The signal is further divided in
TL071 (IC6). programmable divide-by-N counter
PLL Transmitter Test Points
This section uses voltage regulator CD4059 (IC3). Output of CD4059 (pin Test point Details
7805 (IC2) to provide regulated power 23) is connected to the frequency com- TP0, TP3 0V (GND)
supply of 5V for the working of IC1. IC5 parator pin 3 of IC4. The PLL compara- TP1 +12V
generates 1.5625kHz reference frequency tor (IC4) compares the phase relation- TP2 Transmitted frequency
for the PLL at pin 1, which is fed to fre- ship between the reference signal on pin TP4 +5V
quency comparator (IC4) at pin 14. 14 with the input frequency on pin 3. TP5 Frequency as set by DIP1-DIP4
A low-level output is taken from the Depending upon the variance
TP6 1.5625kHz
antenna via limiting resistor R9 (shown (phase relationship) up or down, a cor-
Note: All measurements are w.r.t. GND
in Fig. 1), which is coupled to pin 2 of IC1 rection voltage is generated on pin 13
via capacitor C18. Pin 5 of IC1, the mode of IC4, which is applied to the varactor The reference frequency of the PLL
pin, is left open to select divide-by-64 diode of the VCO to bring it precisely is multiplied by the programmable
mode. Output frequency of the trans- to ‘on frequency.’ An active low-pass divider divide rate to give the final
mitter is divided by 64. Transistor T5 filter (IC6) removes audible 1.5625kHz frequency. If the divider rate is 1024
converts the output of IC1 to 12V CMOS reference tone from the control voltage. (as set by DIP switches DIP1-DIP4

www.efymag.com Electronics For You | December 2014 73

 dIy: project

Fig. 3: Actual-size PCB layout of RF section Fig. 4: Component layout of PCB of RF section

shown in Fig. 2), then the output will be

1.5625×1024×64 = 102.4MHz.
Similarly, a DIP setting of 1000 gives
us an output frequency of 100MHz.
LED1 lights up to indicate a lock on the
selected frequency.

Construction and testing

An actual-size, single-layer PCB layout
for Unit 1 is shown in Fig. 3 and its
component layout in Fig. 4. Single-
layer, actual-size PCB layout for Unit
2 is shown in Fig. 5 and its component
layout in Fig. 6.
Assemble the circuits on the PCBs to
save time and minimise assembly errors.
Unit 1 is connected to Unit 2 by a co-axial
cable of short length. Open end of resistor
R1, indicated as ‘A’ in Unit 1, is connected
Fig. 5: Actual-size PCB layout of PLL control section to pin 6 of IC6, indicated as ‘A’ in Unit 2,
by co-axial cable. Similarly, open end of
resistor R9, indicated as ‘C’ in Unit 1, is
connected to open end of C18, indicated as
‘C’ in Unit 2, by co-axial cable. Ground the
shield wire of the coaxial cable.
Keep all leads as short as possible.
To test the circuit for proper functioning,
connect stabilised 12V supply to both
the units. The circuit will accept audio
signal from just about anything (CD,
tape, iPod or computer) and transmit the
signal, which can be received by an FM
radio. An external microphone amplifier
can be used for speech. A good match-
ing 50-ohm ground-plane antenna will
greatly enhance the range of transmis-
sion. Use appropriate IC bases on the
PCB. 
The author is an electronics hobbyist and a small-
business owner in Albany, New York, USA. His
Fig. 6: Component layout of PCB of PLL control section interests include designing RF circuits

74 December 2014 | Electronics For You www.efymag.com